From 15d2ed1ef73d25f5df7407a359892131ef3ddf98 Mon Sep 17 00:00:00 2001 From: penguin Date: Sat, 26 Dec 2020 15:33:17 -0600 Subject: [PATCH] dpll and 12mhz osc0 working --- .../.igloo/target/same54p20a/Makefile | 3 +- .../same54p20a_test/ESF/modules/core/clocks.c | 388 +++++++++--------- .../same54p20a_test/ESF/modules/core/clocks.h | 2 +- test/same54p20a_test/ESF/modules/core/core.c | 13 + test/same54p20a_test/ESF/modules/core/core.h | 13 + .../same54p20a_test/ESF/modules/core/memory.c | 24 ++ .../same54p20a_test/ESF/modules/core/memory.h | 18 +- test/same54p20a_test/cfg/conf_core.h | 190 +++++---- test/same54p20a_test/inc/igloo.h | 2 - test/same54p20a_test/src/main.c | 141 +++---- 10 files changed, 447 insertions(+), 347 deletions(-) diff --git a/test/same54p20a_test/.igloo/target/same54p20a/Makefile b/test/same54p20a_test/.igloo/target/same54p20a/Makefile index f7c6a8b8..d0f938bb 100644 --- a/test/same54p20a_test/.igloo/target/same54p20a/Makefile +++ b/test/same54p20a_test/.igloo/target/same54p20a/Makefile @@ -94,7 +94,6 @@ ESF/mcu/src/system_same54.o \ ESF/modules/core/core.o \ ESF/modules/core/event.o \ ESF/modules/core/memory.o \ -ESF/modules/core/event.o \ ESF/modules/core/clocks.o \ ESF/modules/usart/usart.o \ src/main.o @@ -102,10 +101,10 @@ src/main.o OBJS_AS_ARGS+= \ $(QUOTE)ESF/mcu/src/startup_same54.o$(QUOTE) \ $(QUOTE)ESF/mcu/src/system_same54.o$(QUOTE) \ +$(QUOTE)ESF/modules/core/core.o$(QUOTE) \ $(QUOTE)ESF/modules/core/clocks.o$(QUOTE) \ $(QUOTE)ESF/modules/core/event.o$(QUOTE) \ $(QUOTE)ESF/modules/core/memory.o$(QUOTE) \ -$(QUOTE)ESF/modules/core/event.o$(QUOTE) \ $(QUOTE)ESF/modules/usart/usart.o$(QUOTE) \ $(QUOTE)src/main.o$(QUOTE) diff --git a/test/same54p20a_test/ESF/modules/core/clocks.c b/test/same54p20a_test/ESF/modules/core/clocks.c index 9c88a084..fe41ffd3 100644 --- a/test/same54p20a_test/ESF/modules/core/clocks.c +++ b/test/same54p20a_test/ESF/modules/core/clocks.c @@ -1,6 +1,6 @@ #include "clocks.h" #include "conf_core.h" -#include + void clock_osc32k_init(void) { #if CORE_CONF_CLK_XOSC32K_ENABLE == 1 @@ -25,6 +25,7 @@ void clock_osc32k_init(void) void clock_osc_init(void) { #if CORE_CONF_CLK_XOSC0_ENABLE == 1 + CRITICAL_SECTION_ENTER(); OSCCTRL->XOSCCTRL[0].bit.XTALEN = CORE_CONF_CLK_XOSC0_XTALEN; OSCCTRL->XOSCCTRL[0].bit.RUNSTDBY = CORE_CONF_CLK_XOSC0_RUNSTDBY; OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CORE_CONF_CLK_XOSC0_ONDEMAND; @@ -36,18 +37,13 @@ void clock_osc_init(void) OSCCTRL->XOSCCTRL[0].bit.CFDPRESC = CORE_CONF_CLK_XOSC0_CFDPRESC; OSCCTRL->XOSCCTRL[0].bit.SWBEN = CORE_CONF_CLK_XOSC0_SWBEN; OSCCTRL->XOSCCTRL[0].bit.STARTUP = CORE_CONF_CLK_XOSC0_STARTUP_TIME; + OSCCTRL->XOSCCTRL[0].bit.ENABLE = CORE_CONF_CLK_XOSC0_ENABLE; + CRITICAL_SECTION_LEAVE(); while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); - -#if CORE_CONF_CLK_XOSC0_ENALC == 1 - OSCCTRL->XOSCCTRL[0].bit.ENALC = CORE_CONF_CLK_XOSC0_ENALC; -#endif - -#if CORE_CONF_CLK_XOSC0_ONDEMAND == 1 - OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CORE_CONF_CLK_XOSC0_ONDEMAND; -#endif #endif #if CORE_CONF_CLK_XOSC1_ENABLE == 1 + CRITICAL_SECTION_ENTER(); OSCCTRL->XOSCCTRL[1].bit.XTALEN = CORE_CONF_CLK_XOSC1_XTALEN; OSCCTRL->XOSCCTRL[1].bit.RUNSTDBY = CORE_CONF_CLK_XOSC1_RUNSTDBY; OSCCTRL->XOSCCTRL[1].bit.LOWBUFGAIN = CORE_CONF_CLK_XOSC1_LOWBUFGAIN; @@ -57,8 +53,25 @@ void clock_osc_init(void) OSCCTRL->XOSCCTRL[1].bit.CFDPRESC = CORE_CONF_CLK_XOSC1_CFDPRESC; OSCCTRL->XOSCCTRL[1].bit.SWBEN = CORE_CONF_CLK_XOSC1_SWBEN; OSCCTRL->XOSCCTRL[1].bit.STARTUP = CORE_CONF_CLK_XOSC1_STARTUP_TIME; + OSCCTRL->XOSCCTRL[1].bit.ENABLE = CORE_CONF_CLK_XOSC1_ENABLE; + CRITICAL_SECTION_LEAVE(); while(0 == OSCCTRL->STATUS.bit.XOSCRDY1); +#endif + +#if CORE_CONF_CLK_XOSC0_ENABLE == 1 + CRITICAL_SECTION_ENTER(); +#if CORE_CONF_CLK_XOSC0_ENALC == 1 + OSCCTRL->XOSCCTRL[0].bit.ENALC = CORE_CONF_CLK_XOSC0_ENALC; +#endif +#if CORE_CONF_CLK_XOSC0_ONDEMAND == 1 + OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CORE_CONF_CLK_XOSC0_ONDEMAND; +#endif + CRITICAL_SECTION_LEAVE(); +#endif + +#if CORE_CONF_CLK_XOSC1_ENABLE == 1 + CRITICAL_SECTION_ENTER(); #if CORE_CONF_CLK_XOSC1_ENALC == 1 OSCCTRL->XOSCCTRL[1].bit.ENALC = CORE_CONF_CLK_XOSC1_ENALC; #endif @@ -66,57 +79,182 @@ void clock_osc_init(void) #if CORE_CONF_CLK_XOSC1_ONDEMAND == 1 OSCCTRL->XOSCCTRL[1].bit.ONDEMAND = CORE_CONF_CLK_XOSC1_ONDEMAND; #endif + CRITICAL_SECTION_LEAVE(); #endif } void clock_mclk_init(void) { - + CRITICAL_SECTION_ENTER(); + MCLK->CPUDIV.reg = CORE_CONF_MCLK_CPUDIV; + CRITICAL_SECTION_LEAVE(); } void clock_gclk_init(void) { - +#if CORE_CONF_GCLK_0_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[0].bit.DIV = CORE_CONF_GCLK_0_DIV_VAL; + GCLK->GENCTRL[0].bit.DIVSEL = CORE_CONF_GCLK_0_DIVSEL; + GCLK->GENCTRL[0].bit.RUNSTDBY = CORE_CONF_GCLK_0_RUN_IN_STANDBY; + GCLK->GENCTRL[0].bit.OE = CORE_CONF_GCLK_0_OUTPUT_ENABLE; + GCLK->GENCTRL[0].bit.OOV = CORE_CONF_GCLK_0_DIVSEL; + GCLK->GENCTRL[0].bit.IDC = CORE_CONF_GCLK_0_IDC; + GCLK->GENCTRL[0].bit.GENEN = CORE_CONF_GCLK_0_ENABLE; + GCLK->GENCTRL[0].bit.SRC = CORE_CONF_GCLK_0_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_1_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[1].bit.DIV = CORE_CONF_GCLK_1_DIV_VAL; + GCLK->GENCTRL[1].bit.DIVSEL = CORE_CONF_GCLK_1_DIVSEL; + GCLK->GENCTRL[1].bit.RUNSTDBY = CORE_CONF_GCLK_1_RUN_IN_STANDBY; + GCLK->GENCTRL[1].bit.OE = CORE_CONF_GCLK_1_OUTPUT_ENABLE; + GCLK->GENCTRL[1].bit.OOV = CORE_CONF_GCLK_1_DIVSEL; + GCLK->GENCTRL[1].bit.IDC = CORE_CONF_GCLK_1_IDC; + GCLK->GENCTRL[1].bit.GENEN = CORE_CONF_GCLK_1_ENABLE; + GCLK->GENCTRL[1].bit.SRC = CORE_CONF_GCLK_1_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_2_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[2].bit.DIV = CORE_CONF_GCLK_2_DIV_VAL; + GCLK->GENCTRL[2].bit.DIVSEL = CORE_CONF_GCLK_2_DIVSEL; + GCLK->GENCTRL[2].bit.RUNSTDBY = CORE_CONF_GCLK_2_RUN_IN_STANDBY; + GCLK->GENCTRL[2].bit.OE = CORE_CONF_GCLK_2_OUTPUT_ENABLE; + GCLK->GENCTRL[2].bit.OOV = CORE_CONF_GCLK_2_DIVSEL; + GCLK->GENCTRL[2].bit.IDC = CORE_CONF_GCLK_2_IDC; + GCLK->GENCTRL[2].bit.GENEN = CORE_CONF_GCLK_2_ENABLE; + GCLK->GENCTRL[2].bit.SRC = CORE_CONF_GCLK_2_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_3_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[3].bit.DIV = CORE_CONF_GCLK_3_DIV_VAL; + GCLK->GENCTRL[3].bit.DIVSEL = CORE_CONF_GCLK_3_DIVSEL; + GCLK->GENCTRL[3].bit.RUNSTDBY = CORE_CONF_GCLK_3_RUN_IN_STANDBY; + GCLK->GENCTRL[3].bit.OE = CORE_CONF_GCLK_3_OUTPUT_ENABLE; + GCLK->GENCTRL[3].bit.OOV = CORE_CONF_GCLK_3_DIVSEL; + GCLK->GENCTRL[3].bit.IDC = CORE_CONF_GCLK_3_IDC; + GCLK->GENCTRL[3].bit.GENEN = CORE_CONF_GCLK_3_ENABLE; + GCLK->GENCTRL[3].bit.SRC = CORE_CONF_GCLK_3_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_4_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[4].bit.DIV = CORE_CONF_GCLK_4_DIV_VAL; + GCLK->GENCTRL[4].bit.DIVSEL = CORE_CONF_GCLK_4_DIVSEL; + GCLK->GENCTRL[4].bit.RUNSTDBY = CORE_CONF_GCLK_4_RUN_IN_STANDBY; + GCLK->GENCTRL[4].bit.OE = CORE_CONF_GCLK_4_OUTPUT_ENABLE; + GCLK->GENCTRL[4].bit.OOV = CORE_CONF_GCLK_4_DIVSEL; + GCLK->GENCTRL[4].bit.IDC = CORE_CONF_GCLK_4_IDC; + GCLK->GENCTRL[4].bit.GENEN = CORE_CONF_GCLK_4_ENABLE; + GCLK->GENCTRL[4].bit.SRC = CORE_CONF_GCLK_4_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_5_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[5].bit.DIV = CORE_CONF_GCLK_5_DIV_VAL; + GCLK->GENCTRL[5].bit.DIVSEL = CORE_CONF_GCLK_5_DIVSEL; + GCLK->GENCTRL[5].bit.RUNSTDBY = CORE_CONF_GCLK_5_RUN_IN_STANDBY; + GCLK->GENCTRL[5].bit.OE = CORE_CONF_GCLK_5_OUTPUT_ENABLE; + GCLK->GENCTRL[5].bit.OOV = CORE_CONF_GCLK_5_DIVSEL; + GCLK->GENCTRL[5].bit.IDC = CORE_CONF_GCLK_5_IDC; + GCLK->GENCTRL[5].bit.GENEN = CORE_CONF_GCLK_5_ENABLE; + GCLK->GENCTRL[5].bit.SRC = CORE_CONF_GCLK_5_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_6_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[6].bit.DIV = CORE_CONF_GCLK_6_DIV_VAL; + GCLK->GENCTRL[6].bit.DIVSEL = CORE_CONF_GCLK_6_DIVSEL; + GCLK->GENCTRL[6].bit.RUNSTDBY = CORE_CONF_GCLK_6_RUN_IN_STANDBY; + GCLK->GENCTRL[6].bit.OE = CORE_CONF_GCLK_6_OUTPUT_ENABLE; + GCLK->GENCTRL[6].bit.OOV = CORE_CONF_GCLK_6_DIVSEL; + GCLK->GENCTRL[6].bit.IDC = CORE_CONF_GCLK_6_IDC; + GCLK->GENCTRL[6].bit.GENEN = CORE_CONF_GCLK_6_ENABLE; + GCLK->GENCTRL[6].bit.SRC = CORE_CONF_GCLK_6_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_7_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[7].bit.DIV = CORE_CONF_GCLK_7_DIV_VAL; + GCLK->GENCTRL[7].bit.DIVSEL = CORE_CONF_GCLK_7_DIVSEL; + GCLK->GENCTRL[7].bit.RUNSTDBY = CORE_CONF_GCLK_7_RUN_IN_STANDBY; + GCLK->GENCTRL[7].bit.OE = CORE_CONF_GCLK_7_OUTPUT_ENABLE; + GCLK->GENCTRL[7].bit.OOV = CORE_CONF_GCLK_7_DIVSEL; + GCLK->GENCTRL[7].bit.IDC = CORE_CONF_GCLK_7_IDC; + GCLK->GENCTRL[7].bit.GENEN = CORE_CONF_GCLK_7_ENABLE; + GCLK->GENCTRL[7].bit.SRC = CORE_CONF_GCLK_7_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_8_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[8].bit.DIV = CORE_CONF_GCLK_8_DIV_VAL; + GCLK->GENCTRL[8].bit.DIVSEL = CORE_CONF_GCLK_8_DIVSEL; + GCLK->GENCTRL[8].bit.RUNSTDBY = CORE_CONF_GCLK_8_RUN_IN_STANDBY; + GCLK->GENCTRL[8].bit.OE = CORE_CONF_GCLK_8_OUTPUT_ENABLE; + GCLK->GENCTRL[8].bit.OOV = CORE_CONF_GCLK_8_DIVSEL; + GCLK->GENCTRL[8].bit.IDC = CORE_CONF_GCLK_8_IDC; + GCLK->GENCTRL[8].bit.GENEN = CORE_CONF_GCLK_8_ENABLE; + GCLK->GENCTRL[8].bit.SRC = CORE_CONF_GCLK_8_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_9_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[9].bit.DIV = CORE_CONF_GCLK_9_DIV_VAL; + GCLK->GENCTRL[9].bit.DIVSEL = CORE_CONF_GCLK_9_DIVSEL; + GCLK->GENCTRL[9].bit.RUNSTDBY = CORE_CONF_GCLK_9_RUN_IN_STANDBY; + GCLK->GENCTRL[9].bit.OE = CORE_CONF_GCLK_9_OUTPUT_ENABLE; + GCLK->GENCTRL[9].bit.OOV = CORE_CONF_GCLK_9_DIVSEL; + GCLK->GENCTRL[9].bit.IDC = CORE_CONF_GCLK_9_IDC; + GCLK->GENCTRL[9].bit.GENEN = CORE_CONF_GCLK_9_ENABLE; + GCLK->GENCTRL[9].bit.SRC = CORE_CONF_GCLK_9_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_10_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[10].bit.DIV = CORE_CONF_GCLK_10_DIV_VAL; + GCLK->GENCTRL[10].bit.DIVSEL = CORE_CONF_GCLK_10_DIVSEL; + GCLK->GENCTRL[10].bit.RUNSTDBY = CORE_CONF_GCLK_10_RUN_IN_STANDBY; + GCLK->GENCTRL[10].bit.OE = CORE_CONF_GCLK_10_OUTPUT_ENABLE; + GCLK->GENCTRL[10].bit.OOV = CORE_CONF_GCLK_10_DIVSEL; + GCLK->GENCTRL[10].bit.IDC = CORE_CONF_GCLK_10_IDC; + GCLK->GENCTRL[10].bit.GENEN = CORE_CONF_GCLK_10_ENABLE; + GCLK->GENCTRL[10].bit.SRC = CORE_CONF_GCLK_10_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif +#if CORE_CONF_GCLK_11_ENABLE == 1 + CRITICAL_SECTION_ENTER(); + GCLK->GENCTRL[11].bit.DIV = CORE_CONF_GCLK_11_DIV_VAL; + GCLK->GENCTRL[11].bit.DIVSEL = CORE_CONF_GCLK_11_DIVSEL; + GCLK->GENCTRL[11].bit.RUNSTDBY = CORE_CONF_GCLK_11_RUN_IN_STANDBY; + GCLK->GENCTRL[11].bit.OE = CORE_CONF_GCLK_11_OUTPUT_ENABLE; + GCLK->GENCTRL[11].bit.OOV = CORE_CONF_GCLK_11_DIVSEL; + GCLK->GENCTRL[11].bit.IDC = CORE_CONF_GCLK_11_IDC; + GCLK->GENCTRL[11].bit.GENEN = CORE_CONF_GCLK_11_ENABLE; + GCLK->GENCTRL[11].bit.SRC = CORE_CONF_GCLK_11_CLOCK_SOURCE; + CRITICAL_SECTION_LEAVE(); +#endif } void clock_dpll_init(void) { #if CORE_CONF_CLK_DPLL0_ENABLE == 1 - uint32_t volatile *atomic0 = NULL; #if CORE_CONF_CLK_DPLL0_REFCLK == 0 - // enter critical - *atomic0 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.GEN = GCLK_PCHCTRL_GEN(CORE_CONF_CLK_DPLL0_GCLK_SRC); GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.CHEN = CORE_CONF_CLK_DPLL0_ENABLE; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); + CRITICAL_SECTION_LEAVE(); #endif - // enter critical - *atomic0 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // write dpll ratio OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = CORE_CONF_CLK_DPLL0_LDRFRAC_VAL; OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = CORE_CONF_CLK_DPLL0_LDR_VAL; - // leave critical - __DMB(); - __set_PRIMASK(*atomic0); - - // enter critical again - *atomic0 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - // write dpll ctrlb OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = CORE_CONF_CLK_DPLL0_DIV_VAL; OSCCTRL->Dpll[0].DPLLCTRLB.bit.DCOEN = CORE_CONF_CLK_DPLL0_DCOEN; @@ -128,48 +266,23 @@ void clock_dpll_init(void) OSCCTRL->Dpll[0].DPLLCTRLB.bit.FILTER = CORE_CONF_CLK_DPLL0_FILTER; OSCCTRL->Dpll[0].DPLLCTRLA.bit.RUNSTDBY = CORE_CONF_CLK_DPLL0_RUNSTDBY; OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = CORE_CONF_CLK_DPLL0_ENABLE; - - __DMB(); - __set_PRIMASK(*atomic0); - + CRITICAL_SECTION_LEAVE(); #endif #if CORE_CONF_CLK_DPLL1_ENABLE == 1 - uint32_t volatile *atomic1 = NULL; #if CORE_CONF_CLK_DPLL0_REFCLK == 0 - // enter critical - *atomic1 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.GEN = GCLK_PCHCTRL_GEN(CORE_CONF_CLK_DPLL1_GCLK_SRC); GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.CHEN = CORE_CONF_CLK_DPLL1_ENABLE; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic1); + CRITICAL_SECTION_LEAVE(); #endif - // enter critical - *atomic1 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // write dpll ratio OSCCTRL->Dpll[1].DPLLRATIO.bit.LDRFRAC = CORE_CONF_CLK_DPLL1_LDRFRAC_VAL; OSCCTRL->Dpll[1].DPLLRATIO.bit.LDR = CORE_CONF_CLK_DPLL1_LDR_VAL; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic1); - - // enter critical again - *atomic1 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - // write dpll ctrlb OSCCTRL->Dpll[1].DPLLCTRLB.bit.DIV = CORE_CONF_CLK_DPLL1_DIV_VAL; OSCCTRL->Dpll[1].DPLLCTRLB.bit.DCOEN = CORE_CONF_CLK_DPLL1_DCOEN; @@ -181,169 +294,88 @@ void clock_dpll_init(void) OSCCTRL->Dpll[1].DPLLCTRLB.bit.FILTER = CORE_CONF_CLK_DPLL1_FILTER; OSCCTRL->Dpll[1].DPLLCTRLA.bit.RUNSTDBY = CORE_CONF_CLK_DPLL1_RUNSTDBY; OSCCTRL->Dpll[1].DPLLCTRLA.bit.ENABLE = CORE_CONF_CLK_DPLL1_ENABLE; - - __DMB(); - __set_PRIMASK(*atomic1); - + CRITICAL_SECTION_LEAVE(); #endif #if CORE_CONF_CLK_DPLL0_ENABLE == 1 while(!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY)); - - // enter critical - *atomic0 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); #if CORE_CONF_CLK_DPLL0_ONDEMAND == 1 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = CORE_CONF_CLK_DPLL0_ONDEMAND; #endif - - // leave critical - __DMB(); - __set_PRIMASK(*atomic0); - + CRITICAL_SECTION_LEAVE(); #endif #if CORE_CONF_CLK_DPLL1_ENABLE == 1 while(!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY)); - - // enter critical - *atomic1 = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); #if CORE_CONF_CLK_DPLL1_ONDEMAND == 1 OSCCTRL->Dpll[1].DPLLCTRLA.bit.ONDEMAND = CORE_CONF_CLK_DPLL1_ONDEMAND; #endif - - // leave critical - __DMB(); - __set_PRIMASK(*atomic1); - + CRITICAL_SECTION_LEAVE(); #endif } void clock_dfll_init(void) { #if CORE_CONF_CLK_DFLL_ENABLE - // enter critical - uint32_t volatile *atomic = NULL; - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K; + CRITICAL_SECTION_LEAVE(); while(GCLK->SYNCBUSY.bit.GENCTRL0); - // leave critical - __DMB(); - __set_PRIMASK(*atomic); - - // enter critical again - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // reset stuff OSCCTRL->DFLLCTRLA.reg = 0; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); - + CRITICAL_SECTION_LEAVE(); #if CORE_CONF_CLK_DFLL_USBCRM != 1 && CORE_CONF_CLK_DFLL_MODE != 0 - // enter critical - atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // reset stuff GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.GEN = GCLK_PCHCTRL_GEN(CORE_CONF_CLK_DFLL_GCLK_SRC); GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.EN = CORE_CONF_CLK_DFLL_ENABLE; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); + CRITICAL_SECTION_LEAVE(); #endif - // enter critical again - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // configure clock multiplier stuff OSCCTRL->DFLLMUL.bit.MUL = CORE_CONF_CLK_DFLL_MUL_VAL; OSCCTRL->DFLLMUL.bit.CSTEP = CORE_CONF_CLK_DFLL_CSTEP_VAL; OSCCTRL->DFLLMUL.bit.FSTEP = CORE_CONF_CLK_DFLL_FSTEP_VAL; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); - + CRITICAL_SECTION_LEAVE(); while(OSCCTRL->DFLLSYNC.bit.DFLLMUL); - // enter critical again - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // reset dfll ctrlb OSCCTRL->DFLLCTRLB.reg = 0; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); - + CRITICAL_SECTION_LEAVE(); // wait for ctrlb sync while(OSCCTRL->DFLLSYNC.bit.DFLLCTRLB); #if CORE_CONF_CLK_DFLL_OVERWRITE_CAL == 1 - // enter critical - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // set calib for dfll48m OSCCTRL->DFLLVAL.bit.COARSE = CORE_CONF_CLK_DFLL_COARSE_VAL; OSCCTRL->DFLLVAL.bit.FINE = CORE_CONF_CLK_DFLL_FINE_VAL; OSCCTRL->DFLLVAL.bit.DIFF = CORE_CONF_CLK_DFLL_DIFF_VAL; - - __DMB(); - __set_PRIMASK(*atomic); + CRITICAL_SECTION_LEAVE(); #endif - // enter critical - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // write dfll val // rewriting this for some reason? OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); - + CRITICAL_SECTION_LEAVE(); // let dfll val sync while(OSCCTRL->DFLLSYNC.bit.DFLLVAL); - // enter critical again - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); // write dfll ctrlb OSCCTRL->DFLLCTRLB.bit.WAITLOCK = CORE_CONF_CLK_DFLL_WAITLOCK; OSCCTRL->DFLLCTRLB.bit.QLDIS = CORE_CONF_CLK_DFLL_QLDIS; OSCCTRL->DFLLCTRLB.bit.USBCRM = CORE_CONF_CLK_DFLL_USBCRM; OSCCTRL->DFLLCTRLB.bit.STABLE = CORE_CONF_CLK_DFLL_STABLE_FCALIB; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); + CRITICAL_SECTION_LEAVE(); if (OSCCTRL->DFLLCTRLB.bit.MODE) { @@ -355,31 +387,15 @@ void clock_dfll_init(void) } #if CORE_CONF_CLK_DFLL_ONDEMAND == 1 - // enter critical - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - + CRITICAL_SECTION_ENTER(); OSCCTRL->DFLLCTRLA.bit.ONDEMAND = CORE_CONF_CLK_DFLL_ONDEMAND; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); + CRITICAL_SECTION_LEAVE(); #endif while(GCLK->SYNCBUSY.reg); - - // enter critical - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); - - + CRITICAL_SECTION_ENTER(); // reset gclk 0 GCLK->GENCTRL[0].bit.SRC = CORE_CONF_GCLK_0_CLOCK_SOURCE; - - // leave critical - __DMB(); - __set_PRIMASK(*atomic); + CRITICAL_SECTION_LEAVE(); #endif } diff --git a/test/same54p20a_test/ESF/modules/core/clocks.h b/test/same54p20a_test/ESF/modules/core/clocks.h index 0559f84e..e346f845 100644 --- a/test/same54p20a_test/ESF/modules/core/clocks.h +++ b/test/same54p20a_test/ESF/modules/core/clocks.h @@ -1,7 +1,7 @@ #ifndef _CLOCKS_H_ #define _CLOCKS_H_ -#include "sam.h" +#include "core.h" // XOSC32K Definitions #define CORE_CONF_CLK_XOSC32KCTRL_CGM_STD_MODE (0x1) diff --git a/test/same54p20a_test/ESF/modules/core/core.c b/test/same54p20a_test/ESF/modules/core/core.c index 8812ffaf..bda27143 100644 --- a/test/same54p20a_test/ESF/modules/core/core.c +++ b/test/same54p20a_test/ESF/modules/core/core.c @@ -27,3 +27,16 @@ void mcu_init(void) // cache init mem_cache_init(); } + +void atomic_enter_critical(uint32_t volatile* atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +void atomic_leave_critical(uint32_t volatile* atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} diff --git a/test/same54p20a_test/ESF/modules/core/core.h b/test/same54p20a_test/ESF/modules/core/core.h index b49ca145..3b2e8293 100644 --- a/test/same54p20a_test/ESF/modules/core/core.h +++ b/test/same54p20a_test/ESF/modules/core/core.h @@ -1,6 +1,19 @@ #ifndef _CORE_H_ #define _CORE_H_ +#include "sam.h" + void mcu_init(void); +void atomic_enter_critical(uint32_t volatile* atomic); +void atomic_leave_critical(uint32_t volatile* atomic); + +#define CRITICAL_SECTION_ENTER() \ + {\ + volatile uint32_t __atomic;\ + atomic_enter_critical(&__atomic); + +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } #endif diff --git a/test/same54p20a_test/ESF/modules/core/memory.c b/test/same54p20a_test/ESF/modules/core/memory.c index 8c5815ea..ad09c2eb 100644 --- a/test/same54p20a_test/ESF/modules/core/memory.c +++ b/test/same54p20a_test/ESF/modules/core/memory.c @@ -1,2 +1,26 @@ #include "memory.h" +#include "conf_core.h" + +void mem_nvm_init(void) +{ + CRITICAL_SECTION_ENTER(); + NVMCTRL->CTRLA.bit.RWS = CORE_CONF_MCLK_NVM_WAIT_STATE; + CRITICAL_SECTION_LEAVE(); +} + +void mem_cache_init(void) +{ +#if CORE_CONF_CMCC_ENABLE == 1 + +#endif +} + +void mem_dma_init(void) +{ +#if CORE_CONF_DMA_ENABLE + CRITICAL_SECTION_ENTER(); + MCLK->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + CRITICAL_SECTION_LEAVE(); +#endif +} diff --git a/test/same54p20a_test/ESF/modules/core/memory.h b/test/same54p20a_test/ESF/modules/core/memory.h index 890ac463..5704a7b3 100644 --- a/test/same54p20a_test/ESF/modules/core/memory.h +++ b/test/same54p20a_test/ESF/modules/core/memory.h @@ -1,19 +1,9 @@ #ifndef _MEMORY_H_ #define _MEMORY_H_ -static inline void mem_nvm_init(void) -{ - -} - -static inline void mem_cache_init(void) -{ - -} - -static inline void mem_dma_init(void) -{ - -} +#include "core.h" +void mem_nvm_init(void); +void mem_cache_init(void); +void mem_dma_init(void); #endif diff --git a/test/same54p20a_test/cfg/conf_core.h b/test/same54p20a_test/cfg/conf_core.h index 12eedc3f..ed1e324c 100644 --- a/test/same54p20a_test/cfg/conf_core.h +++ b/test/same54p20a_test/cfg/conf_core.h @@ -2,6 +2,17 @@ #define _CONF_CLOCKS_H_ #include "clocks.h" +#define CORE_CONF_MCLK_NVM_WAIT_STATE 0x0 +#define CORE_CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val + +// DMA Config +#define CORE_CONF_DMA_ENABLE (0) +// Cache Config +#define CORE_CONF_CMCC_ENABLE (0) +// Event Port Configs +#define CORE_CONF_PORT_EVCTRL_0_ENABLE (0) +#define CORE_CONF_PORT_EVCTRL_1_ENABLE (0) +#define CORE_CONF_PORT_EVCTRL_2_ENABLE (0) // XOSC0 Config #define CORE_CONF_CLK_XOSC0_ENABLE (1) #define CORE_CONF_CLK_XOSC0_XTALEN (1) @@ -11,10 +22,10 @@ #define CORE_CONF_CLK_XOSC0_IPTAT CORE_CONF_CLK_XOSCCTRL_IPTAT_8MHZ_TO_16MHZ #define CORE_CONF_CLK_XOSC0_IMULT CORE_CONF_CLK_XOSCCTRL_IMULT_8MHZ_TO_16MHZ #define CORE_CONF_CLK_XOSC0_ENALC (1) -#define CORE_CONF_CLK_XOSC0_CFDEN (0) +#define CORE_CONF_CLK_XOSC0_CFDEN (1) #define CORE_CONF_CLK_XOSC0_SWBEN (0) #define CORE_CONF_CLK_XOSC0_STARTUP_TIME CORE_CONF_CLK_XOSCCTRL_STARTUP_31us -#define CORE_CONF_CLK_XOSC0_CFDPRESC (0) +#define CORE_CONF_CLK_XOSC0_CFDPRESC (0x03) // XOSC1 Config #define CORE_CONF_CLK_XOSC1_ENABLE (0) @@ -31,21 +42,21 @@ #define CORE_CONF_CLK_XOSC1_CFDPRESC (0) // XOSC32K Config -#define CORE_CONF_CLK_XOSC32K_ENABLE (1) +#define CORE_CONF_CLK_XOSC32K_ENABLE (0) #define CORE_CONF_CLK_XOSC32K_CGM CORE_CONF_CLK_XOSC32KCTRL_CGM_STD_MODE #define CORE_CONF_CLK_XOSC32K_WRTLOCK (0) #define CORE_CONF_CLK_XOSC32K_STARTUP_TIME CORE_CONF_CLK_XOSC32KCTRL_STARTUP_62592us #define CORE_CONF_CLK_XOSC32K_ONDEMAND (0) -#define CORE_CONF_CLK_XOSC32K_RUNSTDBY (1) +#define CORE_CONF_CLK_XOSC32K_RUNSTDBY (0) #define CORE_CONF_CLK_XOSC32K_EN1K (0) -#define CORE_CONF_CLK_XOSC32K_EN32K (1) -#define CORE_CONF_CLK_XOSC32K_XTALEN (1) +#define CORE_CONF_CLK_XOSC32K_EN32K (0) +#define CORE_CONF_CLK_XOSC32K_XTALEN (0) #define CORE_CONF_CLK_XOSC32K_CFDPRESC (0) #define CORE_CONF_CLK_XOSC32K_CFDEN (0) #define CORE_CONF_CLK_XOSC32K_SWBACK (0) // DFLL Config -#define CORE_CONF_CLK_DFLL_ENABLE (1) +#define CORE_CONF_CLK_DFLL_ENABLE (0) #define CORE_CONF_CLK_DFLL_RUNSTDBY (0) #define CORE_CONF_CLK_DFLL_ONDEMAND (0) #define CORE_CONF_CLK_DFLL_WAITLOCK (0) @@ -61,22 +72,21 @@ #define CORE_CONF_CLK_DFLL_FINE_VAL 128 #define CORE_CONF_CLK_DFLL_CSTEP_VAL 1 #define CORE_CONF_CLK_DFLL_FSTEP_VAL 1 -#define CORE_CONF_CLK_DFLL_MUL_VAL 1465 +#define CORE_CONF_CLK_DFLL_MUL_VAL 1 #define CORE_CONF_CLK_DFLL_GCLK_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #define CORE_CONF_CLK_DFLL_OVERWRITE_CAL 0 // DPLL0 Config #define CORE_CONF_CLK_DPLL0_ENABLE (1) -#define CORE_CONF_CLK_DPLL0_ONDEMAND (1) +#define CORE_CONF_CLK_DPLL0_ONDEMAND (0) #define CORE_CONF_CLK_DPLL0_RUNSTDBY (0) #define CORE_CONF_CLK_DPLL0_LDRFRAC_VAL 0 -#define CORE_CONF_CLK_DPLL0_LDR_VAL 0 -#define CORE_CONF_CLK_DPLL0_DIV_VAL 0 +#define CORE_CONF_CLK_DPLL0_LDR_VAL (119) +#define CORE_CONF_CLK_DPLL0_DIV_VAL (5) #define CORE_CONF_CLK_DPLL0_DCOEN 0 #define CORE_CONF_CLK_DPLL0_DCOFILTER CORE_CONF_CLK_DPLLCTRL_DCOFILTER_3210KHZ #define CORE_CONF_CLK_DPLL0_LBYPASS 0 #define CORE_CONF_CLK_DPLL0_LTIME 0 -#define CORE_CONF_CLK_DPLL0_DIV_VAL 0 #define CORE_CONF_CLK_DPLL0_WUF 0 #define CORE_CONF_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0 #define CORE_CONF_CLK_DPLL0_REFCLK CORE_CONF_CLK_DPLLCTRL_REFCLK_XOSC0 @@ -103,80 +113,116 @@ * When in doubt, leave this at its default. */ #define CORE_CONF_CLK_DPLL0_FILTER 0x0 + // DPLL1 Config // GCLK Generators Config -#define CORE_CONF_GCLK_0_ENABLE false -#define CORE_CONF_GCLK_0_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_0_ENABLE 1 +#define CORE_CONF_GCLK_0_RUN_IN_STANDBY 1 #define CORE_CONF_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_0_PRESCALER 1 -#define CORE_CONF_GCLK_0_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_1_ENABLE false -#define CORE_CONF_GCLK_1_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_0_DIV_VAL 1 +#define CORE_CONF_GCLK_0_DIVSEL 0 +#define CORE_CONF_GCLK_0_OUTPUT_ENABLE 1 +#define CORE_CONF_GCLK_0_OUTPUT_OFF_VALUE 1 +#define CORE_CONF_GCLK_0_IDC 1 + +#define CORE_CONF_GCLK_1_ENABLE 0 +#define CORE_CONF_GCLK_1_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_1_PRESCALER 1 -#define CORE_CONF_GCLK_1_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_2_ENABLE false -#define CORE_CONF_GCLK_2_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_1_DIV_VAL 1 +#define CORE_CONF_GCLK_1_DIVSEL 0 +#define CORE_CONF_GCLK_1_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_1_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_1_IDC 0 + +#define CORE_CONF_GCLK_2_ENABLE 0 +#define CORE_CONF_GCLK_2_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_2_PRESCALER 1 -#define CORE_CONF_GCLK_2_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_3_ENABLE false -#define CORE_CONF_GCLK_3_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_2_DIV_VAL 1 +#define CORE_CONF_GCLK_2_DIVSEL 0 +#define CORE_CONF_GCLK_2_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_2_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_2_IDC 0 + +#define CORE_CONF_GCLK_3_ENABLE 0 +#define CORE_CONF_GCLK_3_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_3_PRESCALER 1 -#define CORE_CONF_GCLK_3_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_4_ENABLE false -#define CORE_CONF_GCLK_4_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_3_DIV_VAL 1 +#define CORE_CONF_GCLK_3_DIVSEL 0 +#define CORE_CONF_GCLK_3_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_3_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_3_IDC 0 + +#define CORE_CONF_GCLK_4_ENABLE 0 +#define CORE_CONF_GCLK_4_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_4_PRESCALER 1 -#define CORE_CONF_GCLK_4_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_5_ENABLE false -#define CORE_CONF_GCLK_5_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_4_DIV_VAL 1 +#define CORE_CONF_GCLK_4_DIVSEL 1 +#define CORE_CONF_GCLK_4_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_4_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_4_IDC 0 + +#define CORE_CONF_GCLK_5_ENABLE 0 +#define CORE_CONF_GCLK_5_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_5_PRESCALER 1 -#define CORE_CONF_GCLK_5_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_6_ENABLE false -#define CORE_CONF_GCLK_6_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_5_DIV_VAL 1 +#define CORE_CONF_GCLK_5_DIVSEL 0 +#define CORE_CONF_GCLK_5_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_5_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_5_IDC 0 + +#define CORE_CONF_GCLK_6_ENABLE 0 +#define CORE_CONF_GCLK_6_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_6_PRESCALER 1 -#define CORE_CONF_GCLK_6_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_7_ENABLE false -#define CORE_CONF_GCLK_7_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_6_DIV_VAL 1 +#define CORE_CONF_GCLK_6_DIVSEL 0 +#define CORE_CONF_GCLK_6_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_6_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_6_IDC 0 + +#define CORE_CONF_GCLK_7_ENABLE 0 +#define CORE_CONF_GCLK_7_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_7_PRESCALER 1 -#define CORE_CONF_GCLK_7_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_8_ENABLE false -#define CORE_CONF_GCLK_8_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_7_DIV_VAL 1 +#define CORE_CONF_GCLK_7_DIVSEL 0 +#define CORE_CONF_GCLK_7_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_7_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_7_IDC 0 + +#define CORE_CONF_GCLK_8_ENABLE 0 +#define CORE_CONF_GCLK_8_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_8_PRESCALER 1 -#define CORE_CONF_GCLK_8_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_9_ENABLE false -#define CORE_CONF_GCLK_9_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_8_DIV_VAL 1 +#define CORE_CONF_GCLK_8_DIVSEL 0 +#define CORE_CONF_GCLK_8_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_8_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_8_IDC 0 + +#define CORE_CONF_GCLK_9_ENABLE 0 +#define CORE_CONF_GCLK_9_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_9_PRESCALER 1 -#define CORE_CONF_GCLK_9_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_10_ENABLE false -#define CORE_CONF_GCLK_10_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_9_DIV_VAL 1 +#define CORE_CONF_GCLK_9_DIVSEL 0 +#define CORE_CONF_GCLK_9_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_9_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_9_IDC 0 + +#define CORE_CONF_GCLK_10_ENABLE 0 +#define CORE_CONF_GCLK_10_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_10_PRESCALER 1 -#define CORE_CONF_GCLK_10_OUTPUT_ENABLE false - -#define CORE_CONF_GCLK_11_ENABLE false -#define CORE_CONF_GCLK_11_RUN_IN_STANDBY false +#define CORE_CONF_GCLK_10_DIV_VAL 1 +#define CORE_CONF_GCLK_10_DIVSEL 0 +#define CORE_CONF_GCLK_10_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_10_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_10_IDC 0 + +#define CORE_CONF_GCLK_11_ENABLE 0 +#define CORE_CONF_GCLK_11_RUN_IN_STANDBY 0 #define CORE_CONF_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 -#define CORE_CONF_GCLK_11_PRESCALER 1 -#define CORE_CONF_GCLK_11_OUTPUT_ENABLE false - +#define CORE_CONF_GCLK_11_DIV_VAL 1 +#define CORE_CONF_GCLK_11_DIVSEL 0 +#define CORE_CONF_GCLK_11_OUTPUT_ENABLE 0 +#define CORE_CONF_GCLK_11_OUTPUT_OFF_VALUE 0 +#define CORE_CONF_GCLK_11_IDC 0 diff --git a/test/same54p20a_test/inc/igloo.h b/test/same54p20a_test/inc/igloo.h index 94aab0d0..3ab4504d 100644 --- a/test/same54p20a_test/inc/igloo.h +++ b/test/same54p20a_test/inc/igloo.h @@ -1,5 +1,3 @@ #ifdef __SAME54P20A__ #include "sam.h" #endif - -#include "conf_core.h" diff --git a/test/same54p20a_test/src/main.c b/test/same54p20a_test/src/main.c index cbeb5eea..38f87b03 100644 --- a/test/same54p20a_test/src/main.c +++ b/test/same54p20a_test/src/main.c @@ -1,76 +1,77 @@ #include "igloo.h" - +#include "core.h" int main() { - // HRI_NVMCTRL_SET_CTRLA_RWS_bf - // osc32kctrl_init - // oscctrl_init - // mclk_init - // if GCLK_INIT_1ST - // gclk_init_generators_by_freq FIRST - // endif - // oscctrl_init_referenced_generators - // gclk_init_generators_by_fref LAST - // - // if dmac enable - // hri_mclk_set_AHBMASK_DMAC_bit - // dma init - // endif - - - // if CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | 2 | 3 - // port event init - // endif - - // if CONF_CMCC_ENABLE - // cache init - // endif - - - - // Run with 12mhz external crystal on XOSC0 - - // Automatic Loop Control - // 0 - disable - // 1 - enable - OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; - // Current Multiplier - // 6 - >24MHz to 48MHz - // 5 - >16MHz to 24MHz - // 4 - >8MHz to 16MHz - // 3 - 8MHz - OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; - // 3 - >24MHz to 48MHz - // 3 - >16MHz to 24MHz - // 3 - >8MHz to 16MHz - // 2 - 8MHz - OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; - OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; - OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; - OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; - - while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); - - OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; - OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; - OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; - // 0 - GCLK - // 1 - XOSC32 - // 2 - XOSC0 - // 3 - XOSC1 - OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; - OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; - OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; - - // wait for pll to be locked and ready - while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK - || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); - - - // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB - GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; - while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); - + /* // HRI_NVMCTRL_SET_CTRLA_RWS_bf */ + /* // osc32kctrl_init */ + /* // oscctrl_init */ + /* // mclk_init */ + /* // if GCLK_INIT_1ST */ + /* // gclk_init_generators_by_freq FIRST */ + /* // endif */ + /* // oscctrl_init_referenced_generators */ + /* // gclk_init_generators_by_fref LAST */ + /* // */ + /* // if dmac enable */ + /* // hri_mclk_set_AHBMASK_DMAC_bit */ + /* // dma init */ + /* // endif */ + + + /* // if CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | 2 | 3 */ + /* // port event init */ + /* // endif */ + + /* // if CONF_CMCC_ENABLE */ + /* // cache init */ + /* // endif */ + + + + /* // Run with 12mhz external crystal on XOSC0 */ + + /* // Automatic Loop Control */ + /* // 0 - disable */ + /* // 1 - enable */ + /* OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; */ + /* // Current Multiplier */ + /* // 6 - >24MHz to 48MHz */ + /* // 5 - >16MHz to 24MHz */ + /* // 4 - >8MHz to 16MHz */ + /* // 3 - 8MHz */ + /* OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; */ + /* // 3 - >24MHz to 48MHz */ + /* // 3 - >16MHz to 24MHz */ + /* // 3 - >8MHz to 16MHz */ + /* // 2 - 8MHz */ + /* OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; */ + /* OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; */ + /* OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; */ + /* OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; */ + + /* while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); */ + + /* OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; */ + /* OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; */ + /* OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; */ + /* // 0 - GCLK */ + /* // 1 - XOSC32 */ + /* // 2 - XOSC0 */ + /* // 3 - XOSC1 */ + /* OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; */ + /* OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; */ + /* OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; */ + + /* // wait for pll to be locked and ready */ + /* while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK */ + /* || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); */ + + + /* // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB */ + /* GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; */ + /* while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); */ + + mcu_init(); asm volatile("nop");