diff --git a/arch/arm/SAM_D2X/hal/inc/hal_gpio.hpp b/arch/arm/SAM_D2X/hal/inc/hal_gpio.hpp index a5f32aeb..076cd55e 100644 --- a/arch/arm/SAM_D2X/hal/inc/hal_gpio.hpp +++ b/arch/arm/SAM_D2X/hal/inc/hal_gpio.hpp @@ -1,14 +1,6 @@ #ifndef _HAL_GPIO_H_ #define _HAL_GPIO_H_ -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef __cplusplus -} -#endif #endif diff --git a/arch/arm/SAM_D2X/hal/inc/hal_init.hpp b/arch/arm/SAM_D2X/hal/inc/hal_init.hpp index 90b3717d..6b540d97 100644 --- a/arch/arm/SAM_D2X/hal/inc/hal_init.hpp +++ b/arch/arm/SAM_D2X/hal/inc/hal_init.hpp @@ -1,8 +1,6 @@ -#ifdef __cplusplus -extern "C" { -#endif +#ifndef _HAL_INIT_HPP_ +#define _HAL_INIT_HPP_ + -#ifdef __cplusplus -} #endif diff --git a/arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp b/arch/arm/SAM_D2X/hal/inc/hal_sam_d2x.hpp similarity index 52% rename from arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp rename to arch/arm/SAM_D2X/hal/inc/hal_sam_d2x.hpp index 9812fbe2..bb23b12f 100644 --- a/arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp +++ b/arch/arm/SAM_D2X/hal/inc/hal_sam_d2x.hpp @@ -2,23 +2,13 @@ #define _HAL_SAM_D2X_HPP_ #include "hal_arm.hpp" +#include namespace hal::arm::sam_d2x { - namespace core - { - - }; - - namespace usart - { - - }; - - namespace spi - { - - }; + void init(); + void clock_update(); }; - +#include "hdi_sam_d2x.h" +#include #endif diff --git a/arch/arm/SAM_D2X/hal/src/hal_sam_d2x.cpp b/arch/arm/SAM_D2X/hal/src/hal_sam_d2x.cpp new file mode 100644 index 00000000..5fc70b39 --- /dev/null +++ b/arch/arm/SAM_D2X/hal/src/hal_sam_d2x.cpp @@ -0,0 +1,17 @@ +#include "hal_sam_d2x.hpp" + +#define __SYSTEM_CLOCK (1000000) +uint32_t SystemCoreClock = __SYSTEM_CLOCK; + +void hal::arm::sam_d2x::init() +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +void hal::arm::sam_d2x::clock_update() +{ + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h b/arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h deleted file mode 100644 index f899fc28..00000000 --- a/arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _HDI_SAM_D2X_H_ -#define _HDI_SAM_D2X_H_ -#include "hal_arm.hpp" -#include -#ifdef __cplusplus -extern "C" { -#endif - -#if !(EP_MCU == __SAM_D2X__) - #error Shouldn't have gotten here -#endif -typedef enum IRQn -{ - // Cortex-M0+ Processor Exception Numbers - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - SVCall_IRQn = -5, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - // samd21j18a specific interrupt numbers - PM_IRQn = 0, - SYSCTRL_IRQn = 1, - WDT_IRQn = 2, - RTC_IRQn = 3, - EIC_IRQn = 4, - NVMCTRL_IRQn = 5, - DMAC_IRQn = 6, - USB_IRQn = 7, - EVSYS_IRQ = 8, - SERCOM0_IRQn = 9, - SERCOM1_IRQn = 10, - SERCOM2_IRQn = 11, - SERCOM3_IRQn = 12, - #if !() - SERCOM4_IRQn = 13, - SERCOM5_IRQn = 14, - -}IRQn_Type; -#ifdef __cplusplus -} -#endif -#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_ac.h b/arch/arm/SAM_D2X/hdi/inc/hdi_ac.h new file mode 100644 index 00000000..9fe36c52 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_ac.h @@ -0,0 +1,594 @@ +#ifndef _HDI_AC_H_ +#define _HDI_AC_H_ + +#define AC_U2205 +#define REV_AC 0x112 + +/* SAMD2X AC Component */ +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ +#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos) +#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) +#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ +#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos) +#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__)*/ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ +#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ +#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ +#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ +#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos) +#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ +#define AC_STATUSC_RESETVALUE 0x00ul /**< \brief (AC_STATUSC reset_value) Status C */ + +#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ +#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) +#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ +#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) +#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ +#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos) +#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) +#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ +#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) +#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */ +#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */ +#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */ +#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_MASK 0x33ul /**< \brief (AC_STATUSC) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ENABLE:1; /*!< bit: 0 Enable */ + uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ + uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 14 Reserved */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t OUT:2; /*!< bit: 16..17 Output */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_MASK 0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ + __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ + RoReg8 Reserved2[0x1]; + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ + RoReg8 Reserved3[0x3]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved4[0x8]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* SAMD2X AC Instance 0 */ + +/* ========== Register definition for AC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */ +#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */ +#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */ +#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */ +#else +#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */ +#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */ +#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */ +#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */ +#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */ +#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */ +#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */ +#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */ +#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */ +#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */ +#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */ +#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */ +#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */ +#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC peripheral ========== */ +#define AC_CMP_NUM 2 // Number of comparators +#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog +#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital +#define AC_NUM_CMP 2 +#define AC_PAIRS 1 // Number of pairs of comparators + +/* SAMD2X AC Instance 1 */ +/* ========== Register definition for AC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_AC1_CTRLA (0x42005400U) /**< \brief (AC1) Control A */ +#define REG_AC1_CTRLB (0x42005401U) /**< \brief (AC1) Control B */ +#define REG_AC1_EVCTRL (0x42005402U) /**< \brief (AC1) Event Control */ +#define REG_AC1_INTENCLR (0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */ +#define REG_AC1_INTENSET (0x42005405U) /**< \brief (AC1) Interrupt Enable Set */ +#define REG_AC1_INTFLAG (0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */ +#define REG_AC1_STATUSA (0x42005408U) /**< \brief (AC1) Status A */ +#define REG_AC1_STATUSB (0x42005409U) /**< \brief (AC1) Status B */ +#define REG_AC1_STATUSC (0x4200540AU) /**< \brief (AC1) Status C */ +#define REG_AC1_WINCTRL (0x4200540CU) /**< \brief (AC1) Window Control */ +#define REG_AC1_COMPCTRL0 (0x42005410U) /**< \brief (AC1) Comparator Control 0 */ +#define REG_AC1_COMPCTRL1 (0x42005414U) /**< \brief (AC1) Comparator Control 1 */ +#define REG_AC1_SCALER0 (0x42005420U) /**< \brief (AC1) Scaler 0 */ +#define REG_AC1_SCALER1 (0x42005421U) /**< \brief (AC1) Scaler 1 */ +#else +#define REG_AC1_CTRLA (*(RwReg8 *)0x42005400U) /**< \brief (AC1) Control A */ +#define REG_AC1_CTRLB (*(WoReg8 *)0x42005401U) /**< \brief (AC1) Control B */ +#define REG_AC1_EVCTRL (*(RwReg16*)0x42005402U) /**< \brief (AC1) Event Control */ +#define REG_AC1_INTENCLR (*(RwReg8 *)0x42005404U) /**< \brief (AC1) Interrupt Enable Clear */ +#define REG_AC1_INTENSET (*(RwReg8 *)0x42005405U) /**< \brief (AC1) Interrupt Enable Set */ +#define REG_AC1_INTFLAG (*(RwReg8 *)0x42005406U) /**< \brief (AC1) Interrupt Flag Status and Clear */ +#define REG_AC1_STATUSA (*(RoReg8 *)0x42005408U) /**< \brief (AC1) Status A */ +#define REG_AC1_STATUSB (*(RoReg8 *)0x42005409U) /**< \brief (AC1) Status B */ +#define REG_AC1_STATUSC (*(RoReg8 *)0x4200540AU) /**< \brief (AC1) Status C */ +#define REG_AC1_WINCTRL (*(RwReg8 *)0x4200540CU) /**< \brief (AC1) Window Control */ +#define REG_AC1_COMPCTRL0 (*(RwReg *)0x42005410U) /**< \brief (AC1) Comparator Control 0 */ +#define REG_AC1_COMPCTRL1 (*(RwReg *)0x42005414U) /**< \brief (AC1) Comparator Control 1 */ +#define REG_AC1_SCALER0 (*(RwReg8 *)0x42005420U) /**< \brief (AC1) Scaler 0 */ +#define REG_AC1_SCALER1 (*(RwReg8 *)0x42005421U) /**< \brief (AC1) Scaler 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for AC1 peripheral ========== */ +#define AC1_CMP_NUM 2 // Number of comparators +#define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog +#define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital +#define AC1_NUM_CMP 2 +#define AC1_PAIRS 1 // Number of pairs of comparators + + + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_adc.h b/arch/arm/SAM_D2X/hdi/inc/hdi_adc.h new file mode 100644 index 00000000..7974f059 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_adc.h @@ -0,0 +1,701 @@ +#ifndef _HDI_ADC_H_ +#define _HDI_ADC_H_ + +#define ADC_U2204 +#define REV_ADC 0x120 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ +#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ +#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ +#define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos) +#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ +#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ +#define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ + +#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ +#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) +#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */ +#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ +#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ +#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ +#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ + uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ + uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */ +#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ +#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos) +#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) +#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ +#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos) +#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) +#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ +#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) +#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */ +#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */ +#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */ +#define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */ +#define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */ +#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */ +#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ + uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ +#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ +#define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ +#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ +#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ +#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos) +#define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ +#define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos) +#define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ + __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ +#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ +#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ +#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ +#define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos) +#define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ +#define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos) +#define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ + uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ +#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos) +#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) +#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ +#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos) +#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) +#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ + RoReg8 Reserved1[0x2]; + __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ + RoReg8 Reserved2[0x3]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ + RoReg8 Reserved3[0x3]; + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ + RoReg8 Reserved4[0x1]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ + RoReg8 Reserved5[0x2]; + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ + RoReg8 Reserved6[0x2]; + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */ +#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */ +#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */ +#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */ +#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */ +#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */ +#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */ +#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */ +#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */ +#else +#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */ +#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */ +#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */ +#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */ +#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */ +#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */ +#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */ +#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */ +#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */ +#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */ +#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */ +#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */ +#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */ +#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */ +#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */ +#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */ +#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */ +#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */ +#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */ +#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for ADC peripheral ========== */ +#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger +#define ADC_EXTCHANNEL_MSB 19 // Number of external channels +#define ADC_GCLK_ID 30 // Index of Generic Clock +#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield +#define ADC_RESULT_MSB 15 // Size of Result + + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_dac.h b/arch/arm/SAM_D2X/hdi/inc/hdi_dac.h new file mode 100644 index 00000000..0fe8942a --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_dac.h @@ -0,0 +1,264 @@ +#ifndef _HDI_DAC_H_ +#define _HDI_DAC_H_ + +#define DAC_U2214 +#define REV_DAC 0x110 + +/* DAC Component */ +/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ +#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ +#define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos) +#define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ + uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ + uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ + uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ + uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ +#define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos) +#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ +#define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos) +#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ +#define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos) +#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ +#define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos) +#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ +#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos) +#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ +#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ + uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ +#define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ +#define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos) +#define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ +#define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos) +#define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ + __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ + __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ +#define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ +#define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ +#define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos) +#define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ +#define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos) +#define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ +#define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ +#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ +#define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ + RoReg8 Reserved2[0x2]; + __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* DAC Instance */ +/* ========== Register definition for DAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status */ +#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data */ +#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer */ +#else +#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */ +#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */ +#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */ +#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */ +#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */ +#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */ +#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */ +#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */ +#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for DAC peripheral ========== */ +#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger +#define DAC_GCLK_ID 33 // Index of Generic Clock + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_dmac.h b/arch/arm/SAM_D2X/hdi/inc/hdi_dmac.h new file mode 100644 index 00000000..ab54694a --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_dmac.h @@ -0,0 +1,1097 @@ +#ifndef _HDI_DMAC_H_ +#define _HDI_DMAC_H_ +#define DMAC_U2223 +#define REV_DMAC 0x110 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ +#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) Byte bus access */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) Half-word bus access */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) Word bus access */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_QOSCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ +#define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ + +#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ +#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) +#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ +#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) +#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ +#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) +#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ +#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ + +#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ +#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) +#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) +#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ +#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ +#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ + +#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ +#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) +#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ +#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ +#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ +#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) +#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ +#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) +#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ +#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) +#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ +#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ +#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ +#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ +#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */ +#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ +#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ +#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) +#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ +#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ +#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Transfer Error */ +#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ +#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Fetch Error */ +#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) No action */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit access */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit access */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit access */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1< +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#define CAST(type, value) ((type *)(value)) +#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ +#else +#define CAST(type, value) (value) +#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ +#include +#if !defined(DONT_USE_CMSIS_INIT) +void SystemInit(void); +void SystemCoreClockUpdate(void); +#endif + +// Hardware definitions for internal peripherals +#include "hdi_ac.h" +#include "hdi_adc.h" +#include "hdi_dmac.h" +#include "hdi_dsu.h" +#include "hdi_eic.h" +#include "hdi_evsys.h" +#include "hdi_gclk.h" +#include "hdi_hmatrixb.h" +#include "hdi_i2s.h" +#include "hdi_mtb.h" +#include "hdi_nvmctrl.h" +#include "hdi_pac.h" +#include "hdi_pm.h" +#include "hdi_port.h" +#include "hdi_rtc.h" +#include "hdi_sercom.h" +#include "hdi_sysctrl.h" +#include "hdi_tc.h" +#include "hdi_tcc.h" +#include "hdi_usb.h" +#include "hdi_wdt.h" + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) *\/ */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ +#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ +#define MUX_PB14H_GCLK_IO0 7L +#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) +#define PORT_PB14H_GCLK_IO0 (1ul << 14) +#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ +#define MUX_PB22H_GCLK_IO0 7L +#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) +#define PORT_PB22H_GCLK_IO0 (1ul << 22) +#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ +#define MUX_PA14H_GCLK_IO0 7L +#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) +#define PORT_PA14H_GCLK_IO0 (1ul << 14) +#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ +#define MUX_PA27H_GCLK_IO0 7L +#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) +#define PORT_PA27H_GCLK_IO0 (1ul << 27) +#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ +#define MUX_PA28H_GCLK_IO0 7L +#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) +#define PORT_PA28H_GCLK_IO0 (1ul << 28) +#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ +#define MUX_PA30H_GCLK_IO0 7L +#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) +#define PORT_PA30H_GCLK_IO0 (1ul << 30) +#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ +#define MUX_PB15H_GCLK_IO1 7L +#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) +#define PORT_PB15H_GCLK_IO1 (1ul << 15) +#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ +#define MUX_PB23H_GCLK_IO1 7L +#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) +#define PORT_PB23H_GCLK_IO1 (1ul << 23) +#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ +#define MUX_PA15H_GCLK_IO1 7L +#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) +#define PORT_PA15H_GCLK_IO1 (1ul << 15) +#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ +#define MUX_PB16H_GCLK_IO2 7L +#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) +#define PORT_PB16H_GCLK_IO2 (1ul << 16) +#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ +#define MUX_PA16H_GCLK_IO2 7L +#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) +#define PORT_PA16H_GCLK_IO2 (1ul << 16) +#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ +#define MUX_PA17H_GCLK_IO3 7L +#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) +#define PORT_PA17H_GCLK_IO3 (1ul << 17) +#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ +#define MUX_PB17H_GCLK_IO3 7L +#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) +#define PORT_PB17H_GCLK_IO3 (1ul << 17) +#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ +#define MUX_PA10H_GCLK_IO4 7L +#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) +#define PORT_PA10H_GCLK_IO4 (1ul << 10) +#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ +#define MUX_PA20H_GCLK_IO4 7L +#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) +#define PORT_PA20H_GCLK_IO4 (1ul << 20) +#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ +#define MUX_PB10H_GCLK_IO4 7L +#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) +#define PORT_PB10H_GCLK_IO4 (1ul << 10) +#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ +#define MUX_PA11H_GCLK_IO5 7L +#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) +#define PORT_PA11H_GCLK_IO5 (1ul << 11) +#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ +#define MUX_PA21H_GCLK_IO5 7L +#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) +#define PORT_PA21H_GCLK_IO5 (1ul << 21) +#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ +#define MUX_PB11H_GCLK_IO5 7L +#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) +#define PORT_PB11H_GCLK_IO5 (1ul << 11) +#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ +#define MUX_PA22H_GCLK_IO6 7L +#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) +#define PORT_PA22H_GCLK_IO6 (1ul << 22) +#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ +#define MUX_PB12H_GCLK_IO6 7L +#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) +#define PORT_PB12H_GCLK_IO6 (1ul << 12) +#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ +#define MUX_PA23H_GCLK_IO7 7L +#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) +#define PORT_PA23H_GCLK_IO7 (1ul << 23) +#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ +#define MUX_PB13H_GCLK_IO7 7L +#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) +#define PORT_PB13H_GCLK_IO7 (1ul << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 0L +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 0L +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 0L +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) +#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 0L +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) +#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 0L +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 0L +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 0L +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) +#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 0L +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) +#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 0L +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) +#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 0L +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 0L +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) +#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 0L +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 0L +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) +#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 0L +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) +#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 0L +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 0L +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) +#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 0L +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) +#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 0L +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 0L +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) +#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 0L +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) +#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 0L +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 0L +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 0L +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) +#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 0L +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) +#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 0L +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 0L +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 0L +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) +#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 0L +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) +#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ +#define MUX_PA28A_EIC_EXTINT8 0L +#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) +#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) +#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 0L +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) +#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 0L +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 0L +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) +#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 0L +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT10 0L +#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) +#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) +#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 0L +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) +#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 0L +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT11 0L +#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) +#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) +#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 0L +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) +#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 0L +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT12 0L +#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) +#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) +#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 0L +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) +#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 0L +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT13 0L +#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) +#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) +#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 0L +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) +#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 0L +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 0L +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) +#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 0L +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) +#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 0L +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT15 0L +#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) +#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) +#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 0L +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) +#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 0L +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) +#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI 0L +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (1ul << 8) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ +#define MUX_PA24G_USB_DM 6L +#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) +#define PORT_PA24G_USB_DM (1ul << 24) +#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ +#define MUX_PA25G_USB_DP 6L +#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) +#define PORT_PA25G_USB_DP (1ul << 25) +#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ +#define MUX_PA23G_USB_SOF_1KHZ 6L +#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) +#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 3L +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) +#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 2L +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) +#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 3L +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) +#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 2L +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) +#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 3L +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) +#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 2L +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) +#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 3L +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) +#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 2L +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 2L +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) +#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 3L +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) +#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 2L +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) +#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 3L +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) +#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 3L +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) +#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 2L +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) +#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 3L +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) +#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 2L +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD0 3L +#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) +#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) +#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 2L +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) +#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD1 3L +#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) +#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) +#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 2L +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) +#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 3L +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) +#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 2L +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) +#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 3L +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) +#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 2L +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD0 3L +#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) +#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) +#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 2L +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) +#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD1 3L +#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) +#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) +#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 2L +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) +#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 3L +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) +#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 3L +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) +#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 2L +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) +#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 3L +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) +#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 3L +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) +#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 2L +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD0 3L +#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) +#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) +#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 3L +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) +#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 2L +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) +#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD1 3L +#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) +#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) +#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 3L +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) +#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 2L +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) +#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 3L +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) +#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 3L +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) +#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 2L +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) +#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 3L +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) +#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 3L +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) +#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 2L +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 2L +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) +#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD0 3L +#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) +#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) +#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 3L +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) +#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD0 3L +#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) +#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) +#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 2L +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) +#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD1 3L +#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) +#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) +#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 3L +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) +#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD1 3L +#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) +#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) +#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 3L +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) +#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 3L +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) +#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 3L +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) +#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 2L +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) +#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 3L +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) +#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 3L +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) +#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 3L +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) +#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 2L +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TCC0_WO0 4L +#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) +#define PORT_PA04E_TCC0_WO0 (1ul << 4) +#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TCC0_WO0 4L +#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) +#define PORT_PA08E_TCC0_WO0 (1ul << 8) +#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TCC0_WO0 4L +#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) +#define PORT_PB30E_TCC0_WO0 (1ul << 30) +#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TCC0_WO1 4L +#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) +#define PORT_PA05E_TCC0_WO1 (1ul << 5) +#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TCC0_WO1 4L +#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) +#define PORT_PA09E_TCC0_WO1 (1ul << 9) +#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TCC0_WO1 4L +#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) +#define PORT_PB31E_TCC0_WO1 (1ul << 31) +#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 5L +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (1ul << 10) +#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC0_WO2 5L +#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) +#define PORT_PA18F_TCC0_WO2 (1ul << 18) +#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 5L +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (1ul << 11) +#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC0_WO3 5L +#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) +#define PORT_PA19F_TCC0_WO3 (1ul << 19) +#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ +#define MUX_PA14F_TCC0_WO4 5L +#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) +#define PORT_PA14F_TCC0_WO4 (1ul << 14) +#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ +#define MUX_PA22F_TCC0_WO4 5L +#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) +#define PORT_PA22F_TCC0_WO4 (1ul << 22) +#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 5L +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (1ul << 10) +#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ +#define MUX_PB16F_TCC0_WO4 5L +#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) +#define PORT_PB16F_TCC0_WO4 (1ul << 16) +#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ +#define MUX_PA15F_TCC0_WO5 5L +#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) +#define PORT_PA15F_TCC0_WO5 (1ul << 15) +#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ +#define MUX_PA23F_TCC0_WO5 5L +#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) +#define PORT_PA23F_TCC0_WO5 (1ul << 23) +#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 5L +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (1ul << 11) +#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ +#define MUX_PB17F_TCC0_WO5 5L +#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) +#define PORT_PB17F_TCC0_WO5 (1ul << 17) +#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 5L +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (1ul << 12) +#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ +#define MUX_PA20F_TCC0_WO6 5L +#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) +#define PORT_PA20F_TCC0_WO6 (1ul << 20) +#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ +#define MUX_PB12F_TCC0_WO6 5L +#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) +#define PORT_PB12F_TCC0_WO6 (1ul << 12) +#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ +#define MUX_PA16F_TCC0_WO6 5L +#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) +#define PORT_PA16F_TCC0_WO6 (1ul << 16) +#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 5L +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (1ul << 13) +#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ +#define MUX_PA21F_TCC0_WO7 5L +#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) +#define PORT_PA21F_TCC0_WO7 (1ul << 21) +#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ +#define MUX_PB13F_TCC0_WO7 5L +#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) +#define PORT_PB13F_TCC0_WO7 (1ul << 13) +#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ +#define MUX_PA17F_TCC0_WO7 5L +#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) +#define PORT_PA17F_TCC0_WO7 (1ul << 17) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TCC1_WO0 4L +#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) +#define PORT_PA06E_TCC1_WO0 (1ul << 6) +#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TCC1_WO0 4L +#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) +#define PORT_PA10E_TCC1_WO0 (1ul << 10) +#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TCC1_WO0 4L +#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) +#define PORT_PA30E_TCC1_WO0 (1ul << 30) +#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TCC1_WO1 4L +#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) +#define PORT_PA07E_TCC1_WO1 (1ul << 7) +#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TCC1_WO1 4L +#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) +#define PORT_PA11E_TCC1_WO1 (1ul << 11) +#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TCC1_WO1 4L +#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) +#define PORT_PA31E_TCC1_WO1 (1ul << 31) +#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ +#define MUX_PA08F_TCC1_WO2 5L +#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) +#define PORT_PA08F_TCC1_WO2 (1ul << 8) +#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC1_WO2 5L +#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) +#define PORT_PA24F_TCC1_WO2 (1ul << 24) +#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ +#define MUX_PB30F_TCC1_WO2 5L +#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) +#define PORT_PB30F_TCC1_WO2 (1ul << 30) +#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ +#define MUX_PA09F_TCC1_WO3 5L +#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) +#define PORT_PA09F_TCC1_WO3 (1ul << 9) +#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ +#define MUX_PA25F_TCC1_WO3 5L +#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) +#define PORT_PA25F_TCC1_WO3 (1ul << 25) +#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ +#define MUX_PB31F_TCC1_WO3 5L +#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) +#define PORT_PB31F_TCC1_WO3 (1ul << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TCC2_WO0 4L +#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) +#define PORT_PA12E_TCC2_WO0 (1ul << 12) +#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TCC2_WO0 4L +#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) +#define PORT_PA16E_TCC2_WO0 (1ul << 16) +#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TCC2_WO0 4L +#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) +#define PORT_PA00E_TCC2_WO0 (1ul << 0) +#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TCC2_WO1 4L +#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) +#define PORT_PA13E_TCC2_WO1 (1ul << 13) +#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TCC2_WO1 4L +#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) +#define PORT_PA17E_TCC2_WO1 (1ul << 17) +#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TCC2_WO1 4L +#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) +#define PORT_PA01E_TCC2_WO1 (1ul << 1) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 4L +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (1ul << 18) +#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 4L +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (1ul << 14) +#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 4L +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (1ul << 19) +#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 4L +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (1ul << 15) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 4L +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (1ul << 22) +#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 4L +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (1ul << 8) +#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 4L +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (1ul << 12) +#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 4L +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (1ul << 23) +#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 4L +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (1ul << 9) +#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 4L +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (1ul << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 4L +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (1ul << 24) +#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 4L +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (1ul << 10) +#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 4L +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (1ul << 14) +#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 4L +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (1ul << 25) +#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 4L +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (1ul << 11) +#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 4L +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (1ul << 15) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 4L +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (1ul << 2) +#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 4L +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (1ul << 16) +#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 4L +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (1ul << 3) +#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 4L +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (1ul << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 4L +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (1ul << 20) +#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 4L +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (1ul << 0) +#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 4L +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (1ul << 22) +#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 4L +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (1ul << 21) +#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 4L +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (1ul << 1) +#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 4L +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (1ul << 23) +/* ========== PORT definition for ADC peripheral ========== */ +#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC_AIN0 1L +#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) +#define PORT_PA02B_ADC_AIN0 (1ul << 2) +#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC_AIN1 1L +#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) +#define PORT_PA03B_ADC_AIN1 (1ul << 3) +#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC_AIN2 1L +#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) +#define PORT_PB08B_ADC_AIN2 (1ul << 8) +#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC_AIN3 1L +#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) +#define PORT_PB09B_ADC_AIN3 (1ul << 9) +#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC_AIN4 1L +#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) +#define PORT_PA04B_ADC_AIN4 (1ul << 4) +#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC_AIN5 1L +#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) +#define PORT_PA05B_ADC_AIN5 (1ul << 5) +#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC_AIN6 1L +#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) +#define PORT_PA06B_ADC_AIN6 (1ul << 6) +#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC_AIN7 1L +#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) +#define PORT_PA07B_ADC_AIN7 (1ul << 7) +#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ +#define MUX_PB00B_ADC_AIN8 1L +#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) +#define PORT_PB00B_ADC_AIN8 (1ul << 0) +#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ +#define MUX_PB01B_ADC_AIN9 1L +#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) +#define PORT_PB01B_ADC_AIN9 (1ul << 1) +#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ +#define MUX_PB02B_ADC_AIN10 1L +#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) +#define PORT_PB02B_ADC_AIN10 (1ul << 2) +#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ +#define MUX_PB03B_ADC_AIN11 1L +#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) +#define PORT_PB03B_ADC_AIN11 (1ul << 3) +#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ +#define MUX_PB04B_ADC_AIN12 1L +#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) +#define PORT_PB04B_ADC_AIN12 (1ul << 4) +#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ +#define MUX_PB05B_ADC_AIN13 1L +#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) +#define PORT_PB05B_ADC_AIN13 (1ul << 5) +#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ +#define MUX_PB06B_ADC_AIN14 1L +#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) +#define PORT_PB06B_ADC_AIN14 (1ul << 6) +#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ +#define MUX_PB07B_ADC_AIN15 1L +#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) +#define PORT_PB07B_ADC_AIN15 (1ul << 7) +#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ +#define MUX_PA08B_ADC_AIN16 1L +#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) +#define PORT_PA08B_ADC_AIN16 (1ul << 8) +#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ +#define MUX_PA09B_ADC_AIN17 1L +#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) +#define PORT_PA09B_ADC_AIN17 (1ul << 9) +#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ +#define MUX_PA10B_ADC_AIN18 1L +#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) +#define PORT_PA10B_ADC_AIN18 (1ul << 10) +#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ +#define MUX_PA11B_ADC_AIN19 1L +#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) +#define PORT_PA11B_ADC_AIN19 (1ul << 11) +#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ +#define MUX_PA04B_ADC_VREFP 1L +#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) +#define PORT_PA04B_ADC_VREFP (1ul << 4) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 1L +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (1ul << 4) +#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 1L +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (1ul << 5) +#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 1L +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (1ul << 6) +#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 1L +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (1ul << 7) +#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ +#define MUX_PA12H_AC_CMP0 7L +#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) +#define PORT_PA12H_AC_CMP0 (1ul << 12) +#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ +#define MUX_PA18H_AC_CMP0 7L +#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) +#define PORT_PA18H_AC_CMP0 (1ul << 18) +#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ +#define MUX_PA13H_AC_CMP1 7L +#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) +#define PORT_PA13H_AC_CMP1 (1ul << 13) +#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ +#define MUX_PA19H_AC_CMP1 7L +#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) +#define PORT_PA19H_AC_CMP1 (1ul << 19) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT 1L +#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) +#define PORT_PA02B_DAC_VOUT (1ul << 2) +#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ +#define MUX_PA03B_DAC_VREFP 1L +#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) +#define PORT_PA03B_DAC_VREFP (1ul << 3) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ +#define MUX_PA11G_I2S_FS0 6L +#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) +#define PORT_PA11G_I2S_FS0 (1ul << 11) +#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ +#define MUX_PA21G_I2S_FS0 6L +#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) +#define PORT_PA21G_I2S_FS0 (1ul << 21) +#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ +#define MUX_PB12G_I2S_FS1 6L +#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) +#define PORT_PB12G_I2S_FS1 (1ul << 12) +#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ +#define MUX_PA09G_I2S_MCK0 6L +#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) +#define PORT_PA09G_I2S_MCK0 (1ul << 9) +#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ +#define MUX_PB17G_I2S_MCK0 6L +#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) +#define PORT_PB17G_I2S_MCK0 (1ul << 17) +#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ +#define MUX_PB10G_I2S_MCK1 6L +#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) +#define PORT_PB10G_I2S_MCK1 (1ul << 10) +#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ +#define MUX_PA10G_I2S_SCK0 6L +#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) +#define PORT_PA10G_I2S_SCK0 (1ul << 10) +#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ +#define MUX_PA20G_I2S_SCK0 6L +#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) +#define PORT_PA20G_I2S_SCK0 (1ul << 20) +#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ +#define MUX_PB11G_I2S_SCK1 6L +#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) +#define PORT_PB11G_I2S_SCK1 (1ul << 11) +#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ +#define MUX_PA07G_I2S_SD0 6L +#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) +#define PORT_PA07G_I2S_SD0 (1ul << 7) +#define PIN_PA19G_I2S_SD0 19L /**< \brief I3S signal: SD0 on PA19 mux G */ +#define MUX_PA19G_I2S_SD0 6L +#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) +#define PORT_PA19G_I2S_SD0 (1ul << 19) +#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ +#define MUX_PA08G_I2S_SD1 6L +#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) +#define PORT_PA08G_I2S_SD1 (1ul << 8) +#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ +#define MUX_PB16G_I2S_SD1 6L +#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) +#define PORT_PB16G_I2S_SD1 (1ul << 16) + +#define FLASH_SIZE 0x40000UL /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ + +#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ +#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ +#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ +#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ +#define PPB_ADDR (0xE0000000u) /**< PPB base address */ + +#define DSU_DID_RESETVALUE 0x10010000UL +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_sercom.h b/arch/arm/SAM_D2X/hdi/inc/hdi_sercom.h new file mode 100644 index 00000000..988174e8 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_sercom.h @@ -0,0 +1,2034 @@ +#ifndef _HDI_SERCOM_H_ +#define _HDI_SERCOM_H_ + +#define SERCOM_U2201 +#define REV_SERCOM 0x220 + +/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ +#define SERCOM_I2CM_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ + +#define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ +#define SERCOM_I2CM_CTRLA_SWRST (0x1ul << SERCOM_I2CM_CTRLA_SWRST_Pos) +#define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ +#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos) +#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ +#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)) +#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */ +#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */ +#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */ +#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */ +#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */ +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */ +#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) +#define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ +#define SERCOM_I2CM_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) +#define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ +#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos) +#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ +#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) +#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) +#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ +#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) +#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) +#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ +#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos) +#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)) +#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ +#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos) +#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ +#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos) +#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) +#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ +#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) +#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ + +/* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ + uint32_t :3; /*!< bit: 17..19 Reserved */ + uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ + uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ + uint32_t :1; /*!< bit: 26 Reserved */ + uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ +#define SERCOM_I2CS_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ + +#define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ +#define SERCOM_I2CS_CTRLA_SWRST (0x1ul << SERCOM_I2CS_CTRLA_SWRST_Pos) +#define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ +#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos) +#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ +#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)) +#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */ +#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */ +#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */ +#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */ +#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */ +#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */ +#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) +#define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ +#define SERCOM_I2CS_CTRLA_RUNSTDBY (0x1ul << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) +#define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ +#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos) +#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ +#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) +#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) +#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) +#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ +#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos) +#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)) +#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ +#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos) +#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ +#define SERCOM_I2CS_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) +#define SERCOM_I2CS_CTRLA_MASK 0x4BB1009Ful /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ + +/* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :7; /*!< bit: 9..15 Reserved */ + uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ +#define SERCOM_SPI_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ + +#define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ +#define SERCOM_SPI_CTRLA_SWRST (0x1ul << SERCOM_SPI_CTRLA_SWRST_Pos) +#define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ +#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos) +#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ +#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)) +#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */ +#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */ +#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */ +#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */ +#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */ +#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */ +#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) +#define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ +#define SERCOM_SPI_CTRLA_RUNSTDBY (0x1ul << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) +#define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ +#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos) +#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ +#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos) +#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)) +#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ +#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos) +#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)) +#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ +#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos) +#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)) +#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ +#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos) +#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ +#define SERCOM_SPI_CTRLA_CPOL (0x1ul << SERCOM_SPI_CTRLA_CPOL_Pos) +#define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ +#define SERCOM_SPI_CTRLA_DORD (0x1ul << SERCOM_SPI_CTRLA_DORD_Pos) +#define SERCOM_SPI_CTRLA_MASK 0x7F33019Ful /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ + +/* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ + uint32_t :2; /*!< bit: 5.. 6 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ + uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ + uint32_t :4; /*!< bit: 9..12 Reserved */ + uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ + uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ + uint32_t :2; /*!< bit: 18..19 Reserved */ + uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ + uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ + uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ + uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ + uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ + uint32_t DORD:1; /*!< bit: 30 Data Order */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_USART_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ +#define SERCOM_USART_CTRLA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ + +#define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ +#define SERCOM_USART_CTRLA_SWRST (0x1ul << SERCOM_USART_CTRLA_SWRST_Pos) +#define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ +#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos) +#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ +#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)) +#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */ +#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */ +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */ +#define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val 0x3ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */ +#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val 0x4ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */ +#define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val 0x5ul /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */ +#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) +#define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ +#define SERCOM_USART_CTRLA_RUNSTDBY (0x1ul << SERCOM_USART_CTRLA_RUNSTDBY_Pos) +#define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ +#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos) +#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ +#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos) +#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)) +#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ +#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos) +#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)) +#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ +#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos) +#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)) +#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ +#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos) +#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)) +#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ +#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos) +#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)) +#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ +#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos) +#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ +#define SERCOM_USART_CTRLA_CPOL (0x1ul << SERCOM_USART_CTRLA_CPOL_Pos) +#define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ +#define SERCOM_USART_CTRLA_DORD (0x1ul << SERCOM_USART_CTRLA_DORD_Pos) +#define SERCOM_USART_CTRLA_MASK 0x7FF3E19Ful /**< \brief (SERCOM_USART_CTRLA) MASK Register */ + +/* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ +#define SERCOM_I2CM_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ + +#define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ +#define SERCOM_I2CM_CTRLB_SMEN (0x1ul << SERCOM_I2CM_CTRLB_SMEN_Pos) +#define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ +#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos) +#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ +#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos) +#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)) +#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ +#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos) +#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ + +/* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ + uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ + uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ + uint32_t :3; /*!< bit: 11..13 Reserved */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t CMD:2; /*!< bit: 16..17 Command */ + uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ + uint32_t :13; /*!< bit: 19..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ +#define SERCOM_I2CS_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ + +#define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ +#define SERCOM_I2CS_CTRLB_SMEN (0x1ul << SERCOM_I2CS_CTRLB_SMEN_Pos) +#define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ +#define SERCOM_I2CS_CTRLB_GCMD (0x1ul << SERCOM_I2CS_CTRLB_GCMD_Pos) +#define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ +#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos) +#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ +#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos) +#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) +#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ +#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos) +#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)) +#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ +#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos) +#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ + +/* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ + uint32_t :2; /*!< bit: 7.. 8 Reserved */ + uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ + uint32_t :3; /*!< bit: 10..12 Reserved */ + uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ + uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ +#define SERCOM_SPI_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ + +#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ +#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos) +#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)) +#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ +#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos) +#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ +#define SERCOM_SPI_CTRLB_SSDE (0x1ul << SERCOM_SPI_CTRLB_SSDE_Pos) +#define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ +#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos) +#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ +#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos) +#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)) +#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ +#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos) +#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ + +/* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ + uint32_t :3; /*!< bit: 3.. 5 Reserved */ + uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ + uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ + uint32_t ENC:1; /*!< bit: 10 Encoding Format */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ + uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_USART_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ +#define SERCOM_USART_CTRLB_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ + +#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ +#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos) +#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)) +#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ +#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos) +#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ +#define SERCOM_USART_CTRLB_COLDEN (0x1ul << SERCOM_USART_CTRLB_COLDEN_Pos) +#define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ +#define SERCOM_USART_CTRLB_SFDE (0x1ul << SERCOM_USART_CTRLB_SFDE_Pos) +#define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ +#define SERCOM_USART_CTRLB_ENC (0x1ul << SERCOM_USART_CTRLB_ENC_Pos) +#define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ +#define SERCOM_USART_CTRLB_PMODE (0x1ul << SERCOM_USART_CTRLB_PMODE_Pos) +#define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ +#define SERCOM_USART_CTRLB_TXEN (0x1ul << SERCOM_USART_CTRLB_TXEN_Pos) +#define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ +#define SERCOM_USART_CTRLB_RXEN (0x1ul << SERCOM_USART_CTRLB_RXEN_Pos) +#define SERCOM_USART_CTRLB_MASK 0x00032747ul /**< \brief (SERCOM_USART_CTRLB) MASK Register */ + +/* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ + uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ + uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_BAUD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ +#define SERCOM_I2CM_BAUD_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ + +#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ +#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos) +#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)) +#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ +#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos) +#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) +#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ +#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos) +#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)) +#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ +#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) +#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)) +#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ + +/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_BAUD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ +#define SERCOM_SPI_BAUD_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ + +#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ +#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos) +#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)) +#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */ + +/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } bit; /*!< Structure used for bit access */ + struct { // FRAC mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRAC; /*!< Structure used for FRAC */ + struct { // FRACFP mode + uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ + uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ + } FRACFP; /*!< Structure used for FRACFP */ + struct { // USARTFP mode + uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ + } USARTFP; /*!< Structure used for USARTFP */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_USART_BAUD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ +#define SERCOM_USART_BAUD_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ + +#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ +#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos) +#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)) +#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */ + +// FRAC mode +#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ +#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos) +#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)) +#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ +#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos) +#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)) +#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ + +// FRACFP mode +#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ +#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) +#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)) +#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ +#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos) +#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)) +#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ + +// USARTFP mode +#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ +#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) +#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)) +#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ + +/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_RXPL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ +#define SERCOM_USART_RXPL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ + +#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ +#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos) +#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)) +#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */ + +/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ +#define SERCOM_I2CM_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ + +#define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ +#define SERCOM_I2CM_INTENCLR_MB (0x1ul << SERCOM_I2CM_INTENCLR_MB_Pos) +#define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ +#define SERCOM_I2CM_INTENCLR_SB (0x1ul << SERCOM_I2CM_INTENCLR_SB_Pos) +#define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_I2CM_INTENCLR_ERROR (0x1ul << SERCOM_I2CM_INTENCLR_ERROR_Pos) +#define SERCOM_I2CM_INTENCLR_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ + +/* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ +#define SERCOM_I2CS_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ + +#define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_PREC (0x1ul << SERCOM_I2CS_INTENCLR_PREC_Pos) +#define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_AMATCH (0x1ul << SERCOM_I2CS_INTENCLR_AMATCH_Pos) +#define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_DRDY (0x1ul << SERCOM_I2CS_INTENCLR_DRDY_Pos) +#define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_I2CS_INTENCLR_ERROR (0x1ul << SERCOM_I2CS_INTENCLR_ERROR_Pos) +#define SERCOM_I2CS_INTENCLR_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ + +/* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ +#define SERCOM_SPI_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ + +#define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_DRE (0x1ul << SERCOM_SPI_INTENCLR_DRE_Pos) +#define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_TXC (0x1ul << SERCOM_SPI_INTENCLR_TXC_Pos) +#define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_RXC (0x1ul << SERCOM_SPI_INTENCLR_RXC_Pos) +#define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_SSL (0x1ul << SERCOM_SPI_INTENCLR_SSL_Pos) +#define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_SPI_INTENCLR_ERROR (0x1ul << SERCOM_SPI_INTENCLR_ERROR_Pos) +#define SERCOM_SPI_INTENCLR_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ + +/* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ +#define SERCOM_USART_INTENCLR_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ + +#define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ +#define SERCOM_USART_INTENCLR_DRE (0x1ul << SERCOM_USART_INTENCLR_DRE_Pos) +#define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ +#define SERCOM_USART_INTENCLR_TXC (0x1ul << SERCOM_USART_INTENCLR_TXC_Pos) +#define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ +#define SERCOM_USART_INTENCLR_RXC (0x1ul << SERCOM_USART_INTENCLR_RXC_Pos) +#define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ +#define SERCOM_USART_INTENCLR_RXS (0x1ul << SERCOM_USART_INTENCLR_RXS_Pos) +#define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ +#define SERCOM_USART_INTENCLR_CTSIC (0x1ul << SERCOM_USART_INTENCLR_CTSIC_Pos) +#define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ +#define SERCOM_USART_INTENCLR_RXBRK (0x1ul << SERCOM_USART_INTENCLR_RXBRK_Pos) +#define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ +#define SERCOM_USART_INTENCLR_ERROR (0x1ul << SERCOM_USART_INTENCLR_ERROR_Pos) +#define SERCOM_USART_INTENCLR_MASK 0xBFul /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ + +/* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ + uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ +#define SERCOM_I2CM_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ + +#define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ +#define SERCOM_I2CM_INTENSET_MB (0x1ul << SERCOM_I2CM_INTENSET_MB_Pos) +#define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ +#define SERCOM_I2CM_INTENSET_SB (0x1ul << SERCOM_I2CM_INTENSET_SB_Pos) +#define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_I2CM_INTENSET_ERROR (0x1ul << SERCOM_I2CM_INTENSET_ERROR_Pos) +#define SERCOM_I2CM_INTENSET_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ + +/* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ + uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ + uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ +#define SERCOM_I2CS_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ + +#define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_PREC (0x1ul << SERCOM_I2CS_INTENSET_PREC_Pos) +#define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_AMATCH (0x1ul << SERCOM_I2CS_INTENSET_AMATCH_Pos) +#define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_DRDY (0x1ul << SERCOM_I2CS_INTENSET_DRDY_Pos) +#define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_I2CS_INTENSET_ERROR (0x1ul << SERCOM_I2CS_INTENSET_ERROR_Pos) +#define SERCOM_I2CS_INTENSET_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ + +/* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ +#define SERCOM_SPI_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ + +#define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ +#define SERCOM_SPI_INTENSET_DRE (0x1ul << SERCOM_SPI_INTENSET_DRE_Pos) +#define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ +#define SERCOM_SPI_INTENSET_TXC (0x1ul << SERCOM_SPI_INTENSET_TXC_Pos) +#define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ +#define SERCOM_SPI_INTENSET_RXC (0x1ul << SERCOM_SPI_INTENSET_RXC_Pos) +#define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ +#define SERCOM_SPI_INTENSET_SSL (0x1ul << SERCOM_SPI_INTENSET_SSL_Pos) +#define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_SPI_INTENSET_ERROR (0x1ul << SERCOM_SPI_INTENSET_ERROR_Pos) +#define SERCOM_SPI_INTENSET_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ + +/* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ + uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ + uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ + uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ + uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ + uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ +#define SERCOM_USART_INTENSET_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ + +#define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ +#define SERCOM_USART_INTENSET_DRE (0x1ul << SERCOM_USART_INTENSET_DRE_Pos) +#define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ +#define SERCOM_USART_INTENSET_TXC (0x1ul << SERCOM_USART_INTENSET_TXC_Pos) +#define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ +#define SERCOM_USART_INTENSET_RXC (0x1ul << SERCOM_USART_INTENSET_RXC_Pos) +#define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ +#define SERCOM_USART_INTENSET_RXS (0x1ul << SERCOM_USART_INTENSET_RXS_Pos) +#define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ +#define SERCOM_USART_INTENSET_CTSIC (0x1ul << SERCOM_USART_INTENSET_CTSIC_Pos) +#define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ +#define SERCOM_USART_INTENSET_RXBRK (0x1ul << SERCOM_USART_INTENSET_RXBRK_Pos) +#define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ +#define SERCOM_USART_INTENSET_ERROR (0x1ul << SERCOM_USART_INTENSET_ERROR_Pos) +#define SERCOM_USART_INTENSET_MASK 0xBFul /**< \brief (SERCOM_USART_INTENSET) MASK Register */ + +/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ + __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ + __I uint8_t :5; /*!< bit: 2.. 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ +#define SERCOM_I2CM_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ + +#define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ +#define SERCOM_I2CM_INTFLAG_MB (0x1ul << SERCOM_I2CM_INTFLAG_MB_Pos) +#define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ +#define SERCOM_I2CM_INTFLAG_SB (0x1ul << SERCOM_I2CM_INTFLAG_SB_Pos) +#define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ +#define SERCOM_I2CM_INTFLAG_ERROR (0x1ul << SERCOM_I2CM_INTFLAG_ERROR_Pos) +#define SERCOM_I2CM_INTFLAG_MASK 0x83ul /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ + +/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ + __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ + __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ + __I uint8_t :4; /*!< bit: 3.. 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ +#define SERCOM_I2CS_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ + +#define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ +#define SERCOM_I2CS_INTFLAG_PREC (0x1ul << SERCOM_I2CS_INTFLAG_PREC_Pos) +#define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ +#define SERCOM_I2CS_INTFLAG_AMATCH (0x1ul << SERCOM_I2CS_INTFLAG_AMATCH_Pos) +#define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ +#define SERCOM_I2CS_INTFLAG_DRDY (0x1ul << SERCOM_I2CS_INTFLAG_DRDY_Pos) +#define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ +#define SERCOM_I2CS_INTFLAG_ERROR (0x1ul << SERCOM_I2CS_INTFLAG_ERROR_Pos) +#define SERCOM_I2CS_INTFLAG_MASK 0x87ul /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ + +/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ + __I uint8_t :3; /*!< bit: 4.. 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ +#define SERCOM_SPI_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ + +#define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ +#define SERCOM_SPI_INTFLAG_DRE (0x1ul << SERCOM_SPI_INTFLAG_DRE_Pos) +#define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ +#define SERCOM_SPI_INTFLAG_TXC (0x1ul << SERCOM_SPI_INTFLAG_TXC_Pos) +#define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ +#define SERCOM_SPI_INTFLAG_RXC (0x1ul << SERCOM_SPI_INTFLAG_RXC_Pos) +#define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ +#define SERCOM_SPI_INTFLAG_SSL (0x1ul << SERCOM_SPI_INTFLAG_SSL_Pos) +#define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ +#define SERCOM_SPI_INTFLAG_ERROR (0x1ul << SERCOM_SPI_INTFLAG_ERROR_Pos) +#define SERCOM_SPI_INTFLAG_MASK 0x8Ful /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ + +/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ + __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ + __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ + __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ + __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ + __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ + __I uint8_t :1; /*!< bit: 6 Reserved */ + __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ +#define SERCOM_USART_INTFLAG_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ + +#define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ +#define SERCOM_USART_INTFLAG_DRE (0x1ul << SERCOM_USART_INTFLAG_DRE_Pos) +#define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ +#define SERCOM_USART_INTFLAG_TXC (0x1ul << SERCOM_USART_INTFLAG_TXC_Pos) +#define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ +#define SERCOM_USART_INTFLAG_RXC (0x1ul << SERCOM_USART_INTFLAG_RXC_Pos) +#define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ +#define SERCOM_USART_INTFLAG_RXS (0x1ul << SERCOM_USART_INTFLAG_RXS_Pos) +#define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ +#define SERCOM_USART_INTFLAG_CTSIC (0x1ul << SERCOM_USART_INTFLAG_CTSIC_Pos) +#define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ +#define SERCOM_USART_INTFLAG_RXBRK (0x1ul << SERCOM_USART_INTFLAG_RXBRK_Pos) +#define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ +#define SERCOM_USART_INTFLAG_ERROR (0x1ul << SERCOM_USART_INTFLAG_ERROR_Pos) +#define SERCOM_USART_INTFLAG_MASK 0xBFul /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ + +/* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t LENERR:1; /*!< bit: 10 Length Error */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ +#define SERCOM_I2CM_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ + +#define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ +#define SERCOM_I2CM_STATUS_BUSERR (0x1ul << SERCOM_I2CM_STATUS_BUSERR_Pos) +#define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ +#define SERCOM_I2CM_STATUS_ARBLOST (0x1ul << SERCOM_I2CM_STATUS_ARBLOST_Pos) +#define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ +#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos) +#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ +#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos) +#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) +#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ +#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos) +#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ +#define SERCOM_I2CM_STATUS_CLKHOLD (0x1ul << SERCOM_I2CM_STATUS_CLKHOLD_Pos) +#define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ +#define SERCOM_I2CM_STATUS_MEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) +#define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CM_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) +#define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ +#define SERCOM_I2CM_STATUS_LENERR (0x1ul << SERCOM_I2CM_STATUS_LENERR_Pos) +#define SERCOM_I2CM_STATUS_MASK 0x07F7ul /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ + +/* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ + uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ + uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ + uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ + uint16_t SR:1; /*!< bit: 4 Repeated Start */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ + uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ + uint16_t :1; /*!< bit: 8 Reserved */ + uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ + uint16_t HS:1; /*!< bit: 10 High Speed */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ +#define SERCOM_I2CS_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ + +#define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ +#define SERCOM_I2CS_STATUS_BUSERR (0x1ul << SERCOM_I2CS_STATUS_BUSERR_Pos) +#define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ +#define SERCOM_I2CS_STATUS_COLL (0x1ul << SERCOM_I2CS_STATUS_COLL_Pos) +#define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ +#define SERCOM_I2CS_STATUS_RXNACK (0x1ul << SERCOM_I2CS_STATUS_RXNACK_Pos) +#define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ +#define SERCOM_I2CS_STATUS_DIR (0x1ul << SERCOM_I2CS_STATUS_DIR_Pos) +#define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ +#define SERCOM_I2CS_STATUS_SR (0x1ul << SERCOM_I2CS_STATUS_SR_Pos) +#define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ +#define SERCOM_I2CS_STATUS_LOWTOUT (0x1ul << SERCOM_I2CS_STATUS_LOWTOUT_Pos) +#define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ +#define SERCOM_I2CS_STATUS_CLKHOLD (0x1ul << SERCOM_I2CS_STATUS_CLKHOLD_Pos) +#define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ +#define SERCOM_I2CS_STATUS_SEXTTOUT (0x1ul << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) +#define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ +#define SERCOM_I2CS_STATUS_HS (0x1ul << SERCOM_I2CS_STATUS_HS_Pos) +#define SERCOM_I2CS_STATUS_MASK 0x06DFul /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ + +/* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t :13; /*!< bit: 3..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_SPI_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ +#define SERCOM_SPI_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ + +#define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ +#define SERCOM_SPI_STATUS_BUFOVF (0x1ul << SERCOM_SPI_STATUS_BUFOVF_Pos) +#define SERCOM_SPI_STATUS_MASK 0x0004ul /**< \brief (SERCOM_SPI_STATUS) MASK Register */ + +/* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PERR:1; /*!< bit: 0 Parity Error */ + uint16_t FERR:1; /*!< bit: 1 Frame Error */ + uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ + uint16_t CTS:1; /*!< bit: 3 Clear To Send */ + uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ + uint16_t COLL:1; /*!< bit: 5 Collision Detected */ + uint16_t :10; /*!< bit: 6..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_USART_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ +#define SERCOM_USART_STATUS_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ + +#define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ +#define SERCOM_USART_STATUS_PERR (0x1ul << SERCOM_USART_STATUS_PERR_Pos) +#define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ +#define SERCOM_USART_STATUS_FERR (0x1ul << SERCOM_USART_STATUS_FERR_Pos) +#define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ +#define SERCOM_USART_STATUS_BUFOVF (0x1ul << SERCOM_USART_STATUS_BUFOVF_Pos) +#define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ +#define SERCOM_USART_STATUS_CTS (0x1ul << SERCOM_USART_STATUS_CTS_Pos) +#define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ +#define SERCOM_USART_STATUS_ISF (0x1ul << SERCOM_USART_STATUS_ISF_Pos) +#define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ +#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos) +#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */ + +/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */ + +#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) +#define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) +#define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ +#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) +#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */ +#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */ + +#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) +#define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) +#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */ + +#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos) +#define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_ENABLE (0x1ul << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) +#define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ +#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) +#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_USART_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */ + +#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos) +#define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_ENABLE (0x1ul << SERCOM_USART_SYNCBUSY_ENABLE_Pos) +#define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ +#define SERCOM_USART_SYNCBUSY_CTRLB (0x1ul << SERCOM_USART_SYNCBUSY_CTRLB_Pos) +#define SERCOM_USART_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ + +/* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ + uint32_t :2; /*!< bit: 11..12 Reserved */ + uint32_t LENEN:1; /*!< bit: 13 Length Enable */ + uint32_t HS:1; /*!< bit: 14 High Speed Mode */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t LEN:8; /*!< bit: 16..23 Length */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ +#define SERCOM_I2CM_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ + +#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ +#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos) +#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)) +#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ +#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos) +#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ +#define SERCOM_I2CM_ADDR_HS (0x1ul << SERCOM_I2CM_ADDR_HS_Pos) +#define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ +#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos) +#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ +#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos) +#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)) +#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ + +/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ + uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ + uint32_t :4; /*!< bit: 11..14 Reserved */ + uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ + uint32_t :1; /*!< bit: 16 Reserved */ + uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ +#define SERCOM_I2CS_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ + +#define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ +#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos) +#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ +#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos) +#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)) +#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ +#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos) +#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ +#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos) +#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) +#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ + +/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ + uint32_t :8; /*!< bit: 8..15 Reserved */ + uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ +#define SERCOM_SPI_ADDR_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ + +#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ +#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos) +#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)) +#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ +#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos) +#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)) +#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */ + +/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ +#define SERCOM_I2CM_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ + +#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ +#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos) +#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)) +#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */ + +/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CS_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ +#define SERCOM_I2CS_DATA_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ + +#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ +#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos) +#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)) +#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */ + +/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint32_t :23; /*!< bit: 9..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SERCOM_SPI_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ +#define SERCOM_SPI_DATA_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ + +#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ +#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos) +#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)) +#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */ + +/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ + uint16_t :7; /*!< bit: 9..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SERCOM_USART_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ +#define SERCOM_USART_DATA_RESETVALUE 0x0000ul /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ + +#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ +#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos) +#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)) +#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */ + +/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_I2CM_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ +#define SERCOM_I2CM_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ + +#define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ +#define SERCOM_I2CM_DBGCTRL_DBGSTOP (0x1ul << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) +#define SERCOM_I2CM_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ + +/* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_SPI_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ +#define SERCOM_SPI_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ + +#define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ +#define SERCOM_SPI_DBGCTRL_DBGSTOP (0x1ul << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) +#define SERCOM_SPI_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ + +/* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SERCOM_USART_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ +#define SERCOM_USART_DBGCTRL_RESETVALUE 0x00ul /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ + +#define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ +#define SERCOM_USART_DBGCTRL_DBGSTOP (0x1ul << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) +#define SERCOM_USART_DBGCTRL_MASK 0x01ul /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ + +/** \brief SERCOM_I2CM hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* I2C Master Mode */ + __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ + __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ + RoReg8 Reserved2[0x4]; + __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ + __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ + __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ + RoReg8 Reserved7[0x7]; + __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ +} SercomI2cm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief SERCOM_I2CS hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* I2C Slave Mode */ + __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ + __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ + RoReg8 Reserved1[0xC]; + __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ + RoReg8 Reserved2[0x1]; + __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ + __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */ + RoReg8 Reserved5[0x4]; + __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ + __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ +} SercomI2cs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief SERCOM_SPI hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* SPI Mode */ + __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ + __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ + RoReg8 Reserved2[0x7]; + __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ + __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */ + RoReg8 Reserved6[0x4]; + __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ + __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ + RoReg8 Reserved7[0x4]; + __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ +} SercomSpi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief SERCOM_USART hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USART Mode */ + __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ + __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ + RoReg8 Reserved1[0x4]; + __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ + __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ + RoReg8 Reserved2[0x5]; + __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ + RoReg8 Reserved3[0x1]; + __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ + RoReg8 Reserved4[0x1]; + __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ + RoReg8 Reserved5[0x1]; + __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ + __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */ + RoReg8 Reserved6[0x8]; + __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ + RoReg8 Reserved7[0x6]; + __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ +} SercomUsart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ + SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ + SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ + SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ +} Sercom; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* SERCOM 0 Inst */ +/* ========== Register definition for SERCOM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ +#else +#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */ +#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */ +#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */ +#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */ +#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */ +#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */ +#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */ +#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */ +#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */ +#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */ +#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */ +#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */ +#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */ +#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */ +#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */ +#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */ +#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */ +#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */ +#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */ +#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */ +#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */ +#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */ +#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */ +#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */ +#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */ +#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */ +#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */ +#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */ +#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */ +#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */ +#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */ +#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */ +#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */ +#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */ +#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */ +#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */ +#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */ +#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM0 peripheral ========== */ +#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger +#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger +#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core +#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM0_INT_MSB 6 +/* SERCOM 1 Inst */ +/* ========== Register definition for SERCOM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ +#else +#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */ +#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */ +#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */ +#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */ +#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */ +#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */ +#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */ +#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */ +#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */ +#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */ +#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */ +#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */ +#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */ +#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */ +#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */ +#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */ +#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */ +#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */ +#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */ +#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */ +#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */ +#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */ +#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */ +#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */ +#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */ +#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */ +#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */ +#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */ +#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */ +#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */ +#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */ +#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */ +#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */ +#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */ +#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */ +#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */ +#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */ +#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM1 peripheral ========== */ +#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger +#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger +#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core +#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM1_INT_MSB 6 +/* SERCOM 2 Inst */ +/* ========== Register definition for SERCOM2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ +#else +#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */ +#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */ +#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */ +#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */ +#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */ +#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */ +#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */ +#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */ +#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */ +#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */ +#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */ +#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */ +#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */ +#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */ +#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */ +#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */ +#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */ +#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */ +#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */ +#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */ +#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */ +#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */ +#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */ +#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */ +#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */ +#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */ +#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */ +#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */ +#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */ +#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */ +#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */ +#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */ +#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */ +#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */ +#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */ +#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */ +#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */ +#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM2 peripheral ========== */ +#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger +#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger +#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core +#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM2_INT_MSB 6 +/* SERCOM 3 Inst */ +/* ========== Register definition for SERCOM3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ +#else +#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */ +#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */ +#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */ +#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */ +#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */ +#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */ +#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */ +#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */ +#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */ +#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */ +#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */ +#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */ +#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */ +#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */ +#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */ +#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */ +#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */ +#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */ +#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */ +#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */ +#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */ +#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */ +#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */ +#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */ +#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */ +#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */ +#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */ +#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */ +#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */ +#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */ +#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */ +#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */ +#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */ +#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */ +#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */ +#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */ +#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */ +#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM3 peripheral ========== */ +#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger +#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger +#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core +#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM3_INT_MSB 6 +/* SERCOM 4 Inst */ +/* ========== Register definition for SERCOM4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ +#else +#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */ +#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */ +#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */ +#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */ +#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */ +#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */ +#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */ +#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */ +#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */ +#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */ +#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */ +#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */ +#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */ +#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */ +#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */ +#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */ +#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */ +#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */ +#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */ +#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */ +#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */ +#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */ +#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */ +#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */ +#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */ +#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */ +#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */ +#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */ +#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */ +#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */ +#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */ +#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */ +#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */ +#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */ +#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */ +#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */ +#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */ +#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM4 peripheral ========== */ +#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger +#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger +#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core +#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM4_INT_MSB 6 +/* SERCOM 5 Inst */ +/* ========== Register definition for SERCOM5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SERCOM5_I2CM_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (0x42001C00U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (0x42001C04U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ +#else +#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CM Control A */ +#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CM Control B */ +#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CU) /**< \brief (SERCOM5) I2CM Baud Rate */ +#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */ +#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */ +#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */ +#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */ +#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */ +#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */ +#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */ +#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) I2CS Control A */ +#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) I2CS Control B */ +#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */ +#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */ +#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */ +#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */ +#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */ +#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */ +#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */ +#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */ +#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) SPI Control B */ +#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CU) /**< \brief (SERCOM5) SPI Baud Rate */ +#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */ +#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */ +#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */ +#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */ +#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */ +#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */ +#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */ +#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */ +#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) USART Control A */ +#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04U) /**< \brief (SERCOM5) USART Control B */ +#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CU) /**< \brief (SERCOM5) USART Baud Rate */ +#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EU) /**< \brief (SERCOM5) USART Receive Pulse Length */ +#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14U) /**< \brief (SERCOM5) USART Interrupt Enable Clear */ +#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */ +#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */ +#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */ +#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */ +#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */ +#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SERCOM5 peripheral ========== */ +#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger +#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger +#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core +#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout +#define SERCOM5_INT_MSB 6 + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_sysctrl.h b/arch/arm/SAM_D2X/hdi/inc/hdi_sysctrl.h new file mode 100644 index 00000000..e7eaa828 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_sysctrl.h @@ -0,0 +1,972 @@ +#ifndef _HDI_SYSCTRL_H_ +#define _HDI_SYSCTRL_H_ + +#define SYSCTRL_U2100 +#define REV_SYSCTRL 0x201 + +/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */ +#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */ + +#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */ +#define SYSCTRL_INTENCLR_XOSCRDY (0x1ul << SYSCTRL_INTENCLR_XOSCRDY_Pos) +#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ +#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1ul << SYSCTRL_INTENCLR_XOSC32KRDY_Pos) +#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ +#define SYSCTRL_INTENCLR_OSC32KRDY (0x1ul << SYSCTRL_INTENCLR_OSC32KRDY_Pos) +#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */ +#define SYSCTRL_INTENCLR_OSC8MRDY (0x1ul << SYSCTRL_INTENCLR_OSC8MRDY_Pos) +#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */ +#define SYSCTRL_INTENCLR_DFLLRDY (0x1ul << SYSCTRL_INTENCLR_DFLLRDY_Pos) +#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ +#define SYSCTRL_INTENCLR_DFLLOOB (0x1ul << SYSCTRL_INTENCLR_DFLLOOB_Pos) +#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ +#define SYSCTRL_INTENCLR_DFLLLCKF (0x1ul << SYSCTRL_INTENCLR_DFLLLCKF_Pos) +#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ +#define SYSCTRL_INTENCLR_DFLLLCKC (0x1ul << SYSCTRL_INTENCLR_DFLLLCKC_Pos) +#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ +#define SYSCTRL_INTENCLR_DFLLRCS (0x1ul << SYSCTRL_INTENCLR_DFLLRCS_Pos) +#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */ +#define SYSCTRL_INTENCLR_BOD33RDY (0x1ul << SYSCTRL_INTENCLR_BOD33RDY_Pos) +#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */ +#define SYSCTRL_INTENCLR_BOD33DET (0x1ul << SYSCTRL_INTENCLR_BOD33DET_Pos) +#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */ +#define SYSCTRL_INTENCLR_B33SRDY (0x1ul << SYSCTRL_INTENCLR_B33SRDY_Pos) +#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ +#define SYSCTRL_INTENCLR_DPLLLCKR (0x1ul << SYSCTRL_INTENCLR_DPLLLCKR_Pos) +#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ +#define SYSCTRL_INTENCLR_DPLLLCKF (0x1ul << SYSCTRL_INTENCLR_DPLLLCKF_Pos) +#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */ +#define SYSCTRL_INTENCLR_DPLLLTO (0x1ul << SYSCTRL_INTENCLR_DPLLLTO_Pos) +#define SYSCTRL_INTENCLR_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENCLR) MASK Register */ + +/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */ +#define SYSCTRL_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */ + +#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */ +#define SYSCTRL_INTENSET_XOSCRDY (0x1ul << SYSCTRL_INTENSET_XOSCRDY_Pos) +#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ +#define SYSCTRL_INTENSET_XOSC32KRDY (0x1ul << SYSCTRL_INTENSET_XOSC32KRDY_Pos) +#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */ +#define SYSCTRL_INTENSET_OSC32KRDY (0x1ul << SYSCTRL_INTENSET_OSC32KRDY_Pos) +#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */ +#define SYSCTRL_INTENSET_OSC8MRDY (0x1ul << SYSCTRL_INTENSET_OSC8MRDY_Pos) +#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */ +#define SYSCTRL_INTENSET_DFLLRDY (0x1ul << SYSCTRL_INTENSET_DFLLRDY_Pos) +#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ +#define SYSCTRL_INTENSET_DFLLOOB (0x1ul << SYSCTRL_INTENSET_DFLLOOB_Pos) +#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ +#define SYSCTRL_INTENSET_DFLLLCKF (0x1ul << SYSCTRL_INTENSET_DFLLLCKF_Pos) +#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ +#define SYSCTRL_INTENSET_DFLLLCKC (0x1ul << SYSCTRL_INTENSET_DFLLLCKC_Pos) +#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ +#define SYSCTRL_INTENSET_DFLLRCS (0x1ul << SYSCTRL_INTENSET_DFLLRCS_Pos) +#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */ +#define SYSCTRL_INTENSET_BOD33RDY (0x1ul << SYSCTRL_INTENSET_BOD33RDY_Pos) +#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */ +#define SYSCTRL_INTENSET_BOD33DET (0x1ul << SYSCTRL_INTENSET_BOD33DET_Pos) +#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */ +#define SYSCTRL_INTENSET_B33SRDY (0x1ul << SYSCTRL_INTENSET_B33SRDY_Pos) +#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ +#define SYSCTRL_INTENSET_DPLLLCKR (0x1ul << SYSCTRL_INTENSET_DPLLLCKR_Pos) +#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ +#define SYSCTRL_INTENSET_DPLLLCKF (0x1ul << SYSCTRL_INTENSET_DPLLLCKF_Pos) +#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */ +#define SYSCTRL_INTENSET_DPLLLTO (0x1ul << SYSCTRL_INTENSET_DPLLLTO_Pos) +#define SYSCTRL_INTENSET_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTENSET) MASK Register */ + +/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + __I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + __I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + __I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + __I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + __I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + __I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + __I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + __I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + __I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + __I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + __I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + __I uint32_t :3; /*!< bit: 12..14 Reserved */ + __I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + __I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + __I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + __I uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ +#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */ +#define SYSCTRL_INTFLAG_XOSCRDY (0x1ul << SYSCTRL_INTFLAG_XOSCRDY_Pos) +#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */ +#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1ul << SYSCTRL_INTFLAG_XOSC32KRDY_Pos) +#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */ +#define SYSCTRL_INTFLAG_OSC32KRDY (0x1ul << SYSCTRL_INTFLAG_OSC32KRDY_Pos) +#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */ +#define SYSCTRL_INTFLAG_OSC8MRDY (0x1ul << SYSCTRL_INTFLAG_OSC8MRDY_Pos) +#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */ +#define SYSCTRL_INTFLAG_DFLLRDY (0x1ul << SYSCTRL_INTFLAG_DFLLRDY_Pos) +#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */ +#define SYSCTRL_INTFLAG_DFLLOOB (0x1ul << SYSCTRL_INTFLAG_DFLLOOB_Pos) +#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */ +#define SYSCTRL_INTFLAG_DFLLLCKF (0x1ul << SYSCTRL_INTFLAG_DFLLLCKF_Pos) +#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */ +#define SYSCTRL_INTFLAG_DFLLLCKC (0x1ul << SYSCTRL_INTFLAG_DFLLLCKC_Pos) +#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */ +#define SYSCTRL_INTFLAG_DFLLRCS (0x1ul << SYSCTRL_INTFLAG_DFLLRCS_Pos) +#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */ +#define SYSCTRL_INTFLAG_BOD33RDY (0x1ul << SYSCTRL_INTFLAG_BOD33RDY_Pos) +#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */ +#define SYSCTRL_INTFLAG_BOD33DET (0x1ul << SYSCTRL_INTFLAG_BOD33DET_Pos) +#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */ +#define SYSCTRL_INTFLAG_B33SRDY (0x1ul << SYSCTRL_INTFLAG_B33SRDY_Pos) +#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */ +#define SYSCTRL_INTFLAG_DPLLLCKR (0x1ul << SYSCTRL_INTFLAG_DPLLLCKR_Pos) +#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */ +#define SYSCTRL_INTFLAG_DPLLLCKF (0x1ul << SYSCTRL_INTFLAG_DPLLLCKF_Pos) +#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */ +#define SYSCTRL_INTFLAG_DPLLLTO (0x1ul << SYSCTRL_INTFLAG_DPLLLTO_Pos) +#define SYSCTRL_INTFLAG_MASK 0x00038FFFul /**< \brief (SYSCTRL_INTFLAG) MASK Register */ + +/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ + uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */ + uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */ + uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */ + uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */ + uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */ + uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */ + uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */ + uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */ + uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */ + uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */ + uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */ + uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */ + uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */ + uint32_t :14; /*!< bit: 18..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_PCLKSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */ +#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */ + +#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */ +#define SYSCTRL_PCLKSR_XOSCRDY (0x1ul << SYSCTRL_PCLKSR_XOSCRDY_Pos) +#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */ +#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1ul << SYSCTRL_PCLKSR_XOSC32KRDY_Pos) +#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */ +#define SYSCTRL_PCLKSR_OSC32KRDY (0x1ul << SYSCTRL_PCLKSR_OSC32KRDY_Pos) +#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */ +#define SYSCTRL_PCLKSR_OSC8MRDY (0x1ul << SYSCTRL_PCLKSR_OSC8MRDY_Pos) +#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */ +#define SYSCTRL_PCLKSR_DFLLRDY (0x1ul << SYSCTRL_PCLKSR_DFLLRDY_Pos) +#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */ +#define SYSCTRL_PCLKSR_DFLLOOB (0x1ul << SYSCTRL_PCLKSR_DFLLOOB_Pos) +#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */ +#define SYSCTRL_PCLKSR_DFLLLCKF (0x1ul << SYSCTRL_PCLKSR_DFLLLCKF_Pos) +#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */ +#define SYSCTRL_PCLKSR_DFLLLCKC (0x1ul << SYSCTRL_PCLKSR_DFLLLCKC_Pos) +#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */ +#define SYSCTRL_PCLKSR_DFLLRCS (0x1ul << SYSCTRL_PCLKSR_DFLLRCS_Pos) +#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */ +#define SYSCTRL_PCLKSR_BOD33RDY (0x1ul << SYSCTRL_PCLKSR_BOD33RDY_Pos) +#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */ +#define SYSCTRL_PCLKSR_BOD33DET (0x1ul << SYSCTRL_PCLKSR_BOD33DET_Pos) +#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */ +#define SYSCTRL_PCLKSR_B33SRDY (0x1ul << SYSCTRL_PCLKSR_B33SRDY_Pos) +#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */ +#define SYSCTRL_PCLKSR_DPLLLCKR (0x1ul << SYSCTRL_PCLKSR_DPLLLCKR_Pos) +#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */ +#define SYSCTRL_PCLKSR_DPLLLCKF (0x1ul << SYSCTRL_PCLKSR_DPLLLCKF_Pos) +#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */ +#define SYSCTRL_PCLKSR_DPLLLTO (0x1ul << SYSCTRL_PCLKSR_DPLLLTO_Pos) +#define SYSCTRL_PCLKSR_MASK 0x00038FFFul /**< \brief (SYSCTRL_PCLKSR) MASK Register */ + +/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t :3; /*!< bit: 3.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ + uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ + uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SYSCTRL_XOSC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define SYSCTRL_XOSC_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ + +#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */ +#define SYSCTRL_XOSC_ENABLE (0x1ul << SYSCTRL_XOSC_ENABLE_Pos) +#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */ +#define SYSCTRL_XOSC_XTALEN (0x1ul << SYSCTRL_XOSC_XTALEN_Pos) +#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */ +#define SYSCTRL_XOSC_RUNSTDBY (0x1ul << SYSCTRL_XOSC_RUNSTDBY_Pos) +#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */ +#define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos) +#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */ +#define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos) +#define SYSCTRL_XOSC_GAIN(value) (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)) +#define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */ +#define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */ +#define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */ +#define SYSCTRL_XOSC_GAIN_3_Val 0x3ul /**< \brief (SYSCTRL_XOSC) 16MHz */ +#define SYSCTRL_XOSC_GAIN_4_Val 0x4ul /**< \brief (SYSCTRL_XOSC) 30MHz */ +#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos) +#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos) +#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos) +#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos) +#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos) +#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */ +#define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos) +#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */ +#define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos) +#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)) +#define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */ + +/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ + uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ + uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ + uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SYSCTRL_XOSC32K_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define SYSCTRL_XOSC32K_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ + +#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */ +#define SYSCTRL_XOSC32K_ENABLE (0x1ul << SYSCTRL_XOSC32K_ENABLE_Pos) +#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */ +#define SYSCTRL_XOSC32K_XTALEN (0x1ul << SYSCTRL_XOSC32K_XTALEN_Pos) +#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */ +#define SYSCTRL_XOSC32K_EN32K (0x1ul << SYSCTRL_XOSC32K_EN32K_Pos) +#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */ +#define SYSCTRL_XOSC32K_EN1K (0x1ul << SYSCTRL_XOSC32K_EN1K_Pos) +#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */ +#define SYSCTRL_XOSC32K_AAMPEN (0x1ul << SYSCTRL_XOSC32K_AAMPEN_Pos) +#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */ +#define SYSCTRL_XOSC32K_RUNSTDBY (0x1ul << SYSCTRL_XOSC32K_RUNSTDBY_Pos) +#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */ +#define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos) +#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */ +#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos) +#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)) +#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */ +#define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos) +#define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */ + +/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ + uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ + uint32_t :2; /*!< bit: 4.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_OSC32K_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ +#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080ul /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ + +#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */ +#define SYSCTRL_OSC32K_ENABLE (0x1ul << SYSCTRL_OSC32K_ENABLE_Pos) +#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */ +#define SYSCTRL_OSC32K_EN32K (0x1ul << SYSCTRL_OSC32K_EN32K_Pos) +#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */ +#define SYSCTRL_OSC32K_EN1K (0x1ul << SYSCTRL_OSC32K_EN1K_Pos) +#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */ +#define SYSCTRL_OSC32K_RUNSTDBY (0x1ul << SYSCTRL_OSC32K_RUNSTDBY_Pos) +#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */ +#define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos) +#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */ +#define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos) +#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)) +#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */ +#define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos) +#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */ +#define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos) +#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)) +#define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */ + +/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SYSCTRL_OSCULP32K_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#define SYSCTRL_OSCULP32K_RESETVALUE 0x1Ful /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ + +#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */ +#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos) +#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)) +#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */ +#define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos) +#define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */ + +/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ + uint32_t :4; /*!< bit: 2.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */ + uint32_t :6; /*!< bit: 10..15 Reserved */ + uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */ + uint32_t :2; /*!< bit: 28..29 Reserved */ + uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_OSC8M_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */ +#define SYSCTRL_OSC8M_RESETVALUE 0x87070382ul /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */ + +#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */ +#define SYSCTRL_OSC8M_ENABLE (0x1ul << SYSCTRL_OSC8M_ENABLE_Pos) +#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */ +#define SYSCTRL_OSC8M_RUNSTDBY (0x1ul << SYSCTRL_OSC8M_RUNSTDBY_Pos) +#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */ +#define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos) +#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */ +#define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos) +#define SYSCTRL_OSC8M_PRESC(value) (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)) +#define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */ +#define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */ +#define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */ +#define SYSCTRL_OSC8M_PRESC_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 8 */ +#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos) +#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos) +#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos) +#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos) +#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */ +#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos) +#define SYSCTRL_OSC8M_CALIB(value) (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)) +#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */ +#define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos) +#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)) +#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */ +#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */ +#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */ +#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3ul /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */ +#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos) +#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos) +#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos) +#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos) +#define SYSCTRL_OSC8M_MASK 0xCFFF03C2ul /**< \brief (SYSCTRL_OSC8M) MASK Register */ + +/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ + uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ + uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ + uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ + uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ + uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ + uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ + uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SYSCTRL_DFLLCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */ +#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080ul /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */ + +#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */ +#define SYSCTRL_DFLLCTRL_ENABLE (0x1ul << SYSCTRL_DFLLCTRL_ENABLE_Pos) +#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */ +#define SYSCTRL_DFLLCTRL_MODE (0x1ul << SYSCTRL_DFLLCTRL_MODE_Pos) +#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */ +#define SYSCTRL_DFLLCTRL_STABLE (0x1ul << SYSCTRL_DFLLCTRL_STABLE_Pos) +#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */ +#define SYSCTRL_DFLLCTRL_LLAW (0x1ul << SYSCTRL_DFLLCTRL_LLAW_Pos) +#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */ +#define SYSCTRL_DFLLCTRL_USBCRM (0x1ul << SYSCTRL_DFLLCTRL_USBCRM_Pos) +#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */ +#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1ul << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos) +#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */ +#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1ul << SYSCTRL_DFLLCTRL_ONDEMAND_Pos) +#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */ +#define SYSCTRL_DFLLCTRL_CCDIS (0x1ul << SYSCTRL_DFLLCTRL_CCDIS_Pos) +#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */ +#define SYSCTRL_DFLLCTRL_QLDIS (0x1ul << SYSCTRL_DFLLCTRL_QLDIS_Pos) +#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */ +#define SYSCTRL_DFLLCTRL_BPLCKC (0x1ul << SYSCTRL_DFLLCTRL_BPLCKC_Pos) +#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */ +#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1ul << SYSCTRL_DFLLCTRL_WAITLOCK_Pos) +#define SYSCTRL_DFLLCTRL_MASK 0x0FFEul /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */ + +/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ + uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ + uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_DFLLVAL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */ +#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */ + +#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */ +#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos) +#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)) +#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */ +#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos) +#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)) +#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */ +#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos) +#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)) +#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */ + +/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ + uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ + uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_DFLLMUL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */ +#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ + +#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */ +#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos) +#define SYSCTRL_DFLLMUL_MUL(value) (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)) +#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */ +#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos) +#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)) +#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */ +#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos) +#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)) +#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */ + +/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t READREQ:1; /*!< bit: 7 Read Request */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SYSCTRL_DFLLSYNC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */ +#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ + +#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */ +#define SYSCTRL_DFLLSYNC_READREQ (0x1ul << SYSCTRL_DFLLSYNC_READREQ_Pos) +#define SYSCTRL_DFLLSYNC_MASK 0x80ul /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */ + +/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t HYST:1; /*!< bit: 2 Hysteresis */ + uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MODE:1; /*!< bit: 8 Operation Mode */ + uint32_t CEN:1; /*!< bit: 9 Clock Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ + uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_BOD33_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */ +#define SYSCTRL_BOD33_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */ + +#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */ +#define SYSCTRL_BOD33_ENABLE (0x1ul << SYSCTRL_BOD33_ENABLE_Pos) +#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */ +#define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos) +#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */ +#define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos) +#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)) +#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */ +#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */ +#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */ +#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos) +#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos) +#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos) +#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */ +#define SYSCTRL_BOD33_RUNSTDBY (0x1ul << SYSCTRL_BOD33_RUNSTDBY_Pos) +#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */ +#define SYSCTRL_BOD33_MODE (0x1ul << SYSCTRL_BOD33_MODE_Pos) +#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */ +#define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos) +#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */ +#define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL(value) (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)) +#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */ +#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */ +#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */ +#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */ +#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */ +#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */ +#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */ +#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */ +#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */ +#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9ul /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */ +#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAul /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */ +#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBul /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */ +#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCul /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */ +#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDul /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */ +#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEul /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */ +#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFul /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */ +#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos) +#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */ +#define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos) +#define SYSCTRL_BOD33_LEVEL(value) (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)) +#define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */ + +/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :6; /*!< bit: 0.. 5 Reserved */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t :6; /*!< bit: 7..12 Reserved */ + uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} SYSCTRL_VREG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */ +#define SYSCTRL_VREG_RESETVALUE 0x0000ul /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */ + +#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */ +#define SYSCTRL_VREG_RUNSTDBY (0x1ul << SYSCTRL_VREG_RUNSTDBY_Pos) +#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */ +#define SYSCTRL_VREG_FORCELDO (0x1ul << SYSCTRL_VREG_FORCELDO_Pos) +#define SYSCTRL_VREG_MASK 0x2040ul /**< \brief (SYSCTRL_VREG) MASK Register */ + +/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */ + uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_VREF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */ +#define SYSCTRL_VREF_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */ + +#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */ +#define SYSCTRL_VREF_TSEN (0x1ul << SYSCTRL_VREF_TSEN_Pos) +#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */ +#define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos) +#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */ +#define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos) +#define SYSCTRL_VREF_CALIB(value) (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)) +#define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */ + +/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SYSCTRL_DPLLCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */ +#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80ul /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */ + +#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */ +#define SYSCTRL_DPLLCTRLA_ENABLE (0x1ul << SYSCTRL_DPLLCTRLA_ENABLE_Pos) +#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */ +#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1ul << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos) +#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */ +#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1ul << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) +#define SYSCTRL_DPLLCTRLA_MASK 0xC2ul /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */ + +/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_DPLLRATIO_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */ +#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ + +#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */ +#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos) +#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)) +#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ +#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos) +#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)) +#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */ + +/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ + uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ + uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ + uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} SYSCTRL_DPLLCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */ +#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000ul /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */ + +#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ +#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos) +#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)) +#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */ +#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */ +#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */ +#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3ul /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */ +#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) +#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) +#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) +#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos) +#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */ +#define SYSCTRL_DPLLCTRLB_LPEN (0x1ul << SYSCTRL_DPLLCTRLB_LPEN_Pos) +#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */ +#define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos) +#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */ +#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos) +#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)) +#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */ +#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */ +#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */ +#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) +#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) +#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos) +#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */ +#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos) +#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)) +#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */ +#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */ +#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */ +#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */ +#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */ +#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) +#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) +#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) +#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) +#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos) +#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */ +#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) +#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */ +#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos) +#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)) +#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */ + +/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ + uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */ + uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */ + uint8_t DIV:1; /*!< bit: 3 Divider Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} SYSCTRL_DPLLSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */ +#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00ul /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */ + +#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */ +#define SYSCTRL_DPLLSTATUS_LOCK (0x1ul << SYSCTRL_DPLLSTATUS_LOCK_Pos) +#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */ +#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1ul << SYSCTRL_DPLLSTATUS_CLKRDY_Pos) +#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */ +#define SYSCTRL_DPLLSTATUS_ENABLE (0x1ul << SYSCTRL_DPLLSTATUS_ENABLE_Pos) +#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */ +#define SYSCTRL_DPLLSTATUS_DIV (0x1ul << SYSCTRL_DPLLSTATUS_DIV_Pos) +#define SYSCTRL_DPLLSTATUS_MASK 0x0Ful /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */ + +/** \brief SYSCTRL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ + __IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ + __IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ + __I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ + __IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ + RoReg8 Reserved1[0x2]; + __IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ + RoReg8 Reserved2[0x2]; + __IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ + __IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ + RoReg8 Reserved3[0x3]; + __IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */ + __IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */ + RoReg8 Reserved4[0x2]; + __IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */ + __IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */ + __IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */ + RoReg8 Reserved5[0x3]; + __IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */ + RoReg8 Reserved6[0x4]; + __IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */ + RoReg8 Reserved7[0x2]; + __IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */ + __IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */ + RoReg8 Reserved8[0x3]; + __IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */ + __IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */ + __I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */ +} Sysctrl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Register definition for SYSCTRL peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ +#define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ +#define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ +#define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ +#define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ +#define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ +#define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ +#define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ +#define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ +#define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ +#define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ +#define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ +#define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ +#define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ +#define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ +#define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ +#else +#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ +#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ +#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ +#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ +#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ +#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ +#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ +#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ +#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ +#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ +#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ +#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ +#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ +#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ +#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ +#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ +#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ +#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ +#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ +#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for SYSCTRL peripheral ========== */ +#define SYSCTRL_BGAP_CALIB_MSB 11 +#define SYSCTRL_BOD33_CALIB_MSB 5 +#define SYSCTRL_DFLL48M_COARSE_MSB 5 +#define SYSCTRL_DFLL48M_FINE_MSB 9 +#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 +#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL +#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K +#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 +#define SYSCTRL_POR33_ENTEST_MSB 1 +#define SYSCTRL_SYSTEM_CLOCK 1000000 // Initial system clock frequency +#define SYSCTRL_ULPVREF_DIVLEV_MSB 3 +#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 +#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 +#define SYSCTRL_VREF_CONTROL_MSB 48 +#define SYSCTRL_VREF_STATUS_MSB 7 +#define SYSCTRL_VREG_LEVEL_MSB 2 +#define SYSCTRL_BOD12_VERSION 0x112 +#define SYSCTRL_BOD33_VERSION 0x112 +#define SYSCTRL_DFLL48M_VERSION 0x301 +#define SYSCTRL_FDPLL_VERSION 0x111 +#define SYSCTRL_OSCULP32K_VERSION 0x111 +#define SYSCTRL_OSC8M_VERSION 0x120 +#define SYSCTRL_OSC32K_VERSION 0x112 +#define SYSCTRL_VREF_VERSION 0x201 +#define SYSCTRL_VREG_VERSION 0x201 +#define SYSCTRL_XOSC_VERSION 0x114 +#define SYSCTRL_XOSC32K_VERSION 0x113 + + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_tc.h b/arch/arm/SAM_D2X/hdi/inc/hdi_tc.h new file mode 100644 index 00000000..5f1a6fbb --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_tc.h @@ -0,0 +1,955 @@ +#ifndef _HDI_TC_H_ +#define _HDI_TC_H_ + +#define TC_U2212 +#define REV_TC 0x131 + +/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ +#define TC_CTRLA_RESETVALUE 0x0000ul /**< \brief (TC_CTRLA reset_value) Control A */ + +#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ +#define TC_CTRLA_SWRST (0x1ul << TC_CTRLA_SWRST_Pos) +#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ +#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos) +#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */ +#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)) +#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */ +#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */ +#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */ +#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) +#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */ +#define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos) +#define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)) +#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */ +#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */ +#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */ +#define TC_CTRLA_WAVEGEN_MPWM_Val 0x3ul /**< \brief (TC_CTRLA) */ +#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos) +#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos) +#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos) +#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos) +#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ +#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)) +#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ +#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ +#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ +#define TC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ +#define TC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ +#define TC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ +#define TC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ +#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ +#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) +#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */ +#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos) +#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ +#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)) +#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ +#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ +#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */ +#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) +#define TC_CTRLA_MASK 0x3F6Ful /**< \brief (TC_CTRLA) MASK Register */ + +/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ + uint16_t :9; /*!< bit: 5..13 Reserved */ + uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ + uint16_t RREQ:1; /*!< bit: 15 Read Request */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TC_READREQ_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */ +#define TC_READREQ_RESETVALUE 0x0000ul /**< \brief (TC_READREQ reset_value) Read Request */ + +#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */ +#define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos) +#define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)) +#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */ +#define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos) +#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */ +#define TC_READREQ_RREQ (0x1ul << TC_READREQ_RREQ_Pos) +#define TC_READREQ_MASK 0xC01Ful /**< \brief (TC_READREQ) MASK Register */ + +/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_CTRLBCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ +#define TC_CTRLBCLR_RESETVALUE 0x02ul /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ + +#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ +#define TC_CTRLBCLR_DIR (0x1ul << TC_CTRLBCLR_DIR_Pos) +#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */ +#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos) +#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */ +#define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)) +#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */ +#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ +#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */ +#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) +#define TC_CTRLBCLR_MASK 0xC5ul /**< \brief (TC_CTRLBCLR) MASK Register */ + +/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t :3; /*!< bit: 3.. 5 Reserved */ + uint8_t CMD:2; /*!< bit: 6.. 7 Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_CTRLBSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ +#define TC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TC_CTRLBSET reset_value) Control B Set */ + +#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ +#define TC_CTRLBSET_DIR (0x1ul << TC_CTRLBSET_DIR_Pos) +#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */ +#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos) +#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */ +#define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)) +#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */ +#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ +#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */ +#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) +#define TC_CTRLBSET_MASK 0xC5ul /**< \brief (TC_CTRLBSET) MASK Register */ + +/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ + uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ + uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_CTRLC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */ +#define TC_CTRLC_RESETVALUE 0x00ul /**< \brief (TC_CTRLC reset_value) Control C */ + +#define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */ +#define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos) +#define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */ +#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos) +#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */ +#define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos) +#define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)) +#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */ +#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos) +#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */ +#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos) +#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */ +#define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos) +#define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)) +#define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */ + +/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */ +#define TC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TC_DBGCTRL reset_value) Debug Control */ + +#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */ +#define TC_DBGCTRL_DBGRUN (0x1ul << TC_DBGCTRL_DBGRUN_Pos) +#define TC_DBGCTRL_MASK 0x01ul /**< \brief (TC_DBGCTRL) MASK Register */ + +/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ + uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ + uint16_t :3; /*!< bit: 9..11 Reserved */ + uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ + uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :12; /*!< bit: 0..11 Reserved */ + uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */ +#define TC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (TC_EVCTRL reset_value) Event Control */ + +#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ +#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)) +#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */ +#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ +#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */ +#define TC_EVCTRL_EVACT_START_Val 0x3ul /**< \brief (TC_EVCTRL) Start TC on event */ +#define TC_EVCTRL_EVACT_PPW_Val 0x5ul /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */ +#define TC_EVCTRL_EVACT_PWP_Val 0x6ul /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */ +#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) +#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */ +#define TC_EVCTRL_TCINV (0x1ul << TC_EVCTRL_TCINV_Pos) +#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */ +#define TC_EVCTRL_TCEI (0x1ul << TC_EVCTRL_TCEI_Pos) +#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */ +#define TC_EVCTRL_OVFEO (0x1ul << TC_EVCTRL_OVFEO_Pos) +#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ +#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) +#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ +#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) +#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */ +#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos) +#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)) +#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */ + +/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ +#define TC_INTENCLR_RESETVALUE 0x00ul /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */ +#define TC_INTENCLR_OVF (0x1ul << TC_INTENCLR_OVF_Pos) +#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */ +#define TC_INTENCLR_ERR (0x1ul << TC_INTENCLR_ERR_Pos) +#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define TC_INTENCLR_SYNCRDY (0x1ul << TC_INTENCLR_SYNCRDY_Pos) +#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ +#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) +#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ +#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) +#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */ +#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos) +#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)) +#define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */ + +/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ + uint8_t :1; /*!< bit: 2 Reserved */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ + uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ +#define TC_INTENSET_RESETVALUE 0x00ul /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ + +#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */ +#define TC_INTENSET_OVF (0x1ul << TC_INTENSET_OVF_Pos) +#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */ +#define TC_INTENSET_ERR (0x1ul << TC_INTENSET_ERR_Pos) +#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */ +#define TC_INTENSET_SYNCRDY (0x1ul << TC_INTENSET_SYNCRDY_Pos) +#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ +#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) +#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ +#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) +#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */ +#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos) +#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)) +#define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */ + +/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t OVF:1; /*!< bit: 0 Overflow */ + __I uint8_t ERR:1; /*!< bit: 1 Error */ + __I uint8_t :1; /*!< bit: 2 Reserved */ + __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ + __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ + __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} TC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TC_INTFLAG_RESETVALUE 0x00ul /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */ +#define TC_INTFLAG_OVF (0x1ul << TC_INTFLAG_OVF_Pos) +#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */ +#define TC_INTFLAG_ERR (0x1ul << TC_INTFLAG_ERR_Pos) +#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */ +#define TC_INTFLAG_SYNCRDY (0x1ul << TC_INTFLAG_SYNCRDY_Pos) +#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */ +#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) +#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */ +#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) +#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */ +#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos) +#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)) +#define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */ + +/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :3; /*!< bit: 0.. 2 Reserved */ + uint8_t STOP:1; /*!< bit: 3 Stop */ + uint8_t SLAVE:1; /*!< bit: 4 Slave */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */ +#define TC_STATUS_RESETVALUE 0x08ul /**< \brief (TC_STATUS reset_value) Status */ + +#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */ +#define TC_STATUS_STOP (0x1ul << TC_STATUS_STOP_Pos) +#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */ +#define TC_STATUS_SLAVE (0x1ul << TC_STATUS_SLAVE_Pos) +#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */ +#define TC_STATUS_SYNCBUSY (0x1ul << TC_STATUS_SYNCBUSY_Pos) +#define TC_STATUS_MASK 0x98ul /**< \brief (TC_STATUS) MASK Register */ + +/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COUNT:16; /*!< bit: 0..15 Count Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TC_COUNT16_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */ +#define TC_COUNT16_COUNT_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */ + +#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */ +#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos) +#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)) +#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */ + +/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t COUNT:32; /*!< bit: 0..31 Count Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TC_COUNT32_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */ +#define TC_COUNT32_COUNT_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */ + +#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */ +#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos) +#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)) +#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */ + +/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */ +#define TC_COUNT8_COUNT_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */ + +#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ +#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos) +#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)) +#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */ + +/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_PER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */ +#define TC_COUNT8_PER_RESETVALUE 0xFFul /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */ + +#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ +#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos) +#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)) +#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */ + +/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} TC_COUNT16_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */ +#define TC_COUNT16_CC_RESETVALUE 0x0000ul /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */ + +#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */ +#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos) +#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)) +#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */ + +/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TC_COUNT32_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */ +#define TC_COUNT32_CC_RESETVALUE 0x00000000ul /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */ + +#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */ +#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos) +#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)) +#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */ + +/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TC_COUNT8_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */ +#define TC_COUNT8_CC_RESETVALUE 0x00ul /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */ + +#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */ +#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos) +#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)) +#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */ + +/** \brief TC_COUNT8 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 8-bit Counter Mode */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ + RoReg8 Reserved3[0x3]; + __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ + RoReg8 Reserved4[0x3]; + __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ +} TcCount8; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief TC_COUNT16 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 16-bit Counter Mode */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ + RoReg8 Reserved3[0x6]; + __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ +} TcCount16; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief TC_COUNT32 hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* 32-bit Counter Mode */ + __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ + __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ + RoReg8 Reserved1[0x1]; + __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x1]; + __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ + __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ + __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ + __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ + __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ + __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ + RoReg8 Reserved3[0x4]; + __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ +} TcCount32; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ + TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ + TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* TC3 Inst */ +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC3_CTRLA (0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_READREQ (0x42002C02U) /**< \brief (TC3) Read Request */ +#define REG_TC3_CTRLBCLR (0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_CTRLC (0x42002C06U) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (0x42002C08U) /**< \brief (TC3) Debug Control */ +#define REG_TC3_EVCTRL (0x42002C0AU) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (0x42002C0FU) /**< \brief (TC3) Status */ +#define REG_TC3_COUNT16_COUNT (0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ +#define REG_TC3_COUNT16_CC0 (0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ +#define REG_TC3_COUNT16_CC1 (0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ +#define REG_TC3_COUNT32_COUNT (0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ +#define REG_TC3_COUNT32_CC0 (0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ +#define REG_TC3_COUNT32_CC1 (0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ +#define REG_TC3_COUNT8_COUNT (0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ +#define REG_TC3_COUNT8_PER (0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ +#define REG_TC3_COUNT8_CC0 (0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ +#define REG_TC3_COUNT8_CC1 (0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00U) /**< \brief (TC3) Control A */ +#define REG_TC3_READREQ (*(RwReg16*)0x42002C02U) /**< \brief (TC3) Read Request */ +#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04U) /**< \brief (TC3) Control B Clear */ +#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05U) /**< \brief (TC3) Control B Set */ +#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06U) /**< \brief (TC3) Control C */ +#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08U) /**< \brief (TC3) Debug Control */ +#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AU) /**< \brief (TC3) Event Control */ +#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CU) /**< \brief (TC3) Interrupt Enable Clear */ +#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DU) /**< \brief (TC3) Interrupt Enable Set */ +#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EU) /**< \brief (TC3) Interrupt Flag Status and Clear */ +#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FU) /**< \brief (TC3) Status */ +#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10U) /**< \brief (TC3) COUNT16 Counter Value */ +#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18U) /**< \brief (TC3) COUNT16 Compare/Capture 0 */ +#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AU) /**< \brief (TC3) COUNT16 Compare/Capture 1 */ +#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10U) /**< \brief (TC3) COUNT32 Counter Value */ +#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18U) /**< \brief (TC3) COUNT32 Compare/Capture 0 */ +#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CU) /**< \brief (TC3) COUNT32 Compare/Capture 1 */ +#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10U) /**< \brief (TC3) COUNT8 Counter Value */ +#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14U) /**< \brief (TC3) COUNT8 Period Value */ +#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18U) /**< \brief (TC3) COUNT8 Compare/Capture 0 */ +#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19U) /**< \brief (TC3) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC3 peripheral ========== */ +#define TC3_CC8_NUM 2 // Number of 8-bit Counters +#define TC3_CC16_NUM 2 // Number of 16-bit Counters +#define TC3_CC32_NUM 2 // Number of 32-bit Counters +#define TC3_DITHERING_EXT 0 // Dithering feature implemented +#define TC3_DMAC_ID_MC_0 25 +#define TC3_DMAC_ID_MC_1 26 +#define TC3_DMAC_ID_MC_LSB 25 +#define TC3_DMAC_ID_MC_MSB 26 +#define TC3_DMAC_ID_MC_SIZE 2 +#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger +#define TC3_GCLK_ID 27 // Index of Generic Clock +#define TC3_MASTER 0 +#define TC3_OW_NUM 2 // Number of Output Waveforms +#define TC3_PERIOD_EXT 0 // Period feature implemented +#define TC3_SHADOW_EXT 0 // Shadow feature implemented + +/* TC4 Inst */ +/* ========== Register definition for TC4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC4_CTRLA (0x42003000U) /**< \brief (TC4) Control A */ +#define REG_TC4_READREQ (0x42003002U) /**< \brief (TC4) Read Request */ +#define REG_TC4_CTRLBCLR (0x42003004U) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (0x42003005U) /**< \brief (TC4) Control B Set */ +#define REG_TC4_CTRLC (0x42003006U) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (0x42003008U) /**< \brief (TC4) Debug Control */ +#define REG_TC4_EVCTRL (0x4200300AU) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (0x4200300FU) /**< \brief (TC4) Status */ +#define REG_TC4_COUNT16_COUNT (0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ +#define REG_TC4_COUNT16_CC0 (0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ +#define REG_TC4_COUNT16_CC1 (0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ +#define REG_TC4_COUNT32_COUNT (0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ +#define REG_TC4_COUNT32_CC0 (0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ +#define REG_TC4_COUNT32_CC1 (0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ +#define REG_TC4_COUNT8_COUNT (0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ +#define REG_TC4_COUNT8_PER (0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ +#define REG_TC4_COUNT8_CC0 (0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ +#define REG_TC4_COUNT8_CC1 (0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC4_CTRLA (*(RwReg16*)0x42003000U) /**< \brief (TC4) Control A */ +#define REG_TC4_READREQ (*(RwReg16*)0x42003002U) /**< \brief (TC4) Read Request */ +#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004U) /**< \brief (TC4) Control B Clear */ +#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005U) /**< \brief (TC4) Control B Set */ +#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006U) /**< \brief (TC4) Control C */ +#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008U) /**< \brief (TC4) Debug Control */ +#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AU) /**< \brief (TC4) Event Control */ +#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CU) /**< \brief (TC4) Interrupt Enable Clear */ +#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DU) /**< \brief (TC4) Interrupt Enable Set */ +#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EU) /**< \brief (TC4) Interrupt Flag Status and Clear */ +#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FU) /**< \brief (TC4) Status */ +#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010U) /**< \brief (TC4) COUNT16 Counter Value */ +#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018U) /**< \brief (TC4) COUNT16 Compare/Capture 0 */ +#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AU) /**< \brief (TC4) COUNT16 Compare/Capture 1 */ +#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010U) /**< \brief (TC4) COUNT32 Counter Value */ +#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018U) /**< \brief (TC4) COUNT32 Compare/Capture 0 */ +#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CU) /**< \brief (TC4) COUNT32 Compare/Capture 1 */ +#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010U) /**< \brief (TC4) COUNT8 Counter Value */ +#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014U) /**< \brief (TC4) COUNT8 Period Value */ +#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018U) /**< \brief (TC4) COUNT8 Compare/Capture 0 */ +#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019U) /**< \brief (TC4) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC4 peripheral ========== */ +#define TC4_CC8_NUM 2 // Number of 8-bit Counters +#define TC4_CC16_NUM 2 // Number of 16-bit Counters +#define TC4_CC32_NUM 2 // Number of 32-bit Counters +#define TC4_DITHERING_EXT 0 // Dithering feature implemented +#define TC4_DMAC_ID_MC_0 28 +#define TC4_DMAC_ID_MC_1 29 +#define TC4_DMAC_ID_MC_LSB 28 +#define TC4_DMAC_ID_MC_MSB 29 +#define TC4_DMAC_ID_MC_SIZE 2 +#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger +#define TC4_GCLK_ID 28 // Index of Generic Clock +#define TC4_MASTER 1 +#define TC4_OW_NUM 2 // Number of Output Waveforms +#define TC4_PERIOD_EXT 0 // Period feature implemented +#define TC4_SHADOW_EXT 0 // Shadow feature implemented + +/* TC5 Inst */ +/* ========== Register definition for TC5 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC5_CTRLA (0x42003400U) /**< \brief (TC5) Control A */ +#define REG_TC5_READREQ (0x42003402U) /**< \brief (TC5) Read Request */ +#define REG_TC5_CTRLBCLR (0x42003404U) /**< \brief (TC5) Control B Clear */ +#define REG_TC5_CTRLBSET (0x42003405U) /**< \brief (TC5) Control B Set */ +#define REG_TC5_CTRLC (0x42003406U) /**< \brief (TC5) Control C */ +#define REG_TC5_DBGCTRL (0x42003408U) /**< \brief (TC5) Debug Control */ +#define REG_TC5_EVCTRL (0x4200340AU) /**< \brief (TC5) Event Control */ +#define REG_TC5_INTENCLR (0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ +#define REG_TC5_INTENSET (0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ +#define REG_TC5_INTFLAG (0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ +#define REG_TC5_STATUS (0x4200340FU) /**< \brief (TC5) Status */ +#define REG_TC5_COUNT16_COUNT (0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ +#define REG_TC5_COUNT16_CC0 (0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ +#define REG_TC5_COUNT16_CC1 (0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ +#define REG_TC5_COUNT32_COUNT (0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ +#define REG_TC5_COUNT32_CC0 (0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ +#define REG_TC5_COUNT32_CC1 (0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ +#define REG_TC5_COUNT8_COUNT (0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ +#define REG_TC5_COUNT8_PER (0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ +#define REG_TC5_COUNT8_CC0 (0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ +#define REG_TC5_COUNT8_CC1 (0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC5_CTRLA (*(RwReg16*)0x42003400U) /**< \brief (TC5) Control A */ +#define REG_TC5_READREQ (*(RwReg16*)0x42003402U) /**< \brief (TC5) Read Request */ +#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404U) /**< \brief (TC5) Control B Clear */ +#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405U) /**< \brief (TC5) Control B Set */ +#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406U) /**< \brief (TC5) Control C */ +#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408U) /**< \brief (TC5) Debug Control */ +#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AU) /**< \brief (TC5) Event Control */ +#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CU) /**< \brief (TC5) Interrupt Enable Clear */ +#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DU) /**< \brief (TC5) Interrupt Enable Set */ +#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EU) /**< \brief (TC5) Interrupt Flag Status and Clear */ +#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FU) /**< \brief (TC5) Status */ +#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410U) /**< \brief (TC5) COUNT16 Counter Value */ +#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418U) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ +#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AU) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ +#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410U) /**< \brief (TC5) COUNT32 Counter Value */ +#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418U) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ +#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CU) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ +#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410U) /**< \brief (TC5) COUNT8 Counter Value */ +#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414U) /**< \brief (TC5) COUNT8 Period Value */ +#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418U) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ +#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419U) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC5 peripheral ========== */ +#define TC5_CC8_NUM 2 // Number of 8-bit Counters +#define TC5_CC16_NUM 2 // Number of 16-bit Counters +#define TC5_CC32_NUM 2 // Number of 32-bit Counters +#define TC5_DITHERING_EXT 0 // Dithering feature implemented +#define TC5_DMAC_ID_MC_0 31 +#define TC5_DMAC_ID_MC_1 32 +#define TC5_DMAC_ID_MC_LSB 31 +#define TC5_DMAC_ID_MC_MSB 32 +#define TC5_DMAC_ID_MC_SIZE 2 +#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger +#define TC5_GCLK_ID 28 // Index of Generic Clock +#define TC5_MASTER 0 +#define TC5_OW_NUM 2 // Number of Output Waveforms +#define TC5_PERIOD_EXT 0 // Period feature implemented +#define TC5_SHADOW_EXT 0 // Shadow feature implemented +/* TC6 Inst */ +/* ========== Register definition for TC6 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC6_CTRLA (0x42003800U) /**< \brief (TC6) Control A */ +#define REG_TC6_READREQ (0x42003802U) /**< \brief (TC6) Read Request */ +#define REG_TC6_CTRLBCLR (0x42003804U) /**< \brief (TC6) Control B Clear */ +#define REG_TC6_CTRLBSET (0x42003805U) /**< \brief (TC6) Control B Set */ +#define REG_TC6_CTRLC (0x42003806U) /**< \brief (TC6) Control C */ +#define REG_TC6_DBGCTRL (0x42003808U) /**< \brief (TC6) Debug Control */ +#define REG_TC6_EVCTRL (0x4200380AU) /**< \brief (TC6) Event Control */ +#define REG_TC6_INTENCLR (0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */ +#define REG_TC6_INTENSET (0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */ +#define REG_TC6_INTFLAG (0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */ +#define REG_TC6_STATUS (0x4200380FU) /**< \brief (TC6) Status */ +#define REG_TC6_COUNT16_COUNT (0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */ +#define REG_TC6_COUNT16_CC0 (0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ +#define REG_TC6_COUNT16_CC1 (0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ +#define REG_TC6_COUNT32_COUNT (0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */ +#define REG_TC6_COUNT32_CC0 (0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ +#define REG_TC6_COUNT32_CC1 (0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ +#define REG_TC6_COUNT8_COUNT (0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */ +#define REG_TC6_COUNT8_PER (0x42003814U) /**< \brief (TC6) COUNT8 Period Value */ +#define REG_TC6_COUNT8_CC0 (0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ +#define REG_TC6_COUNT8_CC1 (0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC6_CTRLA (*(RwReg16*)0x42003800U) /**< \brief (TC6) Control A */ +#define REG_TC6_READREQ (*(RwReg16*)0x42003802U) /**< \brief (TC6) Read Request */ +#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804U) /**< \brief (TC6) Control B Clear */ +#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805U) /**< \brief (TC6) Control B Set */ +#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806U) /**< \brief (TC6) Control C */ +#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808U) /**< \brief (TC6) Debug Control */ +#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AU) /**< \brief (TC6) Event Control */ +#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CU) /**< \brief (TC6) Interrupt Enable Clear */ +#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DU) /**< \brief (TC6) Interrupt Enable Set */ +#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EU) /**< \brief (TC6) Interrupt Flag Status and Clear */ +#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FU) /**< \brief (TC6) Status */ +#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810U) /**< \brief (TC6) COUNT16 Counter Value */ +#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818U) /**< \brief (TC6) COUNT16 Compare/Capture 0 */ +#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AU) /**< \brief (TC6) COUNT16 Compare/Capture 1 */ +#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810U) /**< \brief (TC6) COUNT32 Counter Value */ +#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818U) /**< \brief (TC6) COUNT32 Compare/Capture 0 */ +#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CU) /**< \brief (TC6) COUNT32 Compare/Capture 1 */ +#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810U) /**< \brief (TC6) COUNT8 Counter Value */ +#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814U) /**< \brief (TC6) COUNT8 Period Value */ +#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818U) /**< \brief (TC6) COUNT8 Compare/Capture 0 */ +#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819U) /**< \brief (TC6) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC6 peripheral ========== */ +#define TC6_CC8_NUM 2 // Number of 8-bit Counters +#define TC6_CC16_NUM 2 // Number of 16-bit Counters +#define TC6_CC32_NUM 2 // Number of 32-bit Counters +#define TC6_DITHERING_EXT 0 // Dithering feature implemented +#define TC6_DMAC_ID_MC_0 34 +#define TC6_DMAC_ID_MC_1 35 +#define TC6_DMAC_ID_MC_LSB 34 +#define TC6_DMAC_ID_MC_MSB 35 +#define TC6_DMAC_ID_MC_SIZE 2 +#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger +#define TC6_GCLK_ID 29 // Index of Generic Clock +#define TC6_MASTER 1 +#define TC6_OW_NUM 2 // Number of Output Waveforms +#define TC6_PERIOD_EXT 0 // Period feature implemented +#define TC6_SHADOW_EXT 0 // Shadow feature implemented +/* TC7 Inst */ +/* ========== Register definition for TC7 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TC7_CTRLA (0x42003C00U) /**< \brief (TC7) Control A */ +#define REG_TC7_READREQ (0x42003C02U) /**< \brief (TC7) Read Request */ +#define REG_TC7_CTRLBCLR (0x42003C04U) /**< \brief (TC7) Control B Clear */ +#define REG_TC7_CTRLBSET (0x42003C05U) /**< \brief (TC7) Control B Set */ +#define REG_TC7_CTRLC (0x42003C06U) /**< \brief (TC7) Control C */ +#define REG_TC7_DBGCTRL (0x42003C08U) /**< \brief (TC7) Debug Control */ +#define REG_TC7_EVCTRL (0x42003C0AU) /**< \brief (TC7) Event Control */ +#define REG_TC7_INTENCLR (0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */ +#define REG_TC7_INTENSET (0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */ +#define REG_TC7_INTFLAG (0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */ +#define REG_TC7_STATUS (0x42003C0FU) /**< \brief (TC7) Status */ +#define REG_TC7_COUNT16_COUNT (0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */ +#define REG_TC7_COUNT16_CC0 (0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ +#define REG_TC7_COUNT16_CC1 (0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ +#define REG_TC7_COUNT32_COUNT (0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */ +#define REG_TC7_COUNT32_CC0 (0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ +#define REG_TC7_COUNT32_CC1 (0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ +#define REG_TC7_COUNT8_COUNT (0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */ +#define REG_TC7_COUNT8_PER (0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */ +#define REG_TC7_COUNT8_CC0 (0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ +#define REG_TC7_COUNT8_CC1 (0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ +#else +#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00U) /**< \brief (TC7) Control A */ +#define REG_TC7_READREQ (*(RwReg16*)0x42003C02U) /**< \brief (TC7) Read Request */ +#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04U) /**< \brief (TC7) Control B Clear */ +#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05U) /**< \brief (TC7) Control B Set */ +#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06U) /**< \brief (TC7) Control C */ +#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08U) /**< \brief (TC7) Debug Control */ +#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AU) /**< \brief (TC7) Event Control */ +#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CU) /**< \brief (TC7) Interrupt Enable Clear */ +#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DU) /**< \brief (TC7) Interrupt Enable Set */ +#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EU) /**< \brief (TC7) Interrupt Flag Status and Clear */ +#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FU) /**< \brief (TC7) Status */ +#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10U) /**< \brief (TC7) COUNT16 Counter Value */ +#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18U) /**< \brief (TC7) COUNT16 Compare/Capture 0 */ +#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AU) /**< \brief (TC7) COUNT16 Compare/Capture 1 */ +#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10U) /**< \brief (TC7) COUNT32 Counter Value */ +#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18U) /**< \brief (TC7) COUNT32 Compare/Capture 0 */ +#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CU) /**< \brief (TC7) COUNT32 Compare/Capture 1 */ +#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10U) /**< \brief (TC7) COUNT8 Counter Value */ +#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14U) /**< \brief (TC7) COUNT8 Period Value */ +#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18U) /**< \brief (TC7) COUNT8 Compare/Capture 0 */ +#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19U) /**< \brief (TC7) COUNT8 Compare/Capture 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TC7 peripheral ========== */ +#define TC7_CC8_NUM 2 // Number of 8-bit Counters +#define TC7_CC16_NUM 2 // Number of 16-bit Counters +#define TC7_CC32_NUM 2 // Number of 32-bit Counters +#define TC7_DITHERING_EXT 0 // Dithering feature implemented +#define TC7_DMAC_ID_MC_0 37 +#define TC7_DMAC_ID_MC_1 38 +#define TC7_DMAC_ID_MC_LSB 37 +#define TC7_DMAC_ID_MC_MSB 38 +#define TC7_DMAC_ID_MC_SIZE 2 +#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger +#define TC7_GCLK_ID 29 // Index of Generic Clock +#define TC7_MASTER 0 +#define TC7_OW_NUM 2 // Number of Output Waveforms +#define TC7_PERIOD_EXT 0 // Period feature implemented +#define TC7_SHADOW_EXT 0 // Shadow feature implemented +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_tcc.h b/arch/arm/SAM_D2X/hdi/inc/hdi_tcc.h new file mode 100644 index 00000000..32792231 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_tcc.h @@ -0,0 +1,2098 @@ +#ifndef _HDI_TCC_H_ +#define _HDI_TCC_H_ + +/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t :9; /*!< bit: 15..23 Reserved */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ +#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ + +#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ +#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) +#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ +#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) +#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ +#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)) +#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ +#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ +#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ +#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)) +#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ +#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ +#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ +#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ +#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ +#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ +#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ +#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ +#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ +#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) +#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ +#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)) +#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ +#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ +#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ +#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ +#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) +#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ +#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) +#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ +#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) +#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ +#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) +#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ +#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) +#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ +#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) +#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)) +#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */ + +/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ +#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ + +#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ +#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) +#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ +#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) +#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ +#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) +#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ +#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)) +#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ +#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)) +#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ +#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ +#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ +#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */ +#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ +#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ + +/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ +#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ + +#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ +#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) +#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ +#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) +#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ +#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) +#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ +#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)) +#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ +#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)) +#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ +#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ +#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ +#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */ +#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ +#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ + +/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ + uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ + uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ + uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ + uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ + uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ + uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :7; /*!< bit: 12..18 Reserved */ + uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ +#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ + +#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ +#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) +#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ +#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) +#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ +#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) +#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ +#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) +#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ +#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) +#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ +#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) +#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ +#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) +#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */ +#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) +#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ +#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) +#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ +#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) +#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ +#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) +#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ +#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) +#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ +#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) +#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)) +#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */ +#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos) +#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */ +#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos) +#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */ +#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos) +#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */ +#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos) +#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */ +#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos) +#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */ +#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos) +#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */ +#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos) +#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */ +#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos) +#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)) +#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ + +/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ +#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ + +#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ +#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)) +#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ +#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ +#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) +#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ +#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) +#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ +#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)) +#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */ +#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ +#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) +#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ +#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)) +#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ +#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ +#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ +#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ +#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ +#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)) +#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ +#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ +#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ +#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ +#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ +#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)) +#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ +#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ +#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ +#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ +#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ +#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ +#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ +#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */ +#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ +#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) +#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)) +#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ +#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) +#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)) +#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */ + +/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ +#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ + +#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ +#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)) +#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ +#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ +#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) +#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ +#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) +#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ +#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)) +#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */ +#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ +#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) +#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ +#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)) +#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ +#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ +#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ +#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ +#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ +#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)) +#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ +#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ +#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ +#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ +#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ +#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)) +#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ +#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ +#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ +#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ +#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ +#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ +#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ +#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */ +#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ +#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) +#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)) +#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ +#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) +#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)) +#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */ + +/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WEXCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ +#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ + +#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ +#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) +#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)) +#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ +#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) +#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ +#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) +#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ +#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) +#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ +#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) +#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ +#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) +#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)) +#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ +#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) +#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)) +#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ +#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) +#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)) +#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ + +/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_DRVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ +#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ + +#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ +#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) +#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ +#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) +#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ +#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) +#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ +#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) +#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ +#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) +#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ +#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) +#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ +#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) +#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ +#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) +#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ +#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) +#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)) +#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ +#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) +#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ +#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) +#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ +#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) +#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ +#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) +#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ +#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) +#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ +#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) +#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ +#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) +#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ +#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) +#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ +#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) +#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)) +#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ +#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) +#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ +#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) +#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ +#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) +#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ +#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) +#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ +#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) +#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ +#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) +#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ +#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) +#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ +#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) +#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ +#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) +#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)) +#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) +#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)) +#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) +#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)) +#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ + +/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ +#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ + +#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ +#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) +#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ +#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) +#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ + +/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ +#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ + +#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ +#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)) +#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ +#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ +#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ +#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ +#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ +#define TCC_EVCTRL_EVACT0_STAMP_Val 0x6ul /**< \brief (TCC_EVCTRL) Stamp capture */ +#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ +#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)) +#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ +#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ +#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ +#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ +#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ +#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ +#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ +#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)) +#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ +#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ +#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ +#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) +#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ +#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) +#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ +#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) +#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ +#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) +#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ +#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) +#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ +#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) +#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)) +#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ +#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) +#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ +#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) +#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ +#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) +#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)) +#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ +#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) +#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ +#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) +#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ +#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) +#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ +#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) +#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ +#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) +#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)) +#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ +#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) +#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ +#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) +#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ +#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) +#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ +#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) +#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ +#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) +#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)) +#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ + +/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ +#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ +#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) +#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ +#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) +#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ +#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) +#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ +#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) +#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */ +#define TCC_INTENCLR_UFS (0x1ul << TCC_INTENCLR_UFS_Pos) +#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) +#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) +#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) +#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) +#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) +#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) +#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) +#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) +#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) +#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) +#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)) +#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */ + +/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ +#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ + +#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ +#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) +#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ +#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) +#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ +#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) +#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ +#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) +#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */ +#define TCC_INTENSET_UFS (0x1ul << TCC_INTENSET_UFS_Pos) +#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) +#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) +#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) +#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) +#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) +#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) +#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) +#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) +#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) +#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) +#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)) +#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */ + +/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint32_t OVF:1; /*!< bit: 0 Overflow */ + __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ + __I uint32_t CNT:1; /*!< bit: 2 Counter */ + __I uint32_t ERR:1; /*!< bit: 3 Error */ + __I uint32_t :6; /*!< bit: 4.. 9 Reserved */ + __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ + __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint32_t :16; /*!< bit: 0..15 Reserved */ + __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ +#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) +#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ +#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) +#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ +#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) +#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ +#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) +#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */ +#define TCC_INTFLAG_UFS (0x1ul << TCC_INTFLAG_UFS_Pos) +#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ +#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) +#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ +#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) +#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ +#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) +#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ +#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) +#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ +#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) +#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ +#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) +#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ +#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) +#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ +#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) +#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ +#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) +#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ +#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) +#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)) +#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */ + +/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ +#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ + +#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ +#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) +#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ +#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) +#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */ +#define TCC_STATUS_UFS (0x1ul << TCC_STATUS_UFS_Pos) +#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ +#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) +#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ +#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) +#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ +#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos) +#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ +#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos) +#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ +#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos) +#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ +#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) +#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ +#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) +#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ +#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) +#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ +#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) +#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ +#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) +#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ +#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) +#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ +#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) +#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ +#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) +#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ +#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos) +#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ +#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos) +#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ +#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos) +#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ +#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos) +#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ +#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos) +#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)) +#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ +#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) +#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ +#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) +#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ +#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) +#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ +#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) +#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ +#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) +#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)) +#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */ + +/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ +#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ + +// DITH4 mode +#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ +#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) +#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)) +#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ +#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) +#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)) +#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ +#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) +#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)) +#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ + +#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ +#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) +#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)) +#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ + +/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ +#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ + +#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ +#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) +#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ +#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) +#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ +#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) +#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ +#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) +#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ +#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) +#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ +#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) +#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ +#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) +#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ +#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) +#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ +#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) +#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)) +#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ +#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) +#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ +#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) +#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ +#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) +#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ +#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) +#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ +#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) +#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ +#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) +#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ +#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) +#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ +#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) +#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ +#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) +#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)) +#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ + +/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ +#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ + +#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ +#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)) +#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ +#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ +#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ +#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ +#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ +#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)) +#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ +#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVE) Critical RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ +#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) +#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ +#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) +#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ +#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) +#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ +#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) +#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ +#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) +#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ +#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) +#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)) +#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ +#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) +#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ +#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) +#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ +#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) +#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ +#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) +#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ +#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) +#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)) +#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ +#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) +#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ +#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) +#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ +#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) +#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ +#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) +#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ +#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) +#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)) +#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ + +/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ +#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ + +// DITH4 mode +#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ +#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos) +#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)) +#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ +#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) +#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)) +#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ +#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos) +#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)) +#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ +#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) +#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)) +#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ +#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos) +#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)) +#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ +#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) +#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)) +#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ + +#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ +#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) +#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)) +#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ + +/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ +#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ + +// DITH4 mode +#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ +#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos) +#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)) +#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ +#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) +#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)) +#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ +#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos) +#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)) +#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ +#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) +#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)) +#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ +#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos) +#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)) +#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ +#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) +#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)) +#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ + +#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ +#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) +#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)) +#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ + +/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATTB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */ +#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */ + +#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */ +#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos) +#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */ +#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos) +#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */ +#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos) +#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */ +#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos) +#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */ +#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos) +#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */ +#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos) +#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */ +#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos) +#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */ +#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos) +#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */ +#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos) +#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)) +#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */ +#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos) +#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */ +#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos) +#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */ +#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos) +#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */ +#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos) +#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */ +#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos) +#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */ +#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos) +#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */ +#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos) +#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */ +#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos) +#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */ +#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos) +#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)) +#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */ + +/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVEB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */ +#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */ + +#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */ +#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)) +#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */ +#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */ +#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */ +#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */ +#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */ +#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)) +#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */ +#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */ +#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */ +#define TCC_WAVEB_RAMPB_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVEB) Critical RAMP2 operation */ +#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2C (TCC_WAVEB_RAMPB_RAMP2C_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */ +#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos) +#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */ +#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos) +#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */ +#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos) +#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */ +#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos) +#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */ +#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos) +#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */ +#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos) +#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)) +#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */ +#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos) +#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */ +#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos) +#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */ +#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos) +#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */ +#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos) +#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */ +#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos) +#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)) +#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */ +#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos) +#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */ +#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos) +#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */ +#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos) +#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */ +#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos) +#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */ +#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos) +#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)) +#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */ + +/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PERB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */ +#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */ + +// DITH4 mode +#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos) +#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)) +#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */ +#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos) +#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)) +#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos) +#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)) +#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */ +#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos) +#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)) +#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos) +#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)) +#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */ +#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos) +#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)) +#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */ + +#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */ +#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos) +#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)) +#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */ + +/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CCB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */ +#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */ + +// DITH4 mode +#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos) +#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)) +#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos) +#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)) +#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos) +#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)) +#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos) +#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)) +#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos) +#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)) +#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos) +#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)) +#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */ + +#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos) +#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)) +#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */ + +/** \brief TCC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ +} Tcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* TCC Inst 0 */ +/* ========== Register definition for TCC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#else +#define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */ +#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */ +#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */ +#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */ +#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */ +#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */ +#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */ +#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */ +#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */ +#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */ +#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */ +#define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */ +#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */ +#define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */ +#define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */ +#define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */ +#define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */ +#define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */ +#define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */ +#define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */ +#define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */ +#define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */ +#define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */ +#define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */ +#define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */ +#define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */ +#define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */ +#define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */ +#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC0 peripheral ========== */ +#define TCC0_CC_NUM 4 // Number of Compare/Capture units +#define TCC0_DITHERING 1 // Dithering feature implemented +#define TCC0_DMAC_ID_MC_0 14 +#define TCC0_DMAC_ID_MC_1 15 +#define TCC0_DMAC_ID_MC_2 16 +#define TCC0_DMAC_ID_MC_3 17 +#define TCC0_DMAC_ID_MC_LSB 14 +#define TCC0_DMAC_ID_MC_MSB 17 +#define TCC0_DMAC_ID_MC_SIZE 4 +#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger +#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented +#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1) +#define TCC0_GCLK_ID 26 // Index of Generic Clock +#define TCC0_MASTER 0 +#define TCC0_OTMX 1 // Output Matrix feature implemented +#define TCC0_OW_NUM 8 // Number of Output Waveforms +#define TCC0_PG 1 // Pattern Generation feature implemented +#define TCC0_SIZE 24 +#define TCC0_SWAP 1 // DTI outputs swap feature implemented +#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave + +/* TCC Inst 1 */ +/* ========== Register definition for TCC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#else +#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */ +#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */ +#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */ +#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */ +#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ +#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ +#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */ +#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */ +#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */ +#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ +#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ +#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ +#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */ +#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */ +#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */ +#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */ +#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */ +#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ +#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ +#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */ +#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ +#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */ +#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ +#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC1 peripheral ========== */ +#define TCC1_CC_NUM 2 // Number of Compare/Capture units +#define TCC1_DITHERING 1 // Dithering feature implemented +#define TCC1_DMAC_ID_MC_0 19 +#define TCC1_DMAC_ID_MC_1 20 +#define TCC1_DMAC_ID_MC_LSB 19 +#define TCC1_DMAC_ID_MC_MSB 20 +#define TCC1_DMAC_ID_MC_SIZE 2 +#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger +#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC1_EXT 24 // Coding of implemented extended features +#define TCC1_GCLK_ID 26 // Index of Generic Clock +#define TCC1_MASTER 1 +#define TCC1_OTMX 0 // Output Matrix feature implemented +#define TCC1_OW_NUM 4 // Number of Output Waveforms +#define TCC1_PG 1 // Pattern Generation feature implemented +#define TCC1_SIZE 24 +#define TCC1_SWAP 0 // DTI outputs swap feature implemented +#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave +/* TCC Inst 2 */ +/* ========== Register definition for TCC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC2_CTRLA (0x42002800U) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (0x42002804U) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (0x42002805U) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (0x42002808U) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (0x42002818U) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (0x4200281EU) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (0x42002820U) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (0x42002830U) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (0x42002834U) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (0x4200283CU) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (0x42002840U) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEB (0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERB (0x4200286CU) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCB0 (0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCB1 (0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#else +#define REG_TCC2_CTRLA (*(RwReg *)0x42002800U) /**< \brief (TCC2) Control A */ +#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804U) /**< \brief (TCC2) Control B Clear */ +#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805U) /**< \brief (TCC2) Control B Set */ +#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808U) /**< \brief (TCC2) Synchronization Busy */ +#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CU) /**< \brief (TCC2) Recoverable Fault A Configuration */ +#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810U) /**< \brief (TCC2) Recoverable Fault B Configuration */ +#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818U) /**< \brief (TCC2) Driver Control */ +#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EU) /**< \brief (TCC2) Debug Control */ +#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820U) /**< \brief (TCC2) Event Control */ +#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824U) /**< \brief (TCC2) Interrupt Enable Clear */ +#define REG_TCC2_INTENSET (*(RwReg *)0x42002828U) /**< \brief (TCC2) Interrupt Enable Set */ +#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CU) /**< \brief (TCC2) Interrupt Flag Status and Clear */ +#define REG_TCC2_STATUS (*(RwReg *)0x42002830U) /**< \brief (TCC2) Status */ +#define REG_TCC2_COUNT (*(RwReg *)0x42002834U) /**< \brief (TCC2) Count */ +#define REG_TCC2_WAVE (*(RwReg *)0x4200283CU) /**< \brief (TCC2) Waveform Control */ +#define REG_TCC2_PER (*(RwReg *)0x42002840U) /**< \brief (TCC2) Period */ +#define REG_TCC2_CC0 (*(RwReg *)0x42002844U) /**< \brief (TCC2) Compare and Capture 0 */ +#define REG_TCC2_CC1 (*(RwReg *)0x42002848U) /**< \brief (TCC2) Compare and Capture 1 */ +#define REG_TCC2_WAVEB (*(RwReg *)0x42002868U) /**< \brief (TCC2) Waveform Control Buffer */ +#define REG_TCC2_PERB (*(RwReg *)0x4200286CU) /**< \brief (TCC2) Period Buffer */ +#define REG_TCC2_CCB0 (*(RwReg *)0x42002870U) /**< \brief (TCC2) Compare and Capture Buffer 0 */ +#define REG_TCC2_CCB1 (*(RwReg *)0x42002874U) /**< \brief (TCC2) Compare and Capture Buffer 1 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC2 peripheral ========== */ +#define TCC2_CC_NUM 2 // Number of Compare/Capture units +#define TCC2_DITHERING 0 // Dithering feature implemented +#define TCC2_DMAC_ID_MC_0 22 +#define TCC2_DMAC_ID_MC_1 23 +#define TCC2_DMAC_ID_MC_LSB 22 +#define TCC2_DMAC_ID_MC_MSB 23 +#define TCC2_DMAC_ID_MC_SIZE 2 +#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger +#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented +#define TCC2_EXT 0 // Coding of implemented extended features +#define TCC2_GCLK_ID 27 // Index of Generic Clock +#define TCC2_MASTER 0 +#define TCC2_OTMX 0 // Output Matrix feature implemented +#define TCC2_OW_NUM 2 // Number of Output Waveforms +#define TCC2_PG 0 // Pattern Generation feature implemented +#define TCC2_SIZE 16 +#define TCC2_SWAP 0 // DTI outputs swap feature implemented +#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave +/* TCC Inst 3 */ +/* ========== Register definition for TCC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_TCC3_CTRLA (0x42006000) /**< \brief (TCC3) Control A */ +#define REG_TCC3_CTRLBCLR (0x42006004) /**< \brief (TCC3) Control B Clear */ +#define REG_TCC3_CTRLBSET (0x42006005) /**< \brief (TCC3) Control B Set */ +#define REG_TCC3_SYNCBUSY (0x42006008) /**< \brief (TCC3) Synchronization Busy */ +#define REG_TCC3_FCTRLA (0x4200600C) /**< \brief (TCC3) Recoverable Fault A Configuration */ +#define REG_TCC3_FCTRLB (0x42006010) /**< \brief (TCC3) Recoverable Fault B Configuration */ +#define REG_TCC3_WEXCTRL (0x42006014) /**< \brief (TCC3) Waveform Extension Configuration */ +#define REG_TCC3_DRVCTRL (0x42006018) /**< \brief (TCC3) Driver Control */ +#define REG_TCC3_DBGCTRL (0x4200601E) /**< \brief (TCC3) Debug Control */ +#define REG_TCC3_EVCTRL (0x42006020) /**< \brief (TCC3) Event Control */ +#define REG_TCC3_INTENCLR (0x42006024) /**< \brief (TCC3) Interrupt Enable Clear */ +#define REG_TCC3_INTENSET (0x42006028) /**< \brief (TCC3) Interrupt Enable Set */ +#define REG_TCC3_INTFLAG (0x4200602C) /**< \brief (TCC3) Interrupt Flag Status and Clear */ +#define REG_TCC3_STATUS (0x42006030) /**< \brief (TCC3) Status */ +#define REG_TCC3_COUNT (0x42006034) /**< \brief (TCC3) Count */ +#define REG_TCC3_PATT (0x42006038) /**< \brief (TCC3) Pattern */ +#define REG_TCC3_WAVE (0x4200603C) /**< \brief (TCC3) Waveform Control */ +#define REG_TCC3_PER (0x42006040) /**< \brief (TCC3) Period */ +#define REG_TCC3_CC0 (0x42006044) /**< \brief (TCC3) Compare and Capture 0 */ +#define REG_TCC3_CC1 (0x42006048) /**< \brief (TCC3) Compare and Capture 1 */ +#define REG_TCC3_CC2 (0x4200604C) /**< \brief (TCC3) Compare and Capture 2 */ +#define REG_TCC3_CC3 (0x42006050) /**< \brief (TCC3) Compare and Capture 3 */ +#define REG_TCC3_PATTB (0x42006064) /**< \brief (TCC3) Pattern Buffer */ +#define REG_TCC3_WAVEB (0x42006068) /**< \brief (TCC3) Waveform Control Buffer */ +#define REG_TCC3_PERB (0x4200606C) /**< \brief (TCC3) Period Buffer */ +#define REG_TCC3_CCB0 (0x42006070) /**< \brief (TCC3) Compare and Capture Buffer 0 */ +#define REG_TCC3_CCB1 (0x42006074) /**< \brief (TCC3) Compare and Capture Buffer 1 */ +#define REG_TCC3_CCB2 (0x42006078) /**< \brief (TCC3) Compare and Capture Buffer 2 */ +#define REG_TCC3_CCB3 (0x4200607C) /**< \brief (TCC3) Compare and Capture Buffer 3 */ +#else +#define REG_TCC3_CTRLA (*(RwReg *)0x42006000UL) /**< \brief (TCC3) Control A */ +#define REG_TCC3_CTRLBCLR (*(RwReg8 *)0x42006004UL) /**< \brief (TCC3) Control B Clear */ +#define REG_TCC3_CTRLBSET (*(RwReg8 *)0x42006005UL) /**< \brief (TCC3) Control B Set */ +#define REG_TCC3_SYNCBUSY (*(RoReg *)0x42006008UL) /**< \brief (TCC3) Synchronization Busy */ +#define REG_TCC3_FCTRLA (*(RwReg *)0x4200600CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */ +#define REG_TCC3_FCTRLB (*(RwReg *)0x42006010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */ +#define REG_TCC3_WEXCTRL (*(RwReg *)0x42006014UL) /**< \brief (TCC3) Waveform Extension Configuration */ +#define REG_TCC3_DRVCTRL (*(RwReg *)0x42006018UL) /**< \brief (TCC3) Driver Control */ +#define REG_TCC3_DBGCTRL (*(RwReg8 *)0x4200601EUL) /**< \brief (TCC3) Debug Control */ +#define REG_TCC3_EVCTRL (*(RwReg *)0x42006020UL) /**< \brief (TCC3) Event Control */ +#define REG_TCC3_INTENCLR (*(RwReg *)0x42006024UL) /**< \brief (TCC3) Interrupt Enable Clear */ +#define REG_TCC3_INTENSET (*(RwReg *)0x42006028UL) /**< \brief (TCC3) Interrupt Enable Set */ +#define REG_TCC3_INTFLAG (*(RwReg *)0x4200602CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */ +#define REG_TCC3_STATUS (*(RwReg *)0x42006030UL) /**< \brief (TCC3) Status */ +#define REG_TCC3_COUNT (*(RwReg *)0x42006034UL) /**< \brief (TCC3) Count */ +#define REG_TCC3_PATT (*(RwReg16*)0x42006038UL) /**< \brief (TCC3) Pattern */ +#define REG_TCC3_WAVE (*(RwReg *)0x4200603CUL) /**< \brief (TCC3) Waveform Control */ +#define REG_TCC3_PER (*(RwReg *)0x42006040UL) /**< \brief (TCC3) Period */ +#define REG_TCC3_CC0 (*(RwReg *)0x42006044UL) /**< \brief (TCC3) Compare and Capture 0 */ +#define REG_TCC3_CC1 (*(RwReg *)0x42006048UL) /**< \brief (TCC3) Compare and Capture 1 */ +#define REG_TCC3_CC2 (*(RwReg *)0x4200604CUL) /**< \brief (TCC3) Compare and Capture 2 */ +#define REG_TCC3_CC3 (*(RwReg *)0x42006050UL) /**< \brief (TCC3) Compare and Capture 3 */ +#define REG_TCC3_PATTB (*(RwReg16*)0x42006064UL) /**< \brief (TCC3) Pattern Buffer */ +#define REG_TCC3_WAVEB (*(RwReg *)0x42006068UL) /**< \brief (TCC3) Waveform Control Buffer */ +#define REG_TCC3_PERB (*(RwReg *)0x4200606CUL) /**< \brief (TCC3) Period Buffer */ +#define REG_TCC3_CCB0 (*(RwReg *)0x42006070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */ +#define REG_TCC3_CCB1 (*(RwReg *)0x42006074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */ +#define REG_TCC3_CCB2 (*(RwReg *)0x42006078UL) /**< \brief (TCC3) Compare and Capture Buffer 2 */ +#define REG_TCC3_CCB3 (*(RwReg *)0x4200607CUL) /**< \brief (TCC3) Compare and Capture Buffer 3 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for TCC3 peripheral ========== */ +#define TCC3_CC_NUM 4 // Number of Compare/Capture units +#define TCC3_DITHERING 1 // Dithering feature implemented +#define TCC3_DMAC_ID_MC_0 46 +#define TCC3_DMAC_ID_MC_1 47 +#define TCC3_DMAC_ID_MC_2 48 +#define TCC3_DMAC_ID_MC_3 49 +#define TCC3_DMAC_ID_MC_LSB 46 +#define TCC3_DMAC_ID_MC_MSB 49 +#define TCC3_DMAC_ID_MC_SIZE 4 +#define TCC3_DMAC_ID_OVF 45 // DMA overflow/underflow/retrigger trigger +#define TCC3_DTI 1 // Dead-Time-Insertion feature implemented +#define TCC3_EXT 31 // Coding of implemented extended features +#define TCC3_GCLK_ID 37 // Index of Generic Clock +#define TCC3_MASTER 0 +#define TCC3_OTMX 1 // Output Matrix feature implemented +#define TCC3_OW_NUM 8 // Number of Output Waveforms +#define TCC3_PG 1 // Pattern Generation feature implemented +#define TCC3_SIZE 24 +#define TCC3_SWAP 1 // DTI outputs swap feature implemented +#define TCC3_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_tcc_lighting.h b/arch/arm/SAM_D2X/hdi/inc/hdi_tcc_lighting.h new file mode 100644 index 00000000..b03bf927 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_tcc_lighting.h @@ -0,0 +1,1788 @@ +#ifndef _HDI_TCC_LIGHTING_H_ +#define _HDI_TCC_LIGHTING_H_ + +#define TCC_U2213 +#define REV_TCC 0x122 + +/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t :9; /*!< bit: 15..23 Reserved */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ +#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ + +#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ +#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) +#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ +#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) +#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ +#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)) +#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ +#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ +#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ +#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)) +#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ +#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ +#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ +#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ +#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ +#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ +#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ +#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ +#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ +#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) +#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ +#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)) +#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ +#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ +#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ +#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ +#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) +#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ +#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) +#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ +#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) +#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ +#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) +#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ +#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) +#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ +#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) +#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)) +#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */ + +/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ +#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ + +#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ +#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) +#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ +#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) +#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ +#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) +#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ +#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)) +#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ +#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)) +#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ +#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ +#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ +#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */ +#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ +#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ + +/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ +#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ + +#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ +#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) +#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ +#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) +#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ +#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) +#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ +#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)) +#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ +#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)) +#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ +#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ +#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ +#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */ +#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ +#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ + +/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ + uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ + uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ + uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ + uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ + uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ + uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :7; /*!< bit: 12..18 Reserved */ + uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ +#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ + +#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ +#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) +#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ +#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) +#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ +#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) +#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ +#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) +#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ +#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) +#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ +#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) +#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ +#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) +#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */ +#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) +#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ +#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) +#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ +#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) +#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ +#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) +#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ +#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) +#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ +#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) +#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)) +#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */ +#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos) +#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */ +#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos) +#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */ +#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos) +#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */ +#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos) +#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */ +#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos) +#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */ +#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos) +#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */ +#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos) +#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */ +#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos) +#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)) +#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ + +/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ +#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ + +#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ +#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)) +#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ +#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ +#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) +#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ +#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) +#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ +#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)) +#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */ +#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ +#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) +#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ +#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)) +#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ +#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ +#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ +#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ +#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ +#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)) +#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ +#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ +#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ +#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ +#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ +#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)) +#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ +#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ +#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ +#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ +#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ +#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ +#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ +#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */ +#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ +#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) +#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)) +#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ +#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) +#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)) +#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */ + +/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ +#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ + +#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ +#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)) +#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ +#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ +#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) +#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ +#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) +#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ +#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)) +#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */ +#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ +#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) +#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ +#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)) +#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ +#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ +#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ +#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ +#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ +#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)) +#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ +#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ +#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ +#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ +#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ +#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)) +#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ +#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ +#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ +#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ +#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ +#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ +#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ +#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */ +#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ +#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) +#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)) +#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ +#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) +#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)) +#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */ + +/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WEXCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ +#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ + +#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ +#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) +#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)) +#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ +#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) +#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ +#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) +#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ +#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) +#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ +#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) +#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ +#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) +#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)) +#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ +#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) +#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)) +#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ +#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) +#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)) +#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ + +/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_DRVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ +#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ + +#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ +#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) +#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ +#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) +#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ +#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) +#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ +#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) +#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ +#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) +#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ +#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) +#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ +#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) +#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ +#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) +#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ +#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) +#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)) +#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ +#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) +#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ +#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) +#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ +#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) +#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ +#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) +#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ +#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) +#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ +#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) +#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ +#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) +#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ +#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) +#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ +#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) +#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)) +#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ +#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) +#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ +#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) +#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ +#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) +#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ +#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) +#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ +#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) +#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ +#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) +#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ +#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) +#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ +#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) +#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ +#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) +#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)) +#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) +#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)) +#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) +#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)) +#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ + +/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ +#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ + +#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ +#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) +#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ +#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) +#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ + +/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ +#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ + +#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ +#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)) +#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ +#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ +#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ +#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ +#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ +#define TCC_EVCTRL_EVACT0_STAMP_Val 0x6ul /**< \brief (TCC_EVCTRL) Stamp capture */ +#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ +#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)) +#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ +#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ +#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ +#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ +#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ +#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ +#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ +#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)) +#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ +#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ +#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ +#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) +#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ +#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) +#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ +#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) +#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ +#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) +#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ +#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) +#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ +#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) +#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)) +#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ +#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) +#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ +#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) +#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ +#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) +#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)) +#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ +#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) +#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ +#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) +#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ +#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) +#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ +#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) +#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ +#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) +#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)) +#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ +#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) +#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ +#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) +#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ +#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) +#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ +#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) +#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ +#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) +#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)) +#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ + +/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ +#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ +#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) +#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ +#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) +#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ +#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) +#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ +#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) +#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */ +#define TCC_INTENCLR_UFS (0x1ul << TCC_INTENCLR_UFS_Pos) +#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) +#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) +#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) +#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) +#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) +#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) +#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) +#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) +#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) +#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) +#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)) +#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */ + +/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :6; /*!< bit: 4.. 9 Reserved */ + uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ +#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ + +#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ +#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) +#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ +#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) +#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ +#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) +#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ +#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) +#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */ +#define TCC_INTENSET_UFS (0x1ul << TCC_INTENSET_UFS_Pos) +#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) +#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) +#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) +#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) +#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) +#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) +#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) +#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) +#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) +#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) +#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)) +#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */ + +/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint32_t OVF:1; /*!< bit: 0 Overflow */ + __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ + __I uint32_t CNT:1; /*!< bit: 2 Counter */ + __I uint32_t ERR:1; /*!< bit: 3 Error */ + __I uint32_t :6; /*!< bit: 4.. 9 Reserved */ + __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ + __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint32_t :16; /*!< bit: 0..15 Reserved */ + __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ +#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) +#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ +#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) +#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ +#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) +#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ +#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) +#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */ +#define TCC_INTFLAG_UFS (0x1ul << TCC_INTFLAG_UFS_Pos) +#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ +#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) +#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ +#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) +#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ +#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) +#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ +#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) +#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ +#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) +#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ +#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) +#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ +#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) +#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ +#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) +#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ +#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) +#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ +#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) +#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)) +#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */ + +/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ +#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ + +#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ +#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) +#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ +#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) +#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */ +#define TCC_STATUS_UFS (0x1ul << TCC_STATUS_UFS_Pos) +#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ +#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) +#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ +#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) +#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ +#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos) +#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ +#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos) +#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ +#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos) +#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ +#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) +#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ +#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) +#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ +#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) +#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ +#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) +#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ +#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) +#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ +#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) +#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ +#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) +#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ +#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) +#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ +#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos) +#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ +#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos) +#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ +#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos) +#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ +#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos) +#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ +#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos) +#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)) +#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ +#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) +#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ +#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) +#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ +#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) +#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ +#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) +#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ +#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) +#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)) +#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */ + +/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ +#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ + +// DITH4 mode +#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ +#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) +#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)) +#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ +#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) +#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)) +#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ +#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) +#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)) +#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ + +#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ +#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) +#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)) +#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ + +/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ +#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ + +#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ +#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) +#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ +#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) +#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ +#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) +#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ +#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) +#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ +#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) +#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ +#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) +#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ +#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) +#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ +#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) +#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ +#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) +#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)) +#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ +#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) +#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ +#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) +#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ +#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) +#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ +#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) +#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ +#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) +#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ +#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) +#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ +#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) +#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ +#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) +#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ +#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) +#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)) +#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ + +/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ +#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ + +#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ +#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)) +#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ +#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ +#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ +#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ +#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ +#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)) +#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ +#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVE) Critical RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ +#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) +#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ +#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) +#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ +#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) +#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ +#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) +#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ +#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) +#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ +#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) +#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)) +#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ +#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) +#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ +#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) +#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ +#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) +#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ +#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) +#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ +#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) +#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)) +#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ +#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) +#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ +#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) +#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ +#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) +#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ +#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) +#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ +#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) +#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)) +#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ + +/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ +#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ + +// DITH4 mode +#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ +#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos) +#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)) +#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ +#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) +#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)) +#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ +#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos) +#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)) +#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ +#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) +#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)) +#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ +#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos) +#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)) +#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ +#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) +#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)) +#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ + +#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ +#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) +#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)) +#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ + +/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ +#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ + +// DITH4 mode +#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ +#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos) +#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)) +#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ +#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) +#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)) +#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ +#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos) +#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)) +#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ +#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) +#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)) +#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ +#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos) +#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)) +#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ +#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) +#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)) +#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ + +#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ +#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) +#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)) +#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ + +/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATTB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */ +#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */ + +#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */ +#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos) +#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */ +#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos) +#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */ +#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos) +#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */ +#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos) +#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */ +#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos) +#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */ +#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos) +#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */ +#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos) +#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */ +#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos) +#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */ +#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos) +#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)) +#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */ +#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos) +#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */ +#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos) +#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */ +#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos) +#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */ +#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos) +#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */ +#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos) +#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */ +#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos) +#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */ +#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos) +#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */ +#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos) +#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */ +#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos) +#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)) +#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */ + +/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVEB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */ +#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */ + +#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */ +#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)) +#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */ +#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */ +#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */ +#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */ +#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */ +#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)) +#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */ +#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */ +#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */ +#define TCC_WAVEB_RAMPB_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVEB) Critical RAMP2 operation */ +#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2C (TCC_WAVEB_RAMPB_RAMP2C_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */ +#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos) +#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */ +#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos) +#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */ +#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos) +#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */ +#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos) +#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */ +#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos) +#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */ +#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos) +#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)) +#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */ +#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos) +#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */ +#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos) +#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */ +#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos) +#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */ +#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos) +#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */ +#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos) +#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)) +#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */ +#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos) +#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */ +#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos) +#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */ +#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos) +#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */ +#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos) +#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */ +#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos) +#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)) +#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */ + +/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PERB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */ +#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */ + +// DITH4 mode +#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos) +#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)) +#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */ +#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos) +#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)) +#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos) +#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)) +#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */ +#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos) +#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)) +#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos) +#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)) +#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */ +#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos) +#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)) +#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */ + +#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */ +#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos) +#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)) +#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */ + +/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CCB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */ +#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */ + +// DITH4 mode +#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos) +#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)) +#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos) +#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)) +#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos) +#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)) +#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos) +#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)) +#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos) +#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)) +#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos) +#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)) +#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */ + +#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos) +#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)) +#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */ + +/** \brief TCC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ +} Tcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_tcc_variant_d.h b/arch/arm/SAM_D2X/hdi/inc/hdi_tcc_variant_d.h new file mode 100644 index 00000000..8ef02611 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_tcc_variant_d.h @@ -0,0 +1,1775 @@ +#ifndef _HDI_TCC_VARIANT_D_H_ +#define _HDI_TCC_VARIANT_D_H_ + +#define TCC_U2213 +#define REV_TCC 0x122 + +/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t :3; /*!< bit: 2.. 4 Reserved */ + uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ + uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ + uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ + uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ + uint32_t :9; /*!< bit: 15..23 Reserved */ + uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ + uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ + uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ + uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :24; /*!< bit: 0..23 Reserved */ + uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ +#define TCC_CTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_CTRLA reset_value) Control A */ + +#define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ +#define TCC_CTRLA_SWRST (0x1ul << TCC_CTRLA_SWRST_Pos) +#define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ +#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos) +#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ +#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)) +#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */ +#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ +#define TCC_CTRLA_RESOLUTION_DITH6_Val 0x3ul /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ +#define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) +#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ +#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)) +#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */ +#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */ +#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */ +#define TCC_CTRLA_PRESCALER_DIV8_Val 0x3ul /**< \brief (TCC_CTRLA) Divide by 8 */ +#define TCC_CTRLA_PRESCALER_DIV16_Val 0x4ul /**< \brief (TCC_CTRLA) Divide by 16 */ +#define TCC_CTRLA_PRESCALER_DIV64_Val 0x5ul /**< \brief (TCC_CTRLA) Divide by 64 */ +#define TCC_CTRLA_PRESCALER_DIV256_Val 0x6ul /**< \brief (TCC_CTRLA) Divide by 256 */ +#define TCC_CTRLA_PRESCALER_DIV1024_Val 0x7ul /**< \brief (TCC_CTRLA) Divide by 1024 */ +#define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) +#define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ +#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos) +#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ +#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)) +#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ +#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ +#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ +#define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) +#define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ +#define TCC_CTRLA_ALOCK (0x1ul << TCC_CTRLA_ALOCK_Pos) +#define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ +#define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) +#define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ +#define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) +#define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ +#define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) +#define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ +#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) +#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ +#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos) +#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)) +#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */ + +/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ +#define TCC_CTRLBCLR_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ + +#define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ +#define TCC_CTRLBCLR_DIR (0x1ul << TCC_CTRLBCLR_DIR_Pos) +#define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ +#define TCC_CTRLBCLR_LUPD (0x1ul << TCC_CTRLBCLR_LUPD_Pos) +#define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ +#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos) +#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ +#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)) +#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBCLR_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) +#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ +#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)) +#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */ +#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ +#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */ +#define TCC_CTRLBCLR_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */ +#define TCC_CTRLBCLR_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ +#define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) +#define TCC_CTRLBCLR_MASK 0xFFul /**< \brief (TCC_CTRLBCLR) MASK Register */ + +/* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIR:1; /*!< bit: 0 Counter Direction */ + uint8_t LUPD:1; /*!< bit: 1 Lock Update */ + uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ + uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ + uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_CTRLBSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ +#define TCC_CTRLBSET_RESETVALUE 0x00ul /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ + +#define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ +#define TCC_CTRLBSET_DIR (0x1ul << TCC_CTRLBSET_DIR_Pos) +#define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ +#define TCC_CTRLBSET_LUPD (0x1ul << TCC_CTRLBSET_LUPD_Pos) +#define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ +#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos) +#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ +#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)) +#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ +#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ +#define TCC_CTRLBSET_IDXCMD_HOLD_Val 0x3ul /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ +#define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) +#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ +#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)) +#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */ +#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ +#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */ +#define TCC_CTRLBSET_CMD_UPDATE_Val 0x3ul /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */ +#define TCC_CTRLBSET_CMD_READSYNC_Val 0x4ul /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ +#define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) +#define TCC_CTRLBSET_MASK 0xFFul /**< \brief (TCC_CTRLBSET) MASK Register */ + +/* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ + uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ + uint32_t STATUS:1; /*!< bit: 3 Status Busy */ + uint32_t COUNT:1; /*!< bit: 4 Count Busy */ + uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ + uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ + uint32_t PER:1; /*!< bit: 7 Period busy */ + uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ + uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ + uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ + uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ + uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ + uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ + uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ + uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ + uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ + uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ + uint32_t :7; /*!< bit: 12..18 Reserved */ + uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ +#define TCC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ + +#define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ +#define TCC_SYNCBUSY_SWRST (0x1ul << TCC_SYNCBUSY_SWRST_Pos) +#define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ +#define TCC_SYNCBUSY_ENABLE (0x1ul << TCC_SYNCBUSY_ENABLE_Pos) +#define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ +#define TCC_SYNCBUSY_CTRLB (0x1ul << TCC_SYNCBUSY_CTRLB_Pos) +#define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ +#define TCC_SYNCBUSY_STATUS (0x1ul << TCC_SYNCBUSY_STATUS_Pos) +#define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ +#define TCC_SYNCBUSY_COUNT (0x1ul << TCC_SYNCBUSY_COUNT_Pos) +#define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ +#define TCC_SYNCBUSY_PATT (0x1ul << TCC_SYNCBUSY_PATT_Pos) +#define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ +#define TCC_SYNCBUSY_WAVE (0x1ul << TCC_SYNCBUSY_WAVE_Pos) +#define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */ +#define TCC_SYNCBUSY_PER (0x1ul << TCC_SYNCBUSY_PER_Pos) +#define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ +#define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) +#define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ +#define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) +#define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ +#define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) +#define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ +#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) +#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ +#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos) +#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)) +#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */ +#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos) +#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */ +#define TCC_SYNCBUSY_WAVEB (0x1ul << TCC_SYNCBUSY_WAVEB_Pos) +#define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */ +#define TCC_SYNCBUSY_PERB (0x1ul << TCC_SYNCBUSY_PERB_Pos) +#define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */ +#define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos) +#define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */ +#define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos) +#define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */ +#define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos) +#define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */ +#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos) +#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */ +#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos) +#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)) +#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */ + +/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ +#define TCC_FCTRLA_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ + +#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ +#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)) +#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */ +#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLA_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) +#define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ +#define TCC_FCTRLA_KEEP (0x1ul << TCC_FCTRLA_KEEP_Pos) +#define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ +#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos) +#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ +#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)) +#define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */ +#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) +#define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ +#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos) +#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ +#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)) +#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */ +#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */ +#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */ +#define TCC_FCTRLA_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLA) Non-recoverable fault */ +#define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) +#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ +#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)) +#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ +#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ +#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ +#define TCC_FCTRLA_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ +#define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) +#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ +#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)) +#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */ +#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */ +#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */ +#define TCC_FCTRLA_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLA) Maximum capture */ +#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */ +#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */ +#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ + +#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) +#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ +#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos) +#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)) +#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ +#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos) +#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)) +#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */ + +/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ + uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ + uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ + uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ + uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ + uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ + uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ + uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_FCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ +#define TCC_FCTRLB_RESETVALUE 0x00000000ul /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ + +#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ +#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)) +#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */ +#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ +#define TCC_FCTRLB_SRC_ALTFAULT_Val 0x3ul /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ +#define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) +#define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ +#define TCC_FCTRLB_KEEP (0x1ul << TCC_FCTRLB_KEEP_Pos) +#define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ +#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos) +#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ +#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)) +#define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */ +#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ +#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ +#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ +#define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) +#define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ +#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos) +#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ +#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)) +#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */ +#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */ +#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */ +#define TCC_FCTRLB_HALT_NR_Val 0x3ul /**< \brief (TCC_FCTRLB) Non-recoverable fault */ +#define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) +#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ +#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)) +#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ +#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ +#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ +#define TCC_FCTRLB_CHSEL_CC3_Val 0x3ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ +#define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) +#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ +#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)) +#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */ +#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */ +#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */ +#define TCC_FCTRLB_CAPTURE_CAPTMAX_Val 0x3ul /**< \brief (TCC_FCTRLB) Maximum capture */ +#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */ +#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */ +#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ + +#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) +#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) + +#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ +#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos) +#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)) +#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ +#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos) +#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)) +#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */ + +/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ + uint32_t :6; /*!< bit: 2.. 7 Reserved */ + uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ + uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ + uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ + uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ + uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WEXCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ +#define TCC_WEXCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ + +#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ +#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos) +#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)) +#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ +#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) +#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ +#define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) +#define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ +#define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) +#define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ +#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) +#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ +#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos) +#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)) +#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ +#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos) +#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)) +#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ +#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos) +#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)) +#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */ + +/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ + uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ + uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ + uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ + uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ + uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ + uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ + uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ + uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ + uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ + uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ + uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ + uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ + uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ + uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ + uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ + uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ + uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ + uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ + uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ + uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ + uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ + uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ + uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ + uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ + uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ + uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ + uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_DRVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ +#define TCC_DRVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ + +#define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ +#define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) +#define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ +#define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) +#define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ +#define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) +#define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ +#define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) +#define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ +#define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) +#define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ +#define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) +#define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ +#define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) +#define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ +#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) +#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ +#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos) +#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)) +#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ +#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) +#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ +#define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) +#define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ +#define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) +#define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ +#define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) +#define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ +#define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) +#define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ +#define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) +#define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ +#define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) +#define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ +#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) +#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ +#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos) +#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)) +#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ +#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) +#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ +#define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) +#define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ +#define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) +#define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ +#define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) +#define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ +#define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) +#define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ +#define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) +#define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ +#define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) +#define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ +#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) +#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ +#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos) +#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)) +#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos) +#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)) +#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ +#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos) +#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)) +#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */ + +/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} TCC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ +#define TCC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ + +#define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ +#define TCC_DBGCTRL_DBGRUN (0x1ul << TCC_DBGCTRL_DBGRUN_Pos) +#define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ +#define TCC_DBGCTRL_FDDBD (0x1ul << TCC_DBGCTRL_FDDBD_Pos) +#define TCC_DBGCTRL_MASK 0x05ul /**< \brief (TCC_DBGCTRL) MASK Register */ + +/* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ + uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ + uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ + uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ + uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ + uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ + uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ + uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ + uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ + uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ + uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ + uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ + uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ + uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ + uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ + uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :12; /*!< bit: 0..11 Reserved */ + uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ + uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ + uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ +#define TCC_EVCTRL_RESETVALUE 0x00000000ul /**< \brief (TCC_EVCTRL reset_value) Event Control */ + +#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ +#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)) +#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ +#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */ +#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */ +#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */ +#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ + +#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) + +#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) +#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ +#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)) +#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */ +#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ +#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */ +#define TCC_EVCTRL_EVACT1_STOP_Val 0x3ul /**< \brief (TCC_EVCTRL) Stop counter on event */ +#define TCC_EVCTRL_EVACT1_DEC_Val 0x4ul /**< \brief (TCC_EVCTRL) Decrement counter on event */ +#define TCC_EVCTRL_EVACT1_PPW_Val 0x5ul /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ +#define TCC_EVCTRL_EVACT1_PWP_Val 0x6ul /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ +#define TCC_EVCTRL_EVACT1_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */ +#define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) +#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ +#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)) +#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ +#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ +#define TCC_EVCTRL_CNTSEL_BOUNDARY_Val 0x3ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ +#define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) +#define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ +#define TCC_EVCTRL_OVFEO (0x1ul << TCC_EVCTRL_OVFEO_Pos) +#define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ +#define TCC_EVCTRL_TRGEO (0x1ul << TCC_EVCTRL_TRGEO_Pos) +#define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ +#define TCC_EVCTRL_CNTEO (0x1ul << TCC_EVCTRL_CNTEO_Pos) +#define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ +#define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) +#define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ +#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) +#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ +#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos) +#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)) +#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ +#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) +#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ +#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) +#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ +#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos) +#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)) +#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ +#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) +#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ +#define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) +#define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ +#define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) +#define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ +#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) +#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ +#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos) +#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)) +#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ +#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) +#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ +#define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) +#define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ +#define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) +#define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ +#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) +#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ +#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos) +#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)) +#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */ + +/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ +#define TCC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ +#define TCC_INTENCLR_OVF (0x1ul << TCC_INTENCLR_OVF_Pos) +#define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ +#define TCC_INTENCLR_TRG (0x1ul << TCC_INTENCLR_TRG_Pos) +#define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ +#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos) +#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ +#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos) +#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos) +#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENCLR_FAULTA (0x1ul << TCC_INTENCLR_FAULTA_Pos) +#define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENCLR_FAULTB (0x1ul << TCC_INTENCLR_FAULTB_Pos) +#define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENCLR_FAULT0 (0x1ul << TCC_INTENCLR_FAULT0_Pos) +#define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENCLR_FAULT1 (0x1ul << TCC_INTENCLR_FAULT1_Pos) +#define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) +#define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) +#define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) +#define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) +#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos) +#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)) +#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */ + +/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ + uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ + uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ + uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ + uint32_t :7; /*!< bit: 4..10 Reserved */ + uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ + uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ + uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ + uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ + uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ +#define TCC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ + +#define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ +#define TCC_INTENSET_OVF (0x1ul << TCC_INTENSET_OVF_Pos) +#define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ +#define TCC_INTENSET_TRG (0x1ul << TCC_INTENSET_TRG_Pos) +#define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ +#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos) +#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ +#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos) +#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ +#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos) +#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ +#define TCC_INTENSET_FAULTA (0x1ul << TCC_INTENSET_FAULTA_Pos) +#define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ +#define TCC_INTENSET_FAULTB (0x1ul << TCC_INTENSET_FAULTB_Pos) +#define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ +#define TCC_INTENSET_FAULT0 (0x1ul << TCC_INTENSET_FAULT0_Pos) +#define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ +#define TCC_INTENSET_FAULT1 (0x1ul << TCC_INTENSET_FAULT1_Pos) +#define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ +#define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) +#define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ +#define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) +#define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ +#define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) +#define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ +#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) +#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ +#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos) +#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)) +#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */ + +/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint32_t OVF:1; /*!< bit: 0 Overflow */ + __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ + __I uint32_t CNT:1; /*!< bit: 2 Counter */ + __I uint32_t ERR:1; /*!< bit: 3 Error */ + __I uint32_t :7; /*!< bit: 4..10 Reserved */ + __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ + __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ + __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ + __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ + __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ + __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ + __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ + __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ + __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint32_t :16; /*!< bit: 0..15 Reserved */ + __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ + __I uint32_t :12; /*!< bit: 20..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define TCC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ +#define TCC_INTFLAG_OVF (0x1ul << TCC_INTFLAG_OVF_Pos) +#define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ +#define TCC_INTFLAG_TRG (0x1ul << TCC_INTFLAG_TRG_Pos) +#define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ +#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos) +#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ +#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos) +#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ +#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos) +#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ +#define TCC_INTFLAG_FAULTA (0x1ul << TCC_INTFLAG_FAULTA_Pos) +#define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ +#define TCC_INTFLAG_FAULTB (0x1ul << TCC_INTFLAG_FAULTB_Pos) +#define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ +#define TCC_INTFLAG_FAULT0 (0x1ul << TCC_INTFLAG_FAULT0_Pos) +#define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ +#define TCC_INTFLAG_FAULT1 (0x1ul << TCC_INTFLAG_FAULT1_Pos) +#define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ +#define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) +#define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ +#define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) +#define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ +#define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) +#define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ +#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) +#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ +#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos) +#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)) +#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */ + +/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t STOP:1; /*!< bit: 0 Stop */ + uint32_t IDX:1; /*!< bit: 1 Ramp */ + uint32_t :1; /*!< bit: 2 Reserved */ + uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ + uint32_t SLAVE:1; /*!< bit: 4 Slave */ + uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ + uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ + uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ + uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ + uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ + uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ + uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ + uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ + uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ + uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ + uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ + uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ + uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ + uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ + uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ + uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ + uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ + uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ +#define TCC_STATUS_RESETVALUE 0x00000001ul /**< \brief (TCC_STATUS reset_value) Status */ + +#define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ +#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos) +#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ +#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos) +#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ +#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos) +#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ +#define TCC_STATUS_SLAVE (0x1ul << TCC_STATUS_SLAVE_Pos) +#define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ +#define TCC_STATUS_PATTBV (0x1ul << TCC_STATUS_PATTBV_Pos) +#define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ +#define TCC_STATUS_WAVEBV (0x1ul << TCC_STATUS_WAVEBV_Pos) +#define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ +#define TCC_STATUS_PERBV (0x1ul << TCC_STATUS_PERBV_Pos) +#define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ +#define TCC_STATUS_FAULTAIN (0x1ul << TCC_STATUS_FAULTAIN_Pos) +#define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ +#define TCC_STATUS_FAULTBIN (0x1ul << TCC_STATUS_FAULTBIN_Pos) +#define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ +#define TCC_STATUS_FAULT0IN (0x1ul << TCC_STATUS_FAULT0IN_Pos) +#define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ +#define TCC_STATUS_FAULT1IN (0x1ul << TCC_STATUS_FAULT1IN_Pos) +#define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ +#define TCC_STATUS_FAULTA (0x1ul << TCC_STATUS_FAULTA_Pos) +#define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ +#define TCC_STATUS_FAULTB (0x1ul << TCC_STATUS_FAULTB_Pos) +#define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ +#define TCC_STATUS_FAULT0 (0x1ul << TCC_STATUS_FAULT0_Pos) +#define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ +#define TCC_STATUS_FAULT1 (0x1ul << TCC_STATUS_FAULT1_Pos) +#define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ +#define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos) +#define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ +#define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos) +#define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ +#define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos) +#define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ +#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos) +#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ +#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos) +#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)) +#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ +#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) +#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ +#define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) +#define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ +#define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) +#define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ +#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) +#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ +#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos) +#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)) +#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */ + +/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t :5; /*!< bit: 0.. 4 Reserved */ + uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t :6; /*!< bit: 0.. 5 Reserved */ + uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_COUNT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ +#define TCC_COUNT_RESETVALUE 0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */ + +// DITH4 mode +#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ +#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos) +#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)) +#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ +#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos) +#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)) +#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ +#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos) +#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)) +#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */ + +#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ +#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos) +#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)) +#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */ + +/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ + uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ + uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ + uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ + uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ + uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ + uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ + uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ + uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ + uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ + uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ + uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ + uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ + uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ + uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ + uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ + uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ +#define TCC_PATT_RESETVALUE 0x0000ul /**< \brief (TCC_PATT reset_value) Pattern */ + +#define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ +#define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) +#define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ +#define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) +#define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ +#define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) +#define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ +#define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) +#define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ +#define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) +#define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ +#define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) +#define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ +#define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) +#define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ +#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) +#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ +#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos) +#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)) +#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ +#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) +#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ +#define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) +#define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ +#define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) +#define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ +#define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) +#define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ +#define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) +#define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ +#define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) +#define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ +#define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) +#define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ +#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) +#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ +#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos) +#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)) +#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */ + +/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ + uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ + uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ + uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ + uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ + uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ + uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ + uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ + uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ + uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ + uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ +#define TCC_WAVE_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVE reset_value) Waveform Control */ + +#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ +#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)) +#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */ +#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */ +#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */ +#define TCC_WAVE_WAVEGEN_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVE) Dual-slope critical */ +#define TCC_WAVE_WAVEGEN_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVE_WAVEGEN_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVE_WAVEGEN_DSTOP_Val 0x7ul /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) +#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ +#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)) +#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */ +#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ +#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */ + +#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) +#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ +#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos) +#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ +#define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) +#define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ +#define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) +#define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ +#define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) +#define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ +#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) +#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ +#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos) +#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)) +#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ +#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) +#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ +#define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) +#define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ +#define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) +#define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ +#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) +#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ +#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos) +#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)) +#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ +#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) +#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ +#define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) +#define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ +#define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) +#define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ +#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) +#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ +#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos) +#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)) +#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */ + +/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t PER:20; /*!< bit: 4..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t PER:19; /*!< bit: 5..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t PER:18; /*!< bit: 6..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PER:24; /*!< bit: 0..23 Period Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ +#define TCC_PER_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */ + +// DITH4 mode +#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ +#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos) +#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)) +#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ +#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos) +#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)) +#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ +#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos) +#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)) +#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ +#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos) +#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)) +#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ +#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos) +#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)) +#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ +#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos) +#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)) +#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */ + +#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ +#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos) +#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)) +#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */ + +/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ + uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ + uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ + uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ +#define TCC_CC_RESETVALUE 0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */ + +// DITH4 mode +#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ +#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos) +#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)) +#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ +#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos) +#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)) +#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ +#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos) +#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)) +#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ +#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos) +#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)) +#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ +#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos) +#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)) +#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ +#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos) +#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)) +#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */ + +#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ +#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos) +#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)) +#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */ + +/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ + uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ + uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ + uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ + uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ + uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ + uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ + uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ + uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ + uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ + uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ + uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ + uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ + uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ + uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ + uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ + uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} TCC_PATTB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */ +#define TCC_PATTB_RESETVALUE 0x0000ul /**< \brief (TCC_PATTB reset_value) Pattern Buffer */ + +#define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */ +#define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos) +#define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */ +#define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos) +#define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */ +#define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos) +#define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */ +#define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos) +#define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */ +#define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos) +#define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */ +#define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos) +#define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */ +#define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos) +#define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */ +#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos) +#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */ +#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos) +#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)) +#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */ +#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos) +#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */ +#define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos) +#define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */ +#define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos) +#define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */ +#define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos) +#define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */ +#define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos) +#define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */ +#define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos) +#define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */ +#define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos) +#define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */ +#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos) +#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */ +#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos) +#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)) +#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */ + +/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ + uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ + uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ + uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ + uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ + uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ + uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ + uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ + uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ + uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ + uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :8; /*!< bit: 0.. 7 Reserved */ + uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ + uint32_t :4; /*!< bit: 12..15 Reserved */ + uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_WAVEB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */ +#define TCC_WAVEB_RESETVALUE 0x00000000ul /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */ + +#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */ +#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)) +#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */ +#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */ +#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */ +#define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val 0x4ul /**< \brief (TCC_WAVEB) Dual-slope critical */ +#define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val 0x5ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ +#define TCC_WAVEB_WAVEGENB_DSBOTH_Val 0x6ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ +#define TCC_WAVEB_WAVEGENB_DSTOP_Val 0x7ul /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */ +#define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos) +#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */ +#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)) +#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */ +#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */ +#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */ + +#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos) +#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos) + +#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */ +#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos) +#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */ +#define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos) +#define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */ +#define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos) +#define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */ +#define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos) +#define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */ +#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos) +#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */ +#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos) +#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)) +#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */ +#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos) +#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */ +#define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos) +#define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */ +#define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos) +#define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */ +#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos) +#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */ +#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos) +#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)) +#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */ +#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos) +#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */ +#define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos) +#define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */ +#define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos) +#define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */ +#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos) +#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */ +#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos) +#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)) +#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */ + +/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_PERB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */ +#define TCC_PERB_RESETVALUE 0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */ + +// DITH4 mode +#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos) +#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)) +#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */ +#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos) +#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)) +#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos) +#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)) +#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */ +#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos) +#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)) +#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */ +#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos) +#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)) +#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */ +#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos) +#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)) +#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */ + +#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */ +#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos) +#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)) +#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */ + +/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { // DITH4 mode + uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ + uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH4; /*!< Structure used for DITH4 */ + struct { // DITH5 mode + uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ + uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH5; /*!< Structure used for DITH5 */ + struct { // DITH6 mode + uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ + uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } DITH6; /*!< Structure used for DITH6 */ + struct { + uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} TCC_CCB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */ +#define TCC_CCB_RESETVALUE 0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */ + +// DITH4 mode +#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos) +#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)) +#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos) +#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)) +#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */ + +// DITH5 mode +#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos) +#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)) +#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos) +#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)) +#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */ + +// DITH6 mode +#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */ +#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos) +#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)) +#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos) +#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)) +#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */ + +#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */ +#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos) +#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)) +#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */ + +/** \brief TCC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ + __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ + RoReg8 Reserved1[0x2]; + __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ + __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ + __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ + __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ + RoReg8 Reserved2[0x2]; + __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ + RoReg8 Reserved3[0x1]; + __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ + __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ + __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ + __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ + __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ + __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ + __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ + RoReg8 Reserved4[0x2]; + __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ + __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ + __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ + RoReg8 Reserved5[0x10]; + __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ + RoReg8 Reserved6[0x2]; + __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ + __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ + __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ +} Tcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_usb.h b/arch/arm/SAM_D2X/hdi/inc/hdi_usb.h new file mode 100644 index 00000000..777b2053 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_usb.h @@ -0,0 +1,2052 @@ +#ifndef _HDI_USB_H_ +#define _HDI_USB_H_ + +#define USB_U2222 +#define REV_USB 0x103 + +/* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t MODE:1; /*!< bit: 7 Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ +#define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */ + +#define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ +#define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos) +#define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ +#define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos) +#define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ +#define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos) +#define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ +#define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos) +#define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */ +#define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */ +#define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) +#define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) +#define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */ + +/* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ +#define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ + +#define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ +#define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos) +#define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ +#define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos) +#define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */ + +/* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ + uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_QOSCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */ +#define USB_QOSCTRL_RESETVALUE 0x05ul /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */ + +#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */ +#define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos) +#define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)) +#define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ +#define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ +#define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ +#define USB_QOSCTRL_CQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ +#define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos) +#define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos) +#define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos) +#define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos) +#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */ +#define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos) +#define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)) +#define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ +#define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ +#define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ +#define USB_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ +#define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos) +#define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos) +#define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos) +#define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos) +#define USB_QOSCTRL_MASK 0x0Ful /**< \brief (USB_QOSCTRL) MASK Register */ + +/* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DETACH:1; /*!< bit: 0 Detach */ + uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ + uint16_t NREPLY:1; /*!< bit: 4 No Reply */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ + uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ + uint16_t GNAK:1; /*!< bit: 9 Global NAK */ + uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ +#define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ + +#define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ +#define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos) +#define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ +#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ +#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)) +#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ +#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ +#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ +#define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ +#define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) +#define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ +#define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos) +#define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ +#define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos) +#define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ +#define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos) +#define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ +#define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos) +#define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ +#define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos) +#define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ +#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ +#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)) +#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ +#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */ +#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */ +#define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */ +#define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) +#define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */ + +/* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :1; /*!< bit: 0 Reserved */ + uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ + uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ + uint16_t TSTK:1; /*!< bit: 6 Test mode K */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ + uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ + uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ + uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ +#define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ + +#define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ +#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos) +#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ +#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos) +#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)) +#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ +#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ +#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) +#define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) +#define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ +#define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos) +#define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ +#define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos) +#define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ +#define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos) +#define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ +#define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos) +#define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ +#define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos) +#define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ +#define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos) +#define USB_HOST_CTRLB_MASK 0x0F6Eul /**< \brief (USB_HOST_CTRLB) MASK Register */ + +/* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ + uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_DADD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ +#define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ + +#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ +#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos) +#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)) +#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ +#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos) +#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */ + +/* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_HSOFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ +#define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ + +#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ +#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos) +#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)) +#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ +#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos) +#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */ + +/* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ +#define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ + +#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ +#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)) +#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ +#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */ +#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ +#define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) +#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ +#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)) +#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ +#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ +#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ +#define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) +#define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */ + +/* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :2; /*!< bit: 0.. 1 Reserved */ + uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ + uint8_t :2; /*!< bit: 4.. 5 Reserved */ + uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ +#define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ + +#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ +#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos) +#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)) +#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ +#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos) +#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)) +#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */ + +/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_FSMSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ +#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ + +#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ +#define USB_FSMSTATUS_FSMSTATE_Msk (0x7Ful << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)) +#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ +#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ +#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ +#define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ +#define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ +#define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ +#define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ +#define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) +#define USB_FSMSTATUS_MASK 0x7Ful /**< \brief (USB_FSMSTATUS) MASK Register */ + +/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :1; /*!< bit: 14 Reserved */ + uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_FNUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ +#define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ + +#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ +#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos) +#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)) +#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ +#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos) +#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)) +#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ +#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos) +#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */ + +/* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ + uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_FNUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ +#define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ + +#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ +#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos) +#define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)) +#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ +#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos) +#define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)) +#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */ + +/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_FLENHIGH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ +#define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ + +#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ +#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos) +#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)) +#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */ + +/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ +#define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ + +#define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ +#define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos) +#define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ +#define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos) +#define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ +#define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos) +#define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ +#define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos) +#define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ +#define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos) +#define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ +#define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos) +#define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ +#define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos) +#define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ +#define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos) +#define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ +#define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos) +#define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ +#define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos) +#define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ + +/* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ + uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ + uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ +#define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ + +#define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ +#define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos) +#define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ +#define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos) +#define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ +#define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos) +#define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ +#define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos) +#define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ +#define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos) +#define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ +#define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos) +#define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ +#define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos) +#define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ +#define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos) +#define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */ + +/* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ + uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ + uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ + uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ + uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ +#define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ + +#define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ +#define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos) +#define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ +#define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos) +#define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ +#define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos) +#define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ +#define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos) +#define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ +#define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos) +#define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ +#define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos) +#define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ +#define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos) +#define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ +#define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos) +#define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ +#define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos) +#define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ +#define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos) +#define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */ + +/* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t :2; /*!< bit: 0.. 1 Reserved */ + uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ + uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ + uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ + uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ + uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ + uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ + uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ + uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ +#define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ + +#define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ +#define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos) +#define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ +#define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos) +#define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ +#define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos) +#define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ +#define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos) +#define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ +#define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos) +#define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ +#define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos) +#define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ +#define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos) +#define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ +#define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos) +#define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */ + +/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ + __I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ + __I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ + __I uint16_t EORST:1; /*!< bit: 3 End of Reset */ + __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + __I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ + __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ + __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + __I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ + __I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ + __I uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ +#define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ + +#define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ +#define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos) +#define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ +#define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos) +#define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ +#define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos) +#define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ +#define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos) +#define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ +#define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos) +#define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ +#define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos) +#define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ +#define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos) +#define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ +#define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos) +#define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ +#define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos) +#define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ +#define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos) +#define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ + +/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint16_t :2; /*!< bit: 0.. 1 Reserved */ + __I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ + __I uint16_t RST:1; /*!< bit: 3 Bus Reset */ + __I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ + __I uint16_t DNRSM:1; /*!< bit: 5 Downstream */ + __I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ + __I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ + __I uint16_t DCONN:1; /*!< bit: 8 Device Connection */ + __I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ + __I uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ +#define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ + +#define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ +#define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos) +#define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ +#define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos) +#define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ +#define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos) +#define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ +#define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos) +#define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ +#define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos) +#define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ +#define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos) +#define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ +#define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos) +#define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ +#define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos) +#define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */ + +/* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTSMRY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ +#define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ + +#define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ +#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos) +#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)) +#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ + +/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ + uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ + uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ + uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ + uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ + uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ + uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ + uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_PINTSMRY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ +#define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ + +#define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) +#define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) +#define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) +#define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) +#define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) +#define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) +#define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) +#define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ +#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) +#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ +#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos) +#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)) +#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */ + +/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_DESCADD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ +#define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */ + +#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ +#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos) +#define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)) +#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */ + +/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ + uint16_t :1; /*!< bit: 5 Reserved */ + uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_PADCAL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ +#define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ + +#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ +#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos) +#define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)) +#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ +#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos) +#define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)) +#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ +#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos) +#define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)) +#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */ + +/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ + uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ +#define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ + +#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ +#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos) +#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)) +#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ +#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos) +#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)) +#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ +#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos) +#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */ + +/* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ + uint8_t BK:1; /*!< bit: 2 Pipe Bank */ + uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ +#define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ + +#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ +#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos) +#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)) +#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ +#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos) +#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ +#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos) +#define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)) +#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */ + +/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_BINTERVAL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ +#define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ + +#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ +#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos) +#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)) +#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */ + +/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPSTATUSCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ +#define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ + +#define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ +#define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) +#define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ +#define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) +#define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */ +#define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ +#define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ +#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ +#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) +#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)) +#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ +#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) +#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ +#define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) +#define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ + +/* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PSTATUSCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ +#define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ + +#define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ +#define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos) +#define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ +#define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos) +#define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ +#define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos) +#define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ +#define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos) +#define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ +#define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos) +#define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ + +/* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPSTATUSSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ +#define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ + +#define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ +#define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) +#define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ +#define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) +#define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ +#define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ +#define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ +#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ +#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) +#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)) +#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ +#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) +#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ +#define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) +#define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ + +/* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PSTATUSSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ +#define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ + +#define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ +#define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos) +#define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ +#define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos) +#define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ +#define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos) +#define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ +#define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos) +#define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ +#define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos) +#define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ + +/* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ + uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ + uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t :4; /*!< bit: 0.. 3 Reserved */ + uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ +#define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ + +#define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ +#define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) +#define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ +#define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos) +#define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ +#define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ +#define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ +#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ +#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos) +#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)) +#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ +#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos) +#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ +#define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos) +#define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ + +/* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t CURBK:1; /*!< bit: 2 Current Bank */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ + uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ +#define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ + +#define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ +#define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos) +#define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ +#define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos) +#define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ +#define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos) +#define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ +#define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos) +#define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ +#define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos) +#define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */ + +/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ + __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ + __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ + __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ + __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ + __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ + __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ + __I uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ + __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ + __I uint8_t :1; /*!< bit: 4 Reserved */ + __I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ + __I uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ +#define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ + +#define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ +#define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) +#define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ +#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) +#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ +#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos) +#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)) +#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ +#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) +#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ +#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) +#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ +#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) +#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)) +#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ +#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos) +#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ +#define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) +#define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ +#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) +#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ +#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos) +#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)) +#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ + +/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ + __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ + __I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ + __I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ + __I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ + __I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ + __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ +#define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ + +#define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) +#define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) +#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos) +#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)) +#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ +#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos) +#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ +#define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos) +#define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ +#define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos) +#define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ +#define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos) +#define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */ + +/* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ +#define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ + +#define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) +#define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) +#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos) +#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)) +#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) +#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) +#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) +#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)) +#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos) +#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) +#define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) +#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ +#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos) +#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)) +#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ + +/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ +#define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ + +#define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ +#define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) +#define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ +#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) +#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ +#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos) +#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)) +#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ +#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos) +#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ +#define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos) +#define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ +#define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos) +#define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Interrupt Disable */ +#define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos) +#define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */ + +/* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ + uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ + uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ + uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ + uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ + uint8_t :1; /*!< bit: 4 Reserved */ + uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ + uint8_t :1; /*!< bit: 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_EPINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ +#define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ + +#define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) +#define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) +#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos) +#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)) +#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) +#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) +#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos) +#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)) +#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ +#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos) +#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ +#define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) +#define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ +#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) +#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ +#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos) +#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)) +#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ + +/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ + uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ + uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ + uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ + uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ + uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_PINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ +#define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ + +#define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ +#define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) +#define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ +#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) +#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ +#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos) +#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)) +#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ +#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos) +#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ +#define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos) +#define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ +#define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos) +#define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ +#define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos) +#define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */ + +/* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_DEVICE_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ + +#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ +#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos) +#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)) +#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */ + +/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_HOST_ADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ + +#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ +#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos) +#define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)) +#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */ + +/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_DEVICE_PCKSIZE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ + +#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ +#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) +#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)) +#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ +#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) +#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)) +#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ +#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos) +#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)) +#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ +#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) +#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ + +/* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ + uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ + uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ + uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} USB_HOST_PCKSIZE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ + +#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ +#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) +#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)) +#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ +#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) +#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)) +#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ +#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos) +#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)) +#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ +#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) +#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */ + +/* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_DEVICE_EXTREG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ + +#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ +#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos) +#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)) +#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ +#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos) +#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)) +#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */ + +/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ + uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ + uint16_t :1; /*!< bit: 15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_EXTREG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ + +#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ +#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos) +#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)) +#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ +#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos) +#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)) +#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */ + +/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_DEVICE_STATUS_BK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ + +#define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ +#define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos) +#define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ +#define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) +#define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ + +/* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ + uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} USB_HOST_STATUS_BK_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ + +#define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ +#define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos) +#define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ +#define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos) +#define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */ + +/* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ + uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_CTRL_PIPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ +#define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ + +#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ +#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos) +#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)) +#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ +#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos) +#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)) +#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ +#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos) +#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)) +#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ + +/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ + uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ + uint16_t PIDER:1; /*!< bit: 2 PID Error */ + uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ + uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ + uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ + uint16_t :8; /*!< bit: 8..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} USB_HOST_STATUS_PIPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ + +#define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ +#define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos) +#define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ +#define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos) +#define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ +#define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos) +#define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ +#define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos) +#define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ +#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos) +#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ +#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos) +#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)) +#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ + +/** \brief UsbDeviceDescBank SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ + __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ + __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ + __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ + RoReg8 Reserved1[0x5]; +} UsbDeviceDescBank; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief UsbHostDescBank SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ + __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ + __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ + __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ + RoReg8 Reserved1[0x1]; + __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ + __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ +} UsbHostDescBank; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief UsbDeviceEndpoint hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ + RoReg8 Reserved1[0x3]; + __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ + __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ + __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ + __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ + __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ + __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ + RoReg8 Reserved2[0x16]; +} UsbDeviceEndpoint; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief UsbHostPipe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ + RoReg8 Reserved1[0x2]; + __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ + __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ + __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ + __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ + __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ + __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ + __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ + RoReg8 Reserved2[0x16]; +} UsbHostPipe; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_DEVICE APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Device */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ + __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ + RoReg8 Reserved3[0x1]; + __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ + RoReg8 Reserved5[0x2]; + __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ +} UsbDevice; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_HOST hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Host */ + __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ + RoReg8 Reserved1[0x1]; + __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ + __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ + RoReg8 Reserved2[0x4]; + __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ + __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ + RoReg8 Reserved3[0x1]; + __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ + __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ + RoReg8 Reserved4[0x2]; + __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ + __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ + RoReg8 Reserved5[0x1]; + __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ + RoReg8 Reserved6[0x2]; + __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ + RoReg8 Reserved7[0x2]; + __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ + RoReg8 Reserved8[0x2]; + __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ + RoReg8 Reserved9[0x2]; + __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ + __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ + RoReg8 Reserved10[0xD6]; + UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ +} UsbHost; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_DEVICE Descriptor SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Device */ + UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ +} UsbDeviceDescriptor; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief USB_HOST Descriptor SRAM registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { /* USB is Host */ + UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ +} UsbHostDescriptor; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SECTION_USB_DESCRIPTOR + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ + UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ +} Usb; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Register definition for USB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USB_CTRLA (0x41005000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (0x41005002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (0x41005003U) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (0x4100500DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (0x41005024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (0x41005028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (0x41005008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (0x4100500AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (0x4100500CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (0x41005008U) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (0x4100500CU) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (0x41005010U) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (0x41005012U) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#else +#define REG_USB_CTRLA (*(RwReg8 *)0x41005000U) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002U) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003U) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DU) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (*(RwReg *)0x41005024U) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (*(RwReg16*)0x41005028U) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AU) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CU) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010U) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008U) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AU) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CU) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010U) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012U) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014U) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018U) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CU) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020U) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100U) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120U) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140U) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160U) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180U) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0U) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0U) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0U) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3U) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5U) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6U) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9U) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for USB peripheral ========== */ +#define USB_EPT_NBR 8 // Number of USB end points (obsolete) +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 6 // Index of Generic Clock +#define USB_PIPE_NUM 8 // Number of USB pipes + + +#endif diff --git a/arch/arm/SAM_D2X/hdi/inc/hdi_wdt.h b/arch/arm/SAM_D2X/hdi/inc/hdi_wdt.h new file mode 100644 index 00000000..7d5d5fdc --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/inc/hdi_wdt.h @@ -0,0 +1,277 @@ +#ifndef _HDI_WDT_H_ +#define _HDI_WDT_H_ + +#define WDT_U2203 +#define REV_WDT 0x200 + +/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :1; /*!< bit: 0 Reserved */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */ +#define WDT_CTRL_RESETVALUE 0x00ul /**< \brief (WDT_CTRL reset_value) Control */ + +#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */ +#define WDT_CTRL_ENABLE (0x1ul << WDT_CTRL_ENABLE_Pos) +#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */ +#define WDT_CTRL_WEN (0x1ul << WDT_CTRL_WEN_Pos) +#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */ +#define WDT_CTRL_ALWAYSON (0x1ul << WDT_CTRL_ALWAYSON_Pos) +#define WDT_CTRL_MASK 0x86ul /**< \brief (WDT_CTRL) MASK Register */ + +/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ + uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_CONFIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */ +#define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */ + +#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */ +#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)) +#define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ +#define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ +#define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ +#define WDT_CONFIG_PER_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ +#define WDT_CONFIG_PER_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ +#define WDT_CONFIG_PER_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ +#define WDT_CONFIG_PER_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ +#define WDT_CONFIG_PER_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ +#define WDT_CONFIG_PER_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ +#define WDT_CONFIG_PER_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ +#define WDT_CONFIG_PER_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ +#define WDT_CONFIG_PER_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ +#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos) +#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */ +#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)) +#define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */ +#define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */ +#define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */ +#define WDT_CONFIG_WINDOW_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */ +#define WDT_CONFIG_WINDOW_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */ +#define WDT_CONFIG_WINDOW_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */ +#define WDT_CONFIG_WINDOW_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */ +#define WDT_CONFIG_WINDOW_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */ +#define WDT_CONFIG_WINDOW_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */ +#define WDT_CONFIG_WINDOW_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */ +#define WDT_CONFIG_WINDOW_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */ +#define WDT_CONFIG_WINDOW_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */ +#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos) +#define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */ + +/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_EWCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */ +#define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */ + +#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */ +#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)) +#define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_1K_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_2K_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_4K_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_8K_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_16K_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */ +#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos) +#define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */ + +/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */ +#define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */ + +#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */ +#define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos) +#define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */ + +/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */ +#define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */ + +#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */ +#define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos) +#define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */ + +/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t EW:1; /*!< bit: 0 Early Warning */ + __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */ +#define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */ +#define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos) +#define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */ + +/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */ +#define WDT_STATUS_RESETVALUE 0x00ul /**< \brief (WDT_STATUS reset_value) Status */ + +#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */ +#define WDT_STATUS_SYNCBUSY (0x1ul << WDT_STATUS_SYNCBUSY_Pos) +#define WDT_STATUS_MASK 0x80ul /**< \brief (WDT_STATUS) MASK Register */ + +/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} WDT_CLEAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */ +#define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */ + +#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */ +#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos) +#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)) +#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */ +#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos) +#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */ + +/** \brief WDT hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ + __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ + RoReg8 Reserved1[0x1]; + __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRL (0x40001000U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40001001U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_STATUS (0x40001007U) /**< \brief (WDT) Status */ +#define REG_WDT_CLEAR (0x40001008U) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRL (*(RwReg8 *)0x40001000U) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001U) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002U) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004U) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005U) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006U) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_STATUS (*(RoReg8 *)0x40001007U) /**< \brief (WDT) Status */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008U) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for WDT peripheral ========== */ +#define WDT_GCLK_ID 3 // Index of Generic Clock + + +#endif diff --git a/arch/arm/SAM_D2X/hdi/src/hdi_sam_d2x.c b/arch/arm/SAM_D2X/hdi/src/hdi_sam_d2x.c new file mode 100644 index 00000000..ae49c5d4 --- /dev/null +++ b/arch/arm/SAM_D2X/hdi/src/hdi_sam_d2x.c @@ -0,0 +1,254 @@ +#include "hdi_sam_d2x.h" +#include +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +int main(void); + +void __libc_init_array(void); + +// Dummy Handler +static void Dummy_Handler(void); + +#define __SYSTEM_CLOCK (1000000) + +/* Cortex-M0+ core Handlers */ +/* This needs to be moved to hal_arm eventually */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_USB +void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TC6 +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_ADC +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_I2S +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC1 +void AC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TCC3 +void TCC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNMI_Handler = (void*) NMI_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pvReservedM12 = (void*) (0UL), /* Reserved */ + .pvReservedM11 = (void*) (0UL), /* Reserved */ + .pvReservedM10 = (void*) (0UL), /* Reserved */ + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVC_Handler = (void*) SVC_Handler, + .pvReservedM4 = (void*) (0UL), /* Reserved */ + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnSYSCTRL_Handler = (void*) SYSCTRL_Handler, /* 1 System Control */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 2 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 3 Real-Time Counter */ + .pfnEIC_Handler = (void*) EIC_Handler, /* 4 External Interrupt Controller */ + .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ +#ifdef ID_USB + .pfnUSB_Handler = (void*) USB_Handler, /* 7 Universal Serial Bus */ +#else + .pvReserved7 = (void*) (0UL), /* 7 Reserved */ +#endif + .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 8 Event System Interface */ + .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ +#else + .pvReserved14 = (void*) (0UL), /* 14 Reserved */ +#endif + .pfnTCC0_Handler = (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ + .pfnTCC1_Handler = (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ + .pfnTCC2_Handler = (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ + .pfnTC4_Handler = (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ + .pfnTC5_Handler = (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ +#ifdef ID_TC6 + .pfnTC6_Handler = (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ +#else + .pvReserved21 = (void*) (0UL), /* 21 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ +#else + .pvReserved22 = (void*) (0UL), /* 22 Reserved */ +#endif +#ifdef ID_ADC + .pfnADC_Handler = (void*) ADC_Handler, /* 23 Analog Digital Converter */ +#else + .pvReserved23 = (void*) (0UL), /* 23 Reserved */ +#endif +#ifdef ID_AC + .pfnAC_Handler = (void*) AC_Handler, /* 24 Analog Comparators 0 */ +#else + .pvReserved24 = (void*) (0UL), /* 24 Reserved */ +#endif +#ifdef ID_DAC + .pfnDAC_Handler = (void*) DAC_Handler, /* 25 Digital Analog Converter */ +#else + .pvReserved25 = (void*) (0UL), /* 25 Reserved */ +#endif +#ifdef ID_PTC + .pfnPTC_Handler = (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif +#ifdef ID_I2S + .pfnI2S_Handler = (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif +#ifdef ID_AC1 + .pfnAC1_Handler = (void*) AC1_Handler, /* 28 Analog Comparators 1 */ +#else + .pvReserved28 = (void*) (0UL), /* 28 Reserved */ +#endif +#ifdef ID_TCC3 + .pfnTCC3_Handler = (void*) TCC3_Handler /* 29 Timer Counter Control 3 */ +#endif +}; + +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Change default QOS values to have the best performance and correct USB behaviour */ + SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; +#if defined(ID_USB) + USB->DEVICE.QOSCTRL.bit.CQOS = 2; + USB->DEVICE.QOSCTRL.bit.DQOS = 2; +#endif + DMAC->QOSCTRL.bit.DQOS = 2; + DMAC->QOSCTRL.bit.FQOS = 2; + DMAC->QOSCTRL.bit.WRBQOS = 2; + + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + + +void Dummy_Handler(void) +{ + while(1){} +} + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; + + +void SystemInit(void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +void SystemCoreClockUpdates(void) +{ + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/arch/arm/SAM_D2X/ld/ex.ld b/arch/arm/SAM_D2X/ld/ex.ld new file mode 100644 index 00000000..89dc411b --- /dev/null +++ b/arch/arm/SAM_D2X/ld/ex.ld @@ -0,0 +1,157 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21J18A + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/arch/arm/common/inc/cmsis/arm_common_tables.h b/arch/arm/common/inc/cmsis/arm_common_tables.h new file mode 100644 index 00000000..dfea7460 --- /dev/null +++ b/arch/arm/common/inc/cmsis/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/arch/arm/common/inc/cmsis/arm_const_structs.h b/arch/arm/common/inc/cmsis/arm_const_structs.h new file mode 100644 index 00000000..80a3e8bb --- /dev/null +++ b/arch/arm/common/inc/cmsis/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/arch/arm/common/inc/cmsis/arm_math.h b/arch/arm/common/inc/cmsis/arm_math.h new file mode 100644 index 00000000..ea9dd26a --- /dev/null +++ b/arch/arm/common/inc/cmsis/arm_math.h @@ -0,0 +1,7157 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/arch/arm/common/inc/cmsis/cmsis_compiler.h b/arch/arm/common/inc/cmsis/cmsis_compiler.h new file mode 100644 index 00000000..94212eb8 --- /dev/null +++ b/arch/arm/common/inc/cmsis/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/arch/arm/common/inc/cmsis/cmsis_gcc.h b/arch/arm/common/inc/cmsis/cmsis_gcc.h new file mode 100644 index 00000000..2d9db15a --- /dev/null +++ b/arch/arm/common/inc/cmsis/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/arch/arm/common/inc/cmsis/cmsis_iccarm.h b/arch/arm/common/inc/cmsis/cmsis_iccarm.h new file mode 100644 index 00000000..11c4af0e --- /dev/null +++ b/arch/arm/common/inc/cmsis/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/arch/arm/common/inc/cmsis/cmsis_version.h b/arch/arm/common/inc/cmsis/cmsis_version.h new file mode 100644 index 00000000..3b6bae4b --- /dev/null +++ b/arch/arm/common/inc/cmsis/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.4.0 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/arch/arm/common/inc/cmsis/core_cm0.h b/arch/arm/common/inc/cmsis/core_cm0.h new file mode 100644 index 00000000..f929bba0 --- /dev/null +++ b/arch/arm/common/inc/cmsis/core_cm0.h @@ -0,0 +1,949 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/arch/arm/common/inc/cmsis/core_cm0plus.h b/arch/arm/common/inc/cmsis/core_cm0plus.h new file mode 100644 index 00000000..424011ac --- /dev/null +++ b/arch/arm/common/inc/cmsis/core_cm0plus.h @@ -0,0 +1,1083 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/arch/arm/common/inc/cmsis/core_cm3.h b/arch/arm/common/inc/cmsis/core_cm3.h new file mode 100644 index 00000000..74bff64b --- /dev/null +++ b/arch/arm/common/inc/cmsis/core_cm3.h @@ -0,0 +1,1941 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/arch/arm/common/inc/cmsis/core_cm4.h b/arch/arm/common/inc/cmsis/core_cm4.h new file mode 100644 index 00000000..7d568735 --- /dev/null +++ b/arch/arm/common/inc/cmsis/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/arch/arm/common/inc/cmsis/core_cm7.h b/arch/arm/common/inc/cmsis/core_cm7.h new file mode 100644 index 00000000..a14dc623 --- /dev/null +++ b/arch/arm/common/inc/cmsis/core_cm7.h @@ -0,0 +1,2671 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/arch/arm/common/inc/cmsis/core_sc000.h b/arch/arm/common/inc/cmsis/core_sc000.h new file mode 100644 index 00000000..9b67c92f --- /dev/null +++ b/arch/arm/common/inc/cmsis/core_sc000.h @@ -0,0 +1,1022 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 28. May 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/arch/arm/common/inc/cmsis/core_sc300.h b/arch/arm/common/inc/cmsis/core_sc300.h new file mode 100644 index 00000000..3e8a4710 --- /dev/null +++ b/arch/arm/common/inc/cmsis/core_sc300.h @@ -0,0 +1,1915 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/arch/arm/common/inc/cmsis/mpu_armv7.h b/arch/arm/common/inc/cmsis/mpu_armv7.h new file mode 100644 index 00000000..01422033 --- /dev/null +++ b/arch/arm/common/inc/cmsis/mpu_armv7.h @@ -0,0 +1,270 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if non-shareable) or 010b (if shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/arch/arm/common/inc/epenguin_dev_arm_util.h b/arch/arm/common/inc/epenguin_dev_arm_util.h new file mode 100644 index 00000000..870eb835 --- /dev/null +++ b/arch/arm/common/inc/epenguin_dev_arm_util.h @@ -0,0 +1,20 @@ +#ifndef _EPENGUIN_DEV_ARM_UTIL_H_ +#define _EPENGUIN_DEV_ARM_UTIL_H_ + +// source -- http://www.highprogrammer.com/alan/windev/visualstudio.html +// Statements like: +//#pragma message(Reminder "Fix this problem!") +// Which will cause messages like: +//C:\Source\Project\main.cpp(47): Reminder: Fix this problem! +// to show up during compiles. Note that you can NOT use the +// words "error" or "warning" in your reminders, since it will +// make the IDE think it should abort execution. You can double +// click on these messages and jump to the line in question. +#define Stringize( L ) #L +#define MakeString( M, L ) M(L) +#define $Line \ + MakeString( Stringize, __LINE__ ) +#define Reminder \ + __FILE__ "(" $Line ") : Reminder: " + +#endif diff --git a/arch/arm/common/inc/hal_arm.hpp b/arch/arm/common/inc/hal_arm.hpp index a86c3d9c..d1387a12 100644 --- a/arch/arm/common/inc/hal_arm.hpp +++ b/arch/arm/common/inc/hal_arm.hpp @@ -4,13 +4,13 @@ #include "epenguin_conf.h" #if !(EP_UARCH == __UARCH_ARM__) - #error This shouldn't be included unless arm is the uarch of choice! + #error This shouldnt be included unless arm is the uarch of choice! #endif #if !(defined(__ASSEMBLY__)) #include -#ifndef __cplusplus +// #ifndef __cplusplus // typedef volatile const uint32_t RoReg; // Read only 32-bit register (volatile const unsigned int) // typedef volatile const uint16_t RoReg16; // Read only 16-bit register (volatile const unsigned int) // typedef volatile const uint8_t RoReg8; // Read only 8-bit register (volatile const unsigned int) @@ -35,5 +35,8 @@ typedef volatile uint8_t RwReg8; // Write only 8-bit register (volatile unsi #define REG_ACCESS(type, address) (address) #endif -namespace hal::arm{}; +namespace hal::arm +{ + +} #endif diff --git a/test/Makefile b/test/Makefile index e69de29b..f8167a80 100644 --- a/test/Makefile +++ b/test/Makefile @@ -0,0 +1,96 @@ +LDSCRIPT = ./ld/ex.ld +MCUTYPE=__SAMD21J18A__ +print-% : ; @echo $* = $($*) +BUILD_DIR:=build +SRC_DIR:=src +INC_DIR:=inc +BIN_DIR:=bin + +VERBOSE:=0 +_ATSYM_:=@ + +ifeq ($(VERBOSE),1) +_ATSYM_= +clean-build: +else +_ATSYM_=@ +endif + +# Tools +CC=arm-none-eabi-g++ +LD=arm-none-eabi-g++ +AR=arm-none-eabi-ar +AS=arm-none-eabi-as + +ELF=$(BIN_DIR)/main.elf + +INC:=$(sort $(shell find -L . -type f,l \( -name '*.h' -o -name '*.hpp' \) -printf '-I%h ' | sort -u)) + +vpath %.c $(sort $(shell find -L ./src -type f,l -name "*.c" -printf '%h\n' | sort -u)) +vpath %.s $(sort $(shell find -L ./src -type f,l -name "*.s" -printf '%h\n' | sort -u)) +vpath %.cpp $(sort $(shell find -L ./src -type f,l -name "*.cpp" -printf '%h\n' | sort -u)) +vpath %.o $(BUILD_DIR) + +OBJ_C=$(shell find -L ./src -type f,l -name '*.c') +OBJ_CPP=$(shell find -L ./src -type f,l -name '*.cpp') +OBJ_S=$(shell find -L ./src -type f,l -name '*.s') + + +OBJ:=$(addprefix $(BUILD_DIR)/, $(notdir $(OBJ_C:%.c=%.o))) +OBJ+=$(addprefix $(BUILD_DIR)/, $(notdir $(OBJ_CPP:%.cpp=%.o))) +OBJ+=$(addprefix $(BUILD_DIR)/, $(notdir $(OBJ_S:%.s=%.o))) + + +DEPS:=$(OBJ:.o=.d) + +LDFLAGS+= -T$(LDSCRIPT) -Wall -mthumb -mcpu=cortex-m0 -Wl,--gc-sections +CFLAGS+= $(INC) -mcpu=cortex-m0 -mthumb -ggdb -D$(MCUTYPE) + +.PHONY: all clean-build clean + +all: $(ELF) +$(ELF): $(OBJ) + @mkdir -p $(dir $@) + @echo "***************" + @echo "Linking Target: " $@ + @echo "prereq: $(OBJ)" + $(_ATSYM_)$(LD) $(LDFLAGS) -o $@ $(OBJ) $(LDLIBS) + +# compile and generate dependency info +$(BUILD_DIR)/%.o: %.c + @mkdir -p $(dir $@) + @echo "***************" + @echo "Compiling $< ---> $@" + $(_ATSYM_)$(CC) -c $(CFLAGS) $< -o $@ + @echo "Outputting Dependency from $< ---> "$(BUILD_DIR)/$*.d + $(_ATSYM_)$(CC) -MM $(CFLAGS) $< > $(BUILD_DIR)/$*.d + +# compile and generate dependency info +$(BUILD_DIR)/%.o: %.cpp + @mkdir -p $(dir $@) + @echo "***************" + @echo "Compiling $< ---> $@" + $(_ATSYM_)$(CC) -c $(CFLAGS) $< -o $@ + @echo "Outputting Dependency from $< ---> "$(BUILD_DIR)/$*.d + $(_ATSYM_)$(CC) -MM $(CFLAGS) $< > $(BUILD_DIR)/$*.d +$(BUILD_DIR)/%.o: %.s + @mkdir -p $(dir $@) + @echo "***************" + @echo "Assembling $< ---> $@" + $(_ATSYM_)$(AS) $< -o $@ + +clean: + @echo "Cleaning project..." + $(_ATSYM_)rm -f $(OBJ) $(DEPS) + $(_ATSYM_)rm -f $(BUILD_DIR)/*.d $(BUILD_DIR)/*.o + $(_ATSYM_)rm -f $(ELF) .gdb_history + +clean-build: clean all + +debug: $(ELF) + arm-none-eabi-gdb -iex "target extended-remote localhost:3333" $(ELF) + +# pull in dependencies +-include $(DEPS) + + diff --git a/test/conf/epenguin_conf.h b/test/conf/epenguin_conf.h index 13f2df11..729a79e1 100644 --- a/test/conf/epenguin_conf.h +++ b/test/conf/epenguin_conf.h @@ -1,8 +1,6 @@ #ifndef _EPENGUIN_CONF_H_ #define _EPENGUIN_CONF_H_ -#include "epenguin_master.h" - #define EP_UARCH __UARCH_ARM__ #define EP_MCU_FAMILY __SAM_D2X__ #define EP_MCU __ATSAMD21J18A__ diff --git a/test/inc/cmsis b/test/inc/cmsis new file mode 120000 index 00000000..8b0b4ce0 --- /dev/null +++ b/test/inc/cmsis @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/common/inc/cmsis/ \ No newline at end of file diff --git a/test/inc/common b/test/inc/common new file mode 120000 index 00000000..18fa6035 --- /dev/null +++ b/test/inc/common @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/arm/common/inc \ No newline at end of file diff --git a/test/inc/epenguin.hpp b/test/inc/epenguin.hpp new file mode 100644 index 00000000..e3fbfa1a --- /dev/null +++ b/test/inc/epenguin.hpp @@ -0,0 +1,89 @@ +#ifndef _EPENGUIN_HPP_ +#define _EPENGUIN_HPP_ + + + +/* -- ePenguin -- + + This master file dictates all supported hardware. It lists supported + architectures, mcu families, and specific mcus. This software framework + targets hardware at the mcu level--not at the board level. Board layers can + be applied, but this framework targets the mcu and the mcu alone. + +*/ +#ifndef __UARCHITECTURES__ +#define __UARCHITECTURES__ +#define __UARCH_ARM__ (0) +#define __UARCH_ARM64__ (1) +#define __UARCH_AVR__ (2) +#define __UARCH_AVR32__ (3) +#define __UARCH_X86__ (4) +#define __UARCH_RISCV__ (5) +#endif + +#ifndef __UFAMILIES__ +#define __UFAMILIES__ +/* Support ARM MCU Families */ + +/* Microchip */ +#define __SAM_D1X__ (0) +#define __SAM_C1X__ (1) +#define __SAM_D2X__ (2) +#define __SAM_E_D5X__ (3) +#define __SAM_C2X__ (4) +#define __SAM_L2X__ (5) + +/* STMicroelectronics */ + +/* NXP */ + +#endif + +#ifndef __UCONTROLLERS__ +#define __UCONTROLLERS__ + +/* ARM */ +/* Microchip */ +/* SAM_D2X */ +/* D2X Series E */ +#define __ATSAMD21E15A__ (0) +#define __ATSAMD21E15B__ (1) +#define __ATSAMD21E15BU__ (2) +#define __ATSAMD21E15L__ (3) +#define __ATSAMD21E16A__ (4) +#define __ATSAMD21E16B__ (5) +#define __ATSAMD21E16BU__ (6) +#define __ATSAMD21E16L__ (7) +#define __ATSAMD21E17A__ (8) +#define __ATSAMD21E17D__ (9) +#define __ATSAMD21E17DU__ (10) +#define __ATSAMD21E17L__ (11) +#define __ATSAMD21E18A__ (12) +/* D2X Series G */ +#define __ATSAMD21G15A__ (13) +#define __ATSAMD21G15B__ (14) +#define __ATSAMD21G15L__ (15) +#define __ATSAMD21G16A__ (16) +#define __ATSAMD21G16B__ (17) +#define __ATSAMD21G16L__ (18) +#define __ATSAMD21G17A__ (19) +#define __ATSAMD21G17AU__ (20) +#define __ATSAMD21G17D__ (21) +#define __ATSAMD21G17L__ (22) +#define __ATSAMD21G18A__ (23) +#define __ATSAMD21G18AU__ (24) +/* D2X Series J */ +#define __ATSAMD21J15A__ (25) +#define __ATSAMD21J15B__ (26) +#define __ATSAMD21J16A__ (27) +#define __ATSAMD21J16B__ (28) +#define __ATSAMD21J17A__ (29) +#define __ATSAMD21J17D__ (30) +#define __ATSAMD21J18A__ (31) + +#endif +#include "epenguin_conf.h" + +#endif + + diff --git a/test/inc/hal b/test/inc/hal new file mode 120000 index 00000000..e10667d0 --- /dev/null +++ b/test/inc/hal @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/arm/SAM_D2X/hal/inc \ No newline at end of file diff --git a/test/inc/hdi b/test/inc/hdi new file mode 120000 index 00000000..b30d5183 --- /dev/null +++ b/test/inc/hdi @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/arm/SAM_D2X/hdi/inc \ No newline at end of file diff --git a/test/ld/ex.ld b/test/ld/ex.ld new file mode 120000 index 00000000..aebbf841 --- /dev/null +++ b/test/ld/ex.ld @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/arm/SAM_D2X/ld/ex.ld \ No newline at end of file diff --git a/test/scripts/Makelinks.sh b/test/scripts/Makelinks.sh new file mode 100644 index 00000000..31d6e516 --- /dev/null +++ b/test/scripts/Makelinks.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +# links cmsis folder into our inc folder +# ln -s /storage/Shared/Documents/ASF_LIBS/xdk-asf-3.48.0/thirdparty/CMSIS/Include ./inc/cmsis +ln -s ${EPSF_HAL}/arch/common/inc/cmsis/ ./inc/cmsis +# links asf3 samd21 include folder into our inc folder +# ln -s /storage/Shared/Documents/ASF_LIBS/xdk-asf-3.48.0/sam0/utils/cmsis/samd21/include ./inc/asf3-inc +ln -s ${EPSF_HAL}/arch/arm/SAM_D2X/hal/inc ./inc/hal +ln -s ${EPSF_HAL}/arch/arm/SAM_D2X/hdi/inc ./inc/hdi +ln -s ${EPSF_HAL}/arch/arm/SAM_D2X/hal/src ./src/hal +ln -s ${EPSF_HAL}/arch/arm/SAM_D2X/hdi/src ./src/hdi +ln -s ${EPSF_HAL}/arch/arm/common/inc ./inc/common +ln -s ${EPSF_HAL}/arch/arm/common/src ./src/common +# links linker script into our linker folder +# ln -s /storage/Shared/Documents/ASF_LIBS/xdk-asf-3.48.0/sam0/utils/linker_scripts/samd21/gcc/samd21j18a_flash.ld ./linker/. +ln -s ${EPSF_HAL}/arch/arm/SAM_D2X/ld/ex.ld ./ld/ex.ld +# links asf3 startup code for d21 into our src folder +# ln -s /storage/Shared/Documents/ASF_LIBS/xdk-asf-3.48.0/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c ./src/. +# ln -s /storage/Shared/Documents/ASF_LIBS/xdk-asf-3.48.0/sam0/utils/cmsis/samd21/source/system_samd21.c ./src/. +# ln -s /storage/Shared/Documents/ASF_LIBS/xdk-asf-3.48.0/sam0/utils/cmsis/samd21/source/system_samd21.h ./inc/. diff --git a/test/scripts/Removelinks.sh b/test/scripts/Removelinks.sh new file mode 100644 index 00000000..dba722b0 --- /dev/null +++ b/test/scripts/Removelinks.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +rm -rf ./inc/cmsis ./inc/hal ./inc/hdi ./src/hal ./src/hdi ./ld/ex.ld ./inc/common ./src/common diff --git a/test/scripts/openocd.cfg b/test/scripts/openocd.cfg new file mode 100644 index 00000000..a0e7ab87 --- /dev/null +++ b/test/scripts/openocd.cfg @@ -0,0 +1,8 @@ +# Atmel-ICE JTAG/SWD in-circuit debugger. +interface cmsis-dap +cmsis_dap_vid_pid 0x03eb 0x2111 +cmsis_dap_serial 3 ATML2748051800004709 + +# Chip info +set CHIPNAME at91samd21j18 +source [find target/at91samdXX.cfg] diff --git a/test/src/common b/test/src/common new file mode 120000 index 00000000..90e4220a --- /dev/null +++ b/test/src/common @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/arm/common/src \ No newline at end of file diff --git a/test/src/hal b/test/src/hal new file mode 120000 index 00000000..fd56a01a --- /dev/null +++ b/test/src/hal @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/arm/SAM_D2X/hal/src \ No newline at end of file diff --git a/test/src/hdi b/test/src/hdi new file mode 120000 index 00000000..bdd2c805 --- /dev/null +++ b/test/src/hdi @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/epenguin_software_framework/arch/arm/SAM_D2X/hdi/src \ No newline at end of file diff --git a/test/src/main.cpp b/test/src/main.cpp new file mode 100644 index 00000000..190fb1b6 --- /dev/null +++ b/test/src/main.cpp @@ -0,0 +1,86 @@ +#include "epenguin.hpp" +#include "hal_sam_d2x.hpp" +#include + + +#define PORT_ADDR (0x41004400) + +#define PORT_GROUP_SIZE (0x80) + +#define PORT_A_OFF (0x00) +#define PORT_B_OFF (0x80) + +#define PORT_DIR_OFF (0x00) +#define PORT_OUT_OFF (0x10) + +// LED 0: PA09 +// LED 1: PB01 + +#define LED0_PORT (0) +#define LED0_PIN (9) + +#define LED1_PORT (1) +#define LED1_PIN (1) + +static void init_pin(int port, int pin); +static void set_pin(int port, int pin); +static void clr_pin(int port, int pin); + +static void delay(int n) +{ + int i; + + for(;n>0;n--) + { + for(i=0;i<100;i++) + { + + asm volatile("nop"); + } + } +} + + + +int main() +{ + init_pin(LED0_PORT, LED0_PIN); + init_pin(LED1_PORT, LED1_PIN); + for(;;) + { + set_pin(LED0_PORT, LED0_PIN); + clr_pin(LED1_PORT, LED1_PIN); + delay(500); + clr_pin(LED0_PORT, LED0_PIN); + set_pin(LED1_PORT, LED1_PIN); + delay(500); + } + return 0; +} + +// port 0: A +// port 1: B + + +void init_pin(int port, int pin) +{ + uint32_t* dir_reg = (uint32_t*)((PORT_ADDR | (port * PORT_GROUP_SIZE) | PORT_DIR_OFF)); + *dir_reg |= (1 << pin); +} + +void set_pin(int port, int pin) +{ + uint32_t* out_reg = (uint32_t*)((PORT_ADDR | (port * PORT_GROUP_SIZE) | PORT_OUT_OFF)); + *out_reg |= (1 << pin); +} + +void clr_pin(int port, int pin) +{ + uint32_t* out_reg = (uint32_t*)((PORT_ADDR | (port * PORT_GROUP_SIZE) | PORT_OUT_OFF)); + *out_reg &= ~(1 << pin); +} + + + + +