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80 lines
4.5 KiB
C
80 lines
4.5 KiB
C
5 years ago
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/**
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* \file
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*
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* \brief Instance description for PM
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_PM_INSTANCE_
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#define _SAMD21_PM_INSTANCE_
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/* ========== Register definition for PM peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */
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#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */
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#define REG_PM_EXTCTRL (0x40000402U) /**< \brief (PM) External Reset Controller */
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#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */
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#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */
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#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */
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#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */
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#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */
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#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */
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#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */
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#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */
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#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
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#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
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#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
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#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */
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#else
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#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
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#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
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#define REG_PM_EXTCTRL (*(RwReg8 *)0x40000402U) /**< \brief (PM) External Reset Controller */
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#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
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#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
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#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
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#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
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#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */
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#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */
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#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */
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#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */
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#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
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#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
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#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
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#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for PM peripheral ========== */
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#define PM_CTRL_MCSEL_DFLL48M 3
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#define PM_CTRL_MCSEL_GCLK 0
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#define PM_CTRL_MCSEL_OSC8M 1
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#define PM_CTRL_MCSEL_XOSC 2
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#define PM_PM_CLK_APB_NUM 2
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#endif /* _SAMD21_PM_INSTANCE_ */
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