SAME54P20A Test Project
icm.h
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1 
30 #ifndef _SAME54_ICM_COMPONENT_
31 #define _SAME54_ICM_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define ICM_U2010
40 #define REV_ICM 0x120
41 
42 /* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t WBDIS:1;
47  uint32_t EOMDIS:1;
48  uint32_t SLBDIS:1;
49  uint32_t :1;
50  uint32_t BBC:4;
51  uint32_t ASCD:1;
52  uint32_t DUALBUFF:1;
53  uint32_t :2;
54  uint32_t UIHASH:1;
55  uint32_t UALGO:3;
56  uint32_t HAPROT:6;
57  uint32_t :2;
58  uint32_t DAPROT:6;
59  uint32_t :2;
60  } bit;
61  uint32_t reg;
62 } ICM_CFG_Type;
63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
64 
65 #define ICM_CFG_OFFSET 0x00
66 #define ICM_CFG_RESETVALUE _U_(0x00000000)
68 #define ICM_CFG_WBDIS_Pos 0
69 #define ICM_CFG_WBDIS (_U_(0x1) << ICM_CFG_WBDIS_Pos)
70 #define ICM_CFG_EOMDIS_Pos 1
71 #define ICM_CFG_EOMDIS (_U_(0x1) << ICM_CFG_EOMDIS_Pos)
72 #define ICM_CFG_SLBDIS_Pos 2
73 #define ICM_CFG_SLBDIS (_U_(0x1) << ICM_CFG_SLBDIS_Pos)
74 #define ICM_CFG_BBC_Pos 4
75 #define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos)
76 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
77 #define ICM_CFG_ASCD_Pos 8
78 #define ICM_CFG_ASCD (_U_(0x1) << ICM_CFG_ASCD_Pos)
79 #define ICM_CFG_DUALBUFF_Pos 9
80 #define ICM_CFG_DUALBUFF (_U_(0x1) << ICM_CFG_DUALBUFF_Pos)
81 #define ICM_CFG_UIHASH_Pos 12
82 #define ICM_CFG_UIHASH (_U_(0x1) << ICM_CFG_UIHASH_Pos)
83 #define ICM_CFG_UALGO_Pos 13
84 #define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos)
85 #define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
86 #define ICM_CFG_UALGO_SHA1_Val _U_(0x0)
87 #define ICM_CFG_UALGO_SHA256_Val _U_(0x1)
88 #define ICM_CFG_UALGO_SHA224_Val _U_(0x4)
89 #define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos)
90 #define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos)
91 #define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos)
92 #define ICM_CFG_HAPROT_Pos 16
93 #define ICM_CFG_HAPROT_Msk (_U_(0x3F) << ICM_CFG_HAPROT_Pos)
94 #define ICM_CFG_HAPROT(value) (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))
95 #define ICM_CFG_DAPROT_Pos 24
96 #define ICM_CFG_DAPROT_Msk (_U_(0x3F) << ICM_CFG_DAPROT_Pos)
97 #define ICM_CFG_DAPROT(value) (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))
98 #define ICM_CFG_MASK _U_(0x3F3FF3F7)
100 /* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */
101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
102 typedef union {
103  struct {
104  uint32_t ENABLE:1;
105  uint32_t DISABLE:1;
106  uint32_t SWRST:1;
107  uint32_t :1;
108  uint32_t REHASH:4;
109  uint32_t RMDIS:4;
110  uint32_t RMEN:4;
111  uint32_t :16;
112  } bit;
113  uint32_t reg;
114 } ICM_CTRL_Type;
115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
116 
117 #define ICM_CTRL_OFFSET 0x04
119 #define ICM_CTRL_ENABLE_Pos 0
120 #define ICM_CTRL_ENABLE (_U_(0x1) << ICM_CTRL_ENABLE_Pos)
121 #define ICM_CTRL_DISABLE_Pos 1
122 #define ICM_CTRL_DISABLE (_U_(0x1) << ICM_CTRL_DISABLE_Pos)
123 #define ICM_CTRL_SWRST_Pos 2
124 #define ICM_CTRL_SWRST (_U_(0x1) << ICM_CTRL_SWRST_Pos)
125 #define ICM_CTRL_REHASH_Pos 4
126 #define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos)
127 #define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
128 #define ICM_CTRL_RMDIS_Pos 8
129 #define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos)
130 #define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
131 #define ICM_CTRL_RMEN_Pos 12
132 #define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos)
133 #define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
134 #define ICM_CTRL_MASK _U_(0x0000FFF7)
136 /* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status -------- */
137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
138 typedef union {
139  struct {
140  uint32_t ENABLE:1;
141  uint32_t :7;
142  uint32_t RAWRMDIS:4;
143  uint32_t RMDIS:4;
144  uint32_t :16;
145  } bit;
146  uint32_t reg;
147 } ICM_SR_Type;
148 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
149 
150 #define ICM_SR_OFFSET 0x08
151 #define ICM_SR_RESETVALUE _U_(0x00000000)
153 #define ICM_SR_ENABLE_Pos 0
154 #define ICM_SR_ENABLE (_U_(0x1) << ICM_SR_ENABLE_Pos)
155 #define ICM_SR_RAWRMDIS_Pos 8
156 #define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos)
157 #define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
158 #define ICM_SR_RMDIS_Pos 12
159 #define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos)
160 #define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
161 #define ICM_SR_MASK _U_(0x0000FF01)
163 /* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */
164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
165 typedef union {
166  struct {
167  uint32_t RHC:4;
168  uint32_t RDM:4;
169  uint32_t RBE:4;
170  uint32_t RWC:4;
171  uint32_t REC:4;
172  uint32_t RSU:4;
173  uint32_t URAD:1;
174  uint32_t :7;
175  } bit;
176  uint32_t reg;
177 } ICM_IER_Type;
178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
179 
180 #define ICM_IER_OFFSET 0x10
182 #define ICM_IER_RHC_Pos 0
183 #define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos)
184 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
185 #define ICM_IER_RDM_Pos 4
186 #define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos)
187 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
188 #define ICM_IER_RBE_Pos 8
189 #define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos)
190 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
191 #define ICM_IER_RWC_Pos 12
192 #define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos)
193 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
194 #define ICM_IER_REC_Pos 16
195 #define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos)
196 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
197 #define ICM_IER_RSU_Pos 20
198 #define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos)
199 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
200 #define ICM_IER_URAD_Pos 24
201 #define ICM_IER_URAD (_U_(0x1) << ICM_IER_URAD_Pos)
202 #define ICM_IER_MASK _U_(0x01FFFFFF)
204 /* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */
205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
206 typedef union {
207  struct {
208  uint32_t RHC:4;
209  uint32_t RDM:4;
210  uint32_t RBE:4;
211  uint32_t RWC:4;
212  uint32_t REC:4;
213  uint32_t RSU:4;
214  uint32_t URAD:1;
215  uint32_t :7;
216  } bit;
217  uint32_t reg;
218 } ICM_IDR_Type;
219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
220 
221 #define ICM_IDR_OFFSET 0x14
222 #define ICM_IDR_RESETVALUE _U_(0x00000000)
224 #define ICM_IDR_RHC_Pos 0
225 #define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos)
226 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
227 #define ICM_IDR_RDM_Pos 4
228 #define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos)
229 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
230 #define ICM_IDR_RBE_Pos 8
231 #define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos)
232 #define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
233 #define ICM_IDR_RWC_Pos 12
234 #define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos)
235 #define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
236 #define ICM_IDR_REC_Pos 16
237 #define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos)
238 #define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
239 #define ICM_IDR_RSU_Pos 20
240 #define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos)
241 #define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
242 #define ICM_IDR_URAD_Pos 24
243 #define ICM_IDR_URAD (_U_(0x1) << ICM_IDR_URAD_Pos)
244 #define ICM_IDR_MASK _U_(0x01FFFFFF)
246 /* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask -------- */
247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
248 typedef union {
249  struct {
250  uint32_t RHC:4;
251  uint32_t RDM:4;
252  uint32_t RBE:4;
253  uint32_t RWC:4;
254  uint32_t REC:4;
255  uint32_t RSU:4;
256  uint32_t URAD:1;
257  uint32_t :7;
258  } bit;
259  uint32_t reg;
260 } ICM_IMR_Type;
261 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
262 
263 #define ICM_IMR_OFFSET 0x18
264 #define ICM_IMR_RESETVALUE _U_(0x00000000)
266 #define ICM_IMR_RHC_Pos 0
267 #define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos)
268 #define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
269 #define ICM_IMR_RDM_Pos 4
270 #define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos)
271 #define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
272 #define ICM_IMR_RBE_Pos 8
273 #define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos)
274 #define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
275 #define ICM_IMR_RWC_Pos 12
276 #define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos)
277 #define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
278 #define ICM_IMR_REC_Pos 16
279 #define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos)
280 #define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
281 #define ICM_IMR_RSU_Pos 20
282 #define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos)
283 #define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
284 #define ICM_IMR_URAD_Pos 24
285 #define ICM_IMR_URAD (_U_(0x1) << ICM_IMR_URAD_Pos)
286 #define ICM_IMR_MASK _U_(0x01FFFFFF)
288 /* -------- ICM_ISR : (ICM Offset: 0x1C) (R/ 32) Interrupt Status -------- */
289 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
290 typedef union {
291  struct {
292  uint32_t RHC:4;
293  uint32_t RDM:4;
294  uint32_t RBE:4;
295  uint32_t RWC:4;
296  uint32_t REC:4;
297  uint32_t RSU:4;
298  uint32_t URAD:1;
299  uint32_t :7;
300  } bit;
301  uint32_t reg;
302 } ICM_ISR_Type;
303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
304 
305 #define ICM_ISR_OFFSET 0x1C
306 #define ICM_ISR_RESETVALUE _U_(0x00000000)
308 #define ICM_ISR_RHC_Pos 0
309 #define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos)
310 #define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
311 #define ICM_ISR_RDM_Pos 4
312 #define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos)
313 #define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
314 #define ICM_ISR_RBE_Pos 8
315 #define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos)
316 #define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
317 #define ICM_ISR_RWC_Pos 12
318 #define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos)
319 #define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
320 #define ICM_ISR_REC_Pos 16
321 #define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos)
322 #define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
323 #define ICM_ISR_RSU_Pos 20
324 #define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos)
325 #define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
326 #define ICM_ISR_URAD_Pos 24
327 #define ICM_ISR_URAD (_U_(0x1) << ICM_ISR_URAD_Pos)
328 #define ICM_ISR_MASK _U_(0x01FFFFFF)
330 /* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status -------- */
331 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
332 typedef union {
333  struct {
334  uint32_t URAT:3;
335  uint32_t :29;
336  } bit;
337  uint32_t reg;
338 } ICM_UASR_Type;
339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
340 
341 #define ICM_UASR_OFFSET 0x20
342 #define ICM_UASR_RESETVALUE _U_(0x00000000)
344 #define ICM_UASR_URAT_Pos 0
345 #define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos)
346 #define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
347 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0)
348 #define ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1)
349 #define ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2)
350 #define ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3)
351 #define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4)
352 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos)
353 #define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos)
354 #define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos)
355 #define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos)
356 #define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos)
357 #define ICM_UASR_MASK _U_(0x00000007)
359 /* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */
360 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
361 typedef union {
362  struct {
363  uint32_t :6;
364  uint32_t DASA:26;
365  } bit;
366  uint32_t reg;
367 } ICM_DSCR_Type;
368 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
369 
370 #define ICM_DSCR_OFFSET 0x30
371 #define ICM_DSCR_RESETVALUE _U_(0x00000000)
373 #define ICM_DSCR_DASA_Pos 6
374 #define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos)
375 #define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
376 #define ICM_DSCR_MASK _U_(0xFFFFFFC0)
378 /* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */
379 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
380 typedef union {
381  struct {
382  uint32_t :7;
383  uint32_t HASA:25;
384  } bit;
385  uint32_t reg;
386 } ICM_HASH_Type;
387 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
388 
389 #define ICM_HASH_OFFSET 0x34
390 #define ICM_HASH_RESETVALUE _U_(0x00000000)
392 #define ICM_HASH_HASA_Pos 7
393 #define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos)
394 #define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
395 #define ICM_HASH_MASK _U_(0xFFFFFF80)
397 /* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */
398 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
399 typedef union {
400  struct {
401  uint32_t VAL:32;
402  } bit;
403  uint32_t reg;
405 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
406 
407 #define ICM_UIHVAL_OFFSET 0x38
408 #define ICM_UIHVAL_RESETVALUE _U_(0x00000000)
410 #define ICM_UIHVAL_VAL_Pos 0
411 #define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos)
412 #define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
413 #define ICM_UIHVAL_MASK _U_(0xFFFFFFFF)
415 /* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */
416 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
417 typedef union {
418  uint32_t reg;
420 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
421 
422 #define ICM_RADDR_OFFSET 0x00
423 #define ICM_RADDR_MASK _U_(0xFFFFFFFF)
425 /* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */
426 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
427 typedef union {
428  struct {
429  uint32_t CDWBN:1;
430  uint32_t WRAP:1;
431  uint32_t EOM:1;
432  uint32_t :1;
433  uint32_t RHIEN:1;
434  uint32_t DMIEN:1;
435  uint32_t BEIEN:1;
436  uint32_t WCIEN:1;
437  uint32_t ECIEN:1;
438  uint32_t SUIEN:1;
439  uint32_t PROCDLY:1;
440  uint32_t :1;
441  uint32_t ALGO:3;
442  uint32_t :9;
443  uint32_t MRPROT:6;
444  uint32_t :2;
445  } bit;
446  uint32_t reg;
447 } ICM_RCFG_Type;
448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
449 
450 #define ICM_RCFG_OFFSET 0x04
451 #define ICM_RCFG_RESETVALUE _U_(0x00000000)
453 #define ICM_RCFG_CDWBN_Pos 0
454 #define ICM_RCFG_CDWBN (_U_(0x1) << ICM_RCFG_CDWBN_Pos)
455 #define ICM_RCFG_CDWBN_WRBA_Val _U_(0x0)
456 #define ICM_RCFG_CDWBN_COMP_Val _U_(0x1)
457 #define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos)
458 #define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos)
459 #define ICM_RCFG_WRAP_Pos 1
460 #define ICM_RCFG_WRAP (_U_(0x1) << ICM_RCFG_WRAP_Pos)
461 #define ICM_RCFG_WRAP_NO_Val _U_(0x0)
462 #define ICM_RCFG_WRAP_YES_Val _U_(0x1)
463 #define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos)
464 #define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos)
465 #define ICM_RCFG_EOM_Pos 2
466 #define ICM_RCFG_EOM (_U_(0x1) << ICM_RCFG_EOM_Pos)
467 #define ICM_RCFG_EOM_NO_Val _U_(0x0)
468 #define ICM_RCFG_EOM_YES_Val _U_(0x1)
469 #define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos)
470 #define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos)
471 #define ICM_RCFG_RHIEN_Pos 4
472 #define ICM_RCFG_RHIEN (_U_(0x1) << ICM_RCFG_RHIEN_Pos)
473 #define ICM_RCFG_RHIEN_EN_Val _U_(0x0)
474 #define ICM_RCFG_RHIEN_DIS_Val _U_(0x1)
475 #define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos)
476 #define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos)
477 #define ICM_RCFG_DMIEN_Pos 5
478 #define ICM_RCFG_DMIEN (_U_(0x1) << ICM_RCFG_DMIEN_Pos)
479 #define ICM_RCFG_DMIEN_EN_Val _U_(0x0)
480 #define ICM_RCFG_DMIEN_DIS_Val _U_(0x1)
481 #define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos)
482 #define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos)
483 #define ICM_RCFG_BEIEN_Pos 6
484 #define ICM_RCFG_BEIEN (_U_(0x1) << ICM_RCFG_BEIEN_Pos)
485 #define ICM_RCFG_BEIEN_EN_Val _U_(0x0)
486 #define ICM_RCFG_BEIEN_DIS_Val _U_(0x1)
487 #define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos)
488 #define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos)
489 #define ICM_RCFG_WCIEN_Pos 7
490 #define ICM_RCFG_WCIEN (_U_(0x1) << ICM_RCFG_WCIEN_Pos)
491 #define ICM_RCFG_WCIEN_EN_Val _U_(0x0)
492 #define ICM_RCFG_WCIEN_DIS_Val _U_(0x1)
493 #define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos)
494 #define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos)
495 #define ICM_RCFG_ECIEN_Pos 8
496 #define ICM_RCFG_ECIEN (_U_(0x1) << ICM_RCFG_ECIEN_Pos)
497 #define ICM_RCFG_ECIEN_EN_Val _U_(0x0)
498 #define ICM_RCFG_ECIEN_DIS_Val _U_(0x1)
499 #define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos)
500 #define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos)
501 #define ICM_RCFG_SUIEN_Pos 9
502 #define ICM_RCFG_SUIEN (_U_(0x1) << ICM_RCFG_SUIEN_Pos)
503 #define ICM_RCFG_SUIEN_EN_Val _U_(0x0)
504 #define ICM_RCFG_SUIEN_DIS_Val _U_(0x1)
505 #define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos)
506 #define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos)
507 #define ICM_RCFG_PROCDLY_Pos 10
508 #define ICM_RCFG_PROCDLY (_U_(0x1) << ICM_RCFG_PROCDLY_Pos)
509 #define ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0)
510 #define ICM_RCFG_PROCDLY_LONG_Val _U_(0x1)
511 #define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos)
512 #define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos)
513 #define ICM_RCFG_ALGO_Pos 12
514 #define ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos)
515 #define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos))
516 #define ICM_RCFG_MRPROT_Pos 24
517 #define ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos)
518 #define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))
519 #define ICM_RCFG_MASK _U_(0x3F0077F7)
521 /* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */
522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
523 typedef union {
524  struct {
525  uint32_t TRSIZE:16;
526  uint32_t :16;
527  } bit;
528  uint32_t reg;
530 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
531 
532 #define ICM_RCTRL_OFFSET 0x08
534 #define ICM_RCTRL_TRSIZE_Pos 0
535 #define ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos)
536 #define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos))
537 #define ICM_RCTRL_MASK _U_(0x0000FFFF)
539 /* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */
540 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
541 typedef union {
542  uint32_t reg;
544 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
545 
546 #define ICM_RNEXT_OFFSET 0x0C
547 #define ICM_RNEXT_MASK _U_(0xFFFFFFFF)
550 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
551 typedef struct {
555  RoReg8 Reserved1[0x4];
561  RoReg8 Reserved2[0xC];
564  __O ICM_UIHVAL_Type UIHVAL[8];
565 } Icm;
566 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
567 
569 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
570 typedef struct {
575 } IcmDescriptor;
576 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
577 
578 #define SECTION_ICM_DESCRIPTOR
579 
582 #endif /* _SAME54_ICM_COMPONENT_ */
ICM_SR_Type::reg
uint32_t reg
Definition: icm.h:146
ICM_ISR_Type::RWC
uint32_t RWC
Definition: icm.h:295
Icm::DSCR
__IO ICM_DSCR_Type DSCR
Offset: 0x30 (R/W 32) Region Descriptor Area Start Address.
Definition: icm.h:562
ICM_RCFG_Type::EOM
uint32_t EOM
Definition: icm.h:431
ICM_IMR_Type::REC
uint32_t REC
Definition: icm.h:254
Icm::IMR
__I ICM_IMR_Type IMR
Offset: 0x18 (R/ 32) Interrupt Mask.
Definition: icm.h:558
ICM_ISR_Type::URAD
uint32_t URAD
Definition: icm.h:298
ICM_CFG_Type::WBDIS
uint32_t WBDIS
Definition: icm.h:46
ICM_RCFG_Type
Definition: icm.h:427
ICM_UIHVAL_Type
Definition: icm.h:399
ICM_DSCR_Type::reg
uint32_t reg
Definition: icm.h:366
ICM_CFG_Type::BBC
uint32_t BBC
Definition: icm.h:50
ICM_CTRL_Type::RMEN
uint32_t RMEN
Definition: icm.h:110
ICM_CFG_Type::UIHASH
uint32_t UIHASH
Definition: icm.h:54
ICM_SR_Type::ENABLE
uint32_t ENABLE
Definition: icm.h:140
ICM_UASR_Type
Definition: icm.h:332
ICM_RCFG_Type::ECIEN
uint32_t ECIEN
Definition: icm.h:437
ICM_DSCR_Type
Definition: icm.h:361
Icm::IDR
__O ICM_IDR_Type IDR
Offset: 0x14 ( /W 32) Interrupt Disable.
Definition: icm.h:557
ICM_UIHVAL_Type::reg
uint32_t reg
Definition: icm.h:403
ICM_RCFG_Type::PROCDLY
uint32_t PROCDLY
Definition: icm.h:439
ICM_IMR_Type::RWC
uint32_t RWC
Definition: icm.h:253
ICM_RCFG_Type::ALGO
uint32_t ALGO
Definition: icm.h:441
Icm
ICM APB hardware registers.
Definition: icm.h:551
ICM_IDR_Type
Definition: icm.h:206
Icm::HASH
__IO ICM_HASH_Type HASH
Offset: 0x34 (R/W 32) Region Hash Area Start Address.
Definition: icm.h:563
ICM_HASH_Type
Definition: icm.h:380
ICM_UASR_Type::reg
uint32_t reg
Definition: icm.h:337
ICM_SR_Type
Definition: icm.h:138
ICM_IMR_Type::RHC
uint32_t RHC
Definition: icm.h:250
ICM_CFG_Type::UALGO
uint32_t UALGO
Definition: icm.h:55
ICM_HASH_Type::HASA
uint32_t HASA
Definition: icm.h:383
ICM_RNEXT_Type::reg
uint32_t reg
Definition: icm.h:542
ICM_IMR_Type
Definition: icm.h:248
Icm::CTRL
__O ICM_CTRL_Type CTRL
Offset: 0x04 ( /W 32) Control.
Definition: icm.h:553
ICM_RADDR_Type::reg
uint32_t reg
Definition: icm.h:418
ICM_CTRL_Type::REHASH
uint32_t REHASH
Definition: icm.h:108
ICM_CTRL_Type::SWRST
uint32_t SWRST
Definition: icm.h:106
ICM_RCTRL_Type::reg
uint32_t reg
Definition: icm.h:528
ICM_RCTRL_Type::TRSIZE
uint32_t TRSIZE
Definition: icm.h:525
ICM_IDR_Type::RDM
uint32_t RDM
Definition: icm.h:209
ICM_IMR_Type::RBE
uint32_t RBE
Definition: icm.h:252
IcmDescriptor::RADDR
__IO ICM_RADDR_Type RADDR
Offset: 0x00 (R/W 32) Region Start Address.
Definition: icm.h:571
ICM_UASR_Type::URAT
uint32_t URAT
Definition: icm.h:334
IcmDescriptor
ICM Descriptor SRAM registers.
Definition: icm.h:570
ICM_CFG_Type::HAPROT
uint32_t HAPROT
Definition: icm.h:56
ICM_ISR_Type::RSU
uint32_t RSU
Definition: icm.h:297
ICM_IER_Type::RSU
uint32_t RSU
Definition: icm.h:172
ICM_HASH_Type::reg
uint32_t reg
Definition: icm.h:385
Icm::ISR
__I ICM_ISR_Type ISR
Offset: 0x1C (R/ 32) Interrupt Status.
Definition: icm.h:559
ICM_SR_Type::RAWRMDIS
uint32_t RAWRMDIS
Definition: icm.h:142
ICM_IDR_Type::RSU
uint32_t RSU
Definition: icm.h:213
ICM_RNEXT_Type
Definition: icm.h:541
ICM_RCFG_Type::CDWBN
uint32_t CDWBN
Definition: icm.h:429
ICM_RCFG_Type::WCIEN
uint32_t WCIEN
Definition: icm.h:436
ICM_IER_Type::reg
uint32_t reg
Definition: icm.h:176
Icm::IER
__O ICM_IER_Type IER
Offset: 0x10 ( /W 32) Interrupt Enable.
Definition: icm.h:556
Icm::CFG
__IO ICM_CFG_Type CFG
Offset: 0x00 (R/W 32) Configuration.
Definition: icm.h:552
ICM_CFG_Type::DAPROT
uint32_t DAPROT
Definition: icm.h:58
ICM_DSCR_Type::DASA
uint32_t DASA
Definition: icm.h:364
ICM_CFG_Type::ASCD
uint32_t ASCD
Definition: icm.h:51
ICM_CTRL_Type::reg
uint32_t reg
Definition: icm.h:113
ICM_RCFG_Type::RHIEN
uint32_t RHIEN
Definition: icm.h:433
ICM_CTRL_Type
Definition: icm.h:102
ICM_IDR_Type::REC
uint32_t REC
Definition: icm.h:212
ICM_IER_Type::RDM
uint32_t RDM
Definition: icm.h:168
ICM_RCFG_Type::DMIEN
uint32_t DMIEN
Definition: icm.h:434
ICM_ISR_Type::RBE
uint32_t RBE
Definition: icm.h:294
ICM_IER_Type::URAD
uint32_t URAD
Definition: icm.h:173
ICM_IMR_Type::RDM
uint32_t RDM
Definition: icm.h:251
ICM_CFG_Type
Definition: icm.h:44
ICM_UIHVAL_Type::VAL
uint32_t VAL
Definition: icm.h:401
ICM_IER_Type::RBE
uint32_t RBE
Definition: icm.h:169
ICM_RCTRL_Type
Definition: icm.h:523
ICM_IDR_Type::URAD
uint32_t URAD
Definition: icm.h:214
Icm::UASR
__I ICM_UASR_Type UASR
Offset: 0x20 (R/ 32) Undefined Access Status.
Definition: icm.h:560
ICM_IDR_Type::RHC
uint32_t RHC
Definition: icm.h:208
ICM_IDR_Type::reg
uint32_t reg
Definition: icm.h:217
ICM_RADDR_Type
Definition: icm.h:417
ICM_CFG_Type::SLBDIS
uint32_t SLBDIS
Definition: icm.h:48
ICM_IER_Type::RWC
uint32_t RWC
Definition: icm.h:170
ICM_CTRL_Type::ENABLE
uint32_t ENABLE
Definition: icm.h:104
ICM_SR_Type::RMDIS
uint32_t RMDIS
Definition: icm.h:143
IcmDescriptor::RNEXT
__IO ICM_RNEXT_Type RNEXT
Offset: 0x0C (R/W 32) Region Next Address.
Definition: icm.h:574
ICM_IER_Type::REC
uint32_t REC
Definition: icm.h:171
ICM_IER_Type
Definition: icm.h:165
ICM_CTRL_Type::RMDIS
uint32_t RMDIS
Definition: icm.h:109
IcmDescriptor::RCFG
__IO ICM_RCFG_Type RCFG
Offset: 0x04 (R/W 32) Region Configuration.
Definition: icm.h:572
ICM_IDR_Type::RBE
uint32_t RBE
Definition: icm.h:210
ICM_ISR_Type::RDM
uint32_t RDM
Definition: icm.h:293
ICM_IMR_Type::reg
uint32_t reg
Definition: icm.h:259
ICM_ISR_Type
Definition: icm.h:290
IcmDescriptor::RCTRL
__IO ICM_RCTRL_Type RCTRL
Offset: 0x08 (R/W 32) Region Control.
Definition: icm.h:573
ICM_RCFG_Type::BEIEN
uint32_t BEIEN
Definition: icm.h:435
ICM_RCFG_Type::WRAP
uint32_t WRAP
Definition: icm.h:430
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
ICM_IMR_Type::URAD
uint32_t URAD
Definition: icm.h:256
ICM_CFG_Type::DUALBUFF
uint32_t DUALBUFF
Definition: icm.h:52
ICM_RCFG_Type::MRPROT
uint32_t MRPROT
Definition: icm.h:443
ICM_IER_Type::RHC
uint32_t RHC
Definition: icm.h:167
Icm::SR
__I ICM_SR_Type SR
Offset: 0x08 (R/ 32) Status.
Definition: icm.h:554
ICM_IDR_Type::RWC
uint32_t RWC
Definition: icm.h:211
ICM_RCFG_Type::reg
uint32_t reg
Definition: icm.h:446
ICM_ISR_Type::RHC
uint32_t RHC
Definition: icm.h:292
ICM_ISR_Type::REC
uint32_t REC
Definition: icm.h:296
ICM_CFG_Type::EOMDIS
uint32_t EOMDIS
Definition: icm.h:47
ICM_CFG_Type::reg
uint32_t reg
Definition: icm.h:61
ICM_RCFG_Type::SUIEN
uint32_t SUIEN
Definition: icm.h:438
ICM_CTRL_Type::DISABLE
uint32_t DISABLE
Definition: icm.h:105
ICM_IMR_Type::RSU
uint32_t RSU
Definition: icm.h:255
ICM_ISR_Type::reg
uint32_t reg
Definition: icm.h:301