SAME54P20A Test Project
dmac.h
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1 
30 #ifndef _SAME54_DMAC_COMPONENT_
31 #define _SAME54_DMAC_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define DMAC_U2503
40 #define REV_DMAC 0x101
41 
42 /* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint16_t SWRST:1;
47  uint16_t DMAENABLE:1;
48  uint16_t :6;
49  uint16_t LVLEN0:1;
50  uint16_t LVLEN1:1;
51  uint16_t LVLEN2:1;
52  uint16_t LVLEN3:1;
53  uint16_t :4;
54  } bit;
55  struct {
56  uint16_t :8;
57  uint16_t LVLEN:4;
58  uint16_t :4;
59  } vec;
60  uint16_t reg;
62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
63 
64 #define DMAC_CTRL_OFFSET 0x00
65 #define DMAC_CTRL_RESETVALUE _U_(0x0000)
67 #define DMAC_CTRL_SWRST_Pos 0
68 #define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
69 #define DMAC_CTRL_DMAENABLE_Pos 1
70 #define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
71 #define DMAC_CTRL_LVLEN0_Pos 8
72 #define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
73 #define DMAC_CTRL_LVLEN1_Pos 9
74 #define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
75 #define DMAC_CTRL_LVLEN2_Pos 10
76 #define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
77 #define DMAC_CTRL_LVLEN3_Pos 11
78 #define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
79 #define DMAC_CTRL_LVLEN_Pos 8
80 #define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
81 #define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
82 #define DMAC_CTRL_MASK _U_(0x0F03)
84 /* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
86 typedef union {
87  struct {
88  uint16_t CRCBEATSIZE:2;
89  uint16_t CRCPOLY:2;
90  uint16_t :4;
91  uint16_t CRCSRC:6;
92  uint16_t CRCMODE:2;
93  } bit;
94  uint16_t reg;
96 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
97 
98 #define DMAC_CRCCTRL_OFFSET 0x02
99 #define DMAC_CRCCTRL_RESETVALUE _U_(0x0000)
101 #define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0
102 #define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
103 #define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
104 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0)
105 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1)
106 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2)
107 #define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
108 #define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
109 #define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
110 #define DMAC_CRCCTRL_CRCPOLY_Pos 2
111 #define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
112 #define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
113 #define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0)
114 #define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1)
115 #define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
116 #define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
117 #define DMAC_CRCCTRL_CRCSRC_Pos 8
118 #define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
119 #define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
120 #define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0)
121 #define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1)
122 #define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
123 #define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
124 #define DMAC_CRCCTRL_CRCMODE_Pos 14
125 #define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
126 #define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
127 #define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0)
128 #define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2)
129 #define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3)
130 #define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
131 #define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
132 #define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
133 #define DMAC_CRCCTRL_MASK _U_(0xFF0F)
135 /* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
136 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
137 typedef union {
138  struct {
139  uint32_t CRCDATAIN:32;
140  } bit;
141  uint32_t reg;
143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
144 
145 #define DMAC_CRCDATAIN_OFFSET 0x04
146 #define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000)
148 #define DMAC_CRCDATAIN_CRCDATAIN_Pos 0
149 #define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
150 #define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
151 #define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF)
153 /* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
154 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
155 typedef union {
156  struct {
157  uint32_t CRCCHKSUM:32;
158  } bit;
159  uint32_t reg;
161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
162 
163 #define DMAC_CRCCHKSUM_OFFSET 0x08
164 #define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000)
166 #define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0
167 #define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
168 #define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
169 #define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF)
171 /* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
173 typedef union {
174  struct {
175  uint8_t CRCBUSY:1;
176  uint8_t CRCZERO:1;
177  uint8_t CRCERR:1;
178  uint8_t :5;
179  } bit;
180  uint8_t reg;
182 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
183 
184 #define DMAC_CRCSTATUS_OFFSET 0x0C
185 #define DMAC_CRCSTATUS_RESETVALUE _U_(0x00)
187 #define DMAC_CRCSTATUS_CRCBUSY_Pos 0
188 #define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
189 #define DMAC_CRCSTATUS_CRCZERO_Pos 1
190 #define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
191 #define DMAC_CRCSTATUS_CRCERR_Pos 2
192 #define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
193 #define DMAC_CRCSTATUS_MASK _U_(0x07)
195 /* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
196 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
197 typedef union {
198  struct {
199  uint8_t DBGRUN:1;
200  uint8_t :7;
201  } bit;
202  uint8_t reg;
204 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
205 
206 #define DMAC_DBGCTRL_OFFSET 0x0D
207 #define DMAC_DBGCTRL_RESETVALUE _U_(0x00)
209 #define DMAC_DBGCTRL_DBGRUN_Pos 0
210 #define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
211 #define DMAC_DBGCTRL_MASK _U_(0x01)
213 /* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
214 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
215 typedef union {
216  struct {
217  uint32_t SWTRIG0:1;
218  uint32_t SWTRIG1:1;
219  uint32_t SWTRIG2:1;
220  uint32_t SWTRIG3:1;
221  uint32_t SWTRIG4:1;
222  uint32_t SWTRIG5:1;
223  uint32_t SWTRIG6:1;
224  uint32_t SWTRIG7:1;
225  uint32_t SWTRIG8:1;
226  uint32_t SWTRIG9:1;
227  uint32_t SWTRIG10:1;
228  uint32_t SWTRIG11:1;
229  uint32_t SWTRIG12:1;
230  uint32_t SWTRIG13:1;
231  uint32_t SWTRIG14:1;
232  uint32_t SWTRIG15:1;
233  uint32_t SWTRIG16:1;
234  uint32_t SWTRIG17:1;
235  uint32_t SWTRIG18:1;
236  uint32_t SWTRIG19:1;
237  uint32_t SWTRIG20:1;
238  uint32_t SWTRIG21:1;
239  uint32_t SWTRIG22:1;
240  uint32_t SWTRIG23:1;
241  uint32_t SWTRIG24:1;
242  uint32_t SWTRIG25:1;
243  uint32_t SWTRIG26:1;
244  uint32_t SWTRIG27:1;
245  uint32_t SWTRIG28:1;
246  uint32_t SWTRIG29:1;
247  uint32_t SWTRIG30:1;
248  uint32_t SWTRIG31:1;
249  } bit;
250  struct {
251  uint32_t SWTRIG:32;
252  } vec;
253  uint32_t reg;
255 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
256 
257 #define DMAC_SWTRIGCTRL_OFFSET 0x10
258 #define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000)
260 #define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0
261 #define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
262 #define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1
263 #define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
264 #define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2
265 #define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
266 #define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3
267 #define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
268 #define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4
269 #define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
270 #define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5
271 #define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
272 #define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6
273 #define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
274 #define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7
275 #define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
276 #define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8
277 #define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
278 #define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9
279 #define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
280 #define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10
281 #define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
282 #define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11
283 #define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
284 #define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12
285 #define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
286 #define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13
287 #define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
288 #define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14
289 #define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
290 #define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15
291 #define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
292 #define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16
293 #define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
294 #define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17
295 #define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
296 #define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18
297 #define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
298 #define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19
299 #define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
300 #define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20
301 #define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
302 #define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21
303 #define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
304 #define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22
305 #define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
306 #define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23
307 #define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
308 #define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24
309 #define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
310 #define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25
311 #define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
312 #define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26
313 #define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
314 #define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27
315 #define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
316 #define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28
317 #define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
318 #define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29
319 #define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
320 #define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30
321 #define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
322 #define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31
323 #define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
324 #define DMAC_SWTRIGCTRL_SWTRIG_Pos 0
325 #define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
326 #define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
327 #define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF)
329 /* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
331 typedef union {
332  struct {
333  uint32_t LVLPRI0:5;
334  uint32_t QOS0:2;
335  uint32_t RRLVLEN0:1;
336  uint32_t LVLPRI1:5;
337  uint32_t QOS1:2;
338  uint32_t RRLVLEN1:1;
339  uint32_t LVLPRI2:5;
340  uint32_t QOS2:2;
341  uint32_t RRLVLEN2:1;
342  uint32_t LVLPRI3:5;
343  uint32_t QOS3:2;
344  uint32_t RRLVLEN3:1;
345  } bit;
346  uint32_t reg;
348 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
349 
350 #define DMAC_PRICTRL0_OFFSET 0x14
351 #define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040)
353 #define DMAC_PRICTRL0_LVLPRI0_Pos 0
354 #define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
355 #define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
356 #define DMAC_PRICTRL0_QOS0_Pos 5
357 #define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
358 #define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
359 #define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0)
360 #define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1)
361 #define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2)
362 #define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3)
363 #define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
364 #define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
365 #define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
366 #define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
367 #define DMAC_PRICTRL0_RRLVLEN0_Pos 7
368 #define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
369 #define DMAC_PRICTRL0_LVLPRI1_Pos 8
370 #define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
371 #define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
372 #define DMAC_PRICTRL0_QOS1_Pos 13
373 #define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
374 #define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
375 #define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0)
376 #define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1)
377 #define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2)
378 #define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3)
379 #define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
380 #define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
381 #define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
382 #define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
383 #define DMAC_PRICTRL0_RRLVLEN1_Pos 15
384 #define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
385 #define DMAC_PRICTRL0_LVLPRI2_Pos 16
386 #define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
387 #define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
388 #define DMAC_PRICTRL0_QOS2_Pos 21
389 #define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
390 #define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
391 #define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0)
392 #define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1)
393 #define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2)
394 #define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3)
395 #define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
396 #define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
397 #define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
398 #define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
399 #define DMAC_PRICTRL0_RRLVLEN2_Pos 23
400 #define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
401 #define DMAC_PRICTRL0_LVLPRI3_Pos 24
402 #define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
403 #define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
404 #define DMAC_PRICTRL0_QOS3_Pos 29
405 #define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
406 #define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
407 #define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0)
408 #define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1)
409 #define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2)
410 #define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3)
411 #define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
412 #define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
413 #define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
414 #define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
415 #define DMAC_PRICTRL0_RRLVLEN3_Pos 31
416 #define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
417 #define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF)
419 /* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
420 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
421 typedef union {
422  struct {
423  uint16_t ID:5;
424  uint16_t :3;
425  uint16_t TERR:1;
426  uint16_t TCMPL:1;
427  uint16_t SUSP:1;
428  uint16_t :1;
429  uint16_t CRCERR:1;
430  uint16_t FERR:1;
431  uint16_t BUSY:1;
432  uint16_t PEND:1;
433  } bit;
434  uint16_t reg;
436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
437 
438 #define DMAC_INTPEND_OFFSET 0x20
439 #define DMAC_INTPEND_RESETVALUE _U_(0x0000)
441 #define DMAC_INTPEND_ID_Pos 0
442 #define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
443 #define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
444 #define DMAC_INTPEND_TERR_Pos 8
445 #define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
446 #define DMAC_INTPEND_TCMPL_Pos 9
447 #define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
448 #define DMAC_INTPEND_SUSP_Pos 10
449 #define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
450 #define DMAC_INTPEND_CRCERR_Pos 12
451 #define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
452 #define DMAC_INTPEND_FERR_Pos 13
453 #define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
454 #define DMAC_INTPEND_BUSY_Pos 14
455 #define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
456 #define DMAC_INTPEND_PEND_Pos 15
457 #define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
458 #define DMAC_INTPEND_MASK _U_(0xF71F)
460 /* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
461 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
462 typedef union {
463  struct {
464  uint32_t CHINT0:1;
465  uint32_t CHINT1:1;
466  uint32_t CHINT2:1;
467  uint32_t CHINT3:1;
468  uint32_t CHINT4:1;
469  uint32_t CHINT5:1;
470  uint32_t CHINT6:1;
471  uint32_t CHINT7:1;
472  uint32_t CHINT8:1;
473  uint32_t CHINT9:1;
474  uint32_t CHINT10:1;
475  uint32_t CHINT11:1;
476  uint32_t CHINT12:1;
477  uint32_t CHINT13:1;
478  uint32_t CHINT14:1;
479  uint32_t CHINT15:1;
480  uint32_t CHINT16:1;
481  uint32_t CHINT17:1;
482  uint32_t CHINT18:1;
483  uint32_t CHINT19:1;
484  uint32_t CHINT20:1;
485  uint32_t CHINT21:1;
486  uint32_t CHINT22:1;
487  uint32_t CHINT23:1;
488  uint32_t CHINT24:1;
489  uint32_t CHINT25:1;
490  uint32_t CHINT26:1;
491  uint32_t CHINT27:1;
492  uint32_t CHINT28:1;
493  uint32_t CHINT29:1;
494  uint32_t CHINT30:1;
495  uint32_t CHINT31:1;
496  } bit;
497  struct {
498  uint32_t CHINT:32;
499  } vec;
500  uint32_t reg;
502 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
503 
504 #define DMAC_INTSTATUS_OFFSET 0x24
505 #define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000)
507 #define DMAC_INTSTATUS_CHINT0_Pos 0
508 #define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
509 #define DMAC_INTSTATUS_CHINT1_Pos 1
510 #define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
511 #define DMAC_INTSTATUS_CHINT2_Pos 2
512 #define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
513 #define DMAC_INTSTATUS_CHINT3_Pos 3
514 #define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
515 #define DMAC_INTSTATUS_CHINT4_Pos 4
516 #define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
517 #define DMAC_INTSTATUS_CHINT5_Pos 5
518 #define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
519 #define DMAC_INTSTATUS_CHINT6_Pos 6
520 #define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
521 #define DMAC_INTSTATUS_CHINT7_Pos 7
522 #define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
523 #define DMAC_INTSTATUS_CHINT8_Pos 8
524 #define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
525 #define DMAC_INTSTATUS_CHINT9_Pos 9
526 #define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
527 #define DMAC_INTSTATUS_CHINT10_Pos 10
528 #define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
529 #define DMAC_INTSTATUS_CHINT11_Pos 11
530 #define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
531 #define DMAC_INTSTATUS_CHINT12_Pos 12
532 #define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
533 #define DMAC_INTSTATUS_CHINT13_Pos 13
534 #define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
535 #define DMAC_INTSTATUS_CHINT14_Pos 14
536 #define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
537 #define DMAC_INTSTATUS_CHINT15_Pos 15
538 #define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
539 #define DMAC_INTSTATUS_CHINT16_Pos 16
540 #define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
541 #define DMAC_INTSTATUS_CHINT17_Pos 17
542 #define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
543 #define DMAC_INTSTATUS_CHINT18_Pos 18
544 #define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
545 #define DMAC_INTSTATUS_CHINT19_Pos 19
546 #define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
547 #define DMAC_INTSTATUS_CHINT20_Pos 20
548 #define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
549 #define DMAC_INTSTATUS_CHINT21_Pos 21
550 #define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
551 #define DMAC_INTSTATUS_CHINT22_Pos 22
552 #define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
553 #define DMAC_INTSTATUS_CHINT23_Pos 23
554 #define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
555 #define DMAC_INTSTATUS_CHINT24_Pos 24
556 #define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
557 #define DMAC_INTSTATUS_CHINT25_Pos 25
558 #define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
559 #define DMAC_INTSTATUS_CHINT26_Pos 26
560 #define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
561 #define DMAC_INTSTATUS_CHINT27_Pos 27
562 #define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
563 #define DMAC_INTSTATUS_CHINT28_Pos 28
564 #define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
565 #define DMAC_INTSTATUS_CHINT29_Pos 29
566 #define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
567 #define DMAC_INTSTATUS_CHINT30_Pos 30
568 #define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
569 #define DMAC_INTSTATUS_CHINT31_Pos 31
570 #define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
571 #define DMAC_INTSTATUS_CHINT_Pos 0
572 #define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
573 #define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
574 #define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF)
576 /* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
577 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
578 typedef union {
579  struct {
580  uint32_t BUSYCH0:1;
581  uint32_t BUSYCH1:1;
582  uint32_t BUSYCH2:1;
583  uint32_t BUSYCH3:1;
584  uint32_t BUSYCH4:1;
585  uint32_t BUSYCH5:1;
586  uint32_t BUSYCH6:1;
587  uint32_t BUSYCH7:1;
588  uint32_t BUSYCH8:1;
589  uint32_t BUSYCH9:1;
590  uint32_t BUSYCH10:1;
591  uint32_t BUSYCH11:1;
592  uint32_t BUSYCH12:1;
593  uint32_t BUSYCH13:1;
594  uint32_t BUSYCH14:1;
595  uint32_t BUSYCH15:1;
596  uint32_t BUSYCH16:1;
597  uint32_t BUSYCH17:1;
598  uint32_t BUSYCH18:1;
599  uint32_t BUSYCH19:1;
600  uint32_t BUSYCH20:1;
601  uint32_t BUSYCH21:1;
602  uint32_t BUSYCH22:1;
603  uint32_t BUSYCH23:1;
604  uint32_t BUSYCH24:1;
605  uint32_t BUSYCH25:1;
606  uint32_t BUSYCH26:1;
607  uint32_t BUSYCH27:1;
608  uint32_t BUSYCH28:1;
609  uint32_t BUSYCH29:1;
610  uint32_t BUSYCH30:1;
611  uint32_t BUSYCH31:1;
612  } bit;
613  struct {
614  uint32_t BUSYCH:32;
615  } vec;
616  uint32_t reg;
618 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
619 
620 #define DMAC_BUSYCH_OFFSET 0x28
621 #define DMAC_BUSYCH_RESETVALUE _U_(0x00000000)
623 #define DMAC_BUSYCH_BUSYCH0_Pos 0
624 #define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
625 #define DMAC_BUSYCH_BUSYCH1_Pos 1
626 #define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
627 #define DMAC_BUSYCH_BUSYCH2_Pos 2
628 #define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
629 #define DMAC_BUSYCH_BUSYCH3_Pos 3
630 #define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
631 #define DMAC_BUSYCH_BUSYCH4_Pos 4
632 #define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
633 #define DMAC_BUSYCH_BUSYCH5_Pos 5
634 #define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
635 #define DMAC_BUSYCH_BUSYCH6_Pos 6
636 #define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
637 #define DMAC_BUSYCH_BUSYCH7_Pos 7
638 #define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
639 #define DMAC_BUSYCH_BUSYCH8_Pos 8
640 #define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
641 #define DMAC_BUSYCH_BUSYCH9_Pos 9
642 #define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
643 #define DMAC_BUSYCH_BUSYCH10_Pos 10
644 #define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
645 #define DMAC_BUSYCH_BUSYCH11_Pos 11
646 #define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
647 #define DMAC_BUSYCH_BUSYCH12_Pos 12
648 #define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
649 #define DMAC_BUSYCH_BUSYCH13_Pos 13
650 #define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
651 #define DMAC_BUSYCH_BUSYCH14_Pos 14
652 #define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
653 #define DMAC_BUSYCH_BUSYCH15_Pos 15
654 #define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
655 #define DMAC_BUSYCH_BUSYCH16_Pos 16
656 #define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
657 #define DMAC_BUSYCH_BUSYCH17_Pos 17
658 #define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
659 #define DMAC_BUSYCH_BUSYCH18_Pos 18
660 #define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
661 #define DMAC_BUSYCH_BUSYCH19_Pos 19
662 #define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
663 #define DMAC_BUSYCH_BUSYCH20_Pos 20
664 #define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
665 #define DMAC_BUSYCH_BUSYCH21_Pos 21
666 #define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
667 #define DMAC_BUSYCH_BUSYCH22_Pos 22
668 #define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
669 #define DMAC_BUSYCH_BUSYCH23_Pos 23
670 #define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
671 #define DMAC_BUSYCH_BUSYCH24_Pos 24
672 #define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
673 #define DMAC_BUSYCH_BUSYCH25_Pos 25
674 #define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
675 #define DMAC_BUSYCH_BUSYCH26_Pos 26
676 #define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
677 #define DMAC_BUSYCH_BUSYCH27_Pos 27
678 #define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
679 #define DMAC_BUSYCH_BUSYCH28_Pos 28
680 #define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
681 #define DMAC_BUSYCH_BUSYCH29_Pos 29
682 #define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
683 #define DMAC_BUSYCH_BUSYCH30_Pos 30
684 #define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
685 #define DMAC_BUSYCH_BUSYCH31_Pos 31
686 #define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
687 #define DMAC_BUSYCH_BUSYCH_Pos 0
688 #define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
689 #define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
690 #define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF)
692 /* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
693 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
694 typedef union {
695  struct {
696  uint32_t PENDCH0:1;
697  uint32_t PENDCH1:1;
698  uint32_t PENDCH2:1;
699  uint32_t PENDCH3:1;
700  uint32_t PENDCH4:1;
701  uint32_t PENDCH5:1;
702  uint32_t PENDCH6:1;
703  uint32_t PENDCH7:1;
704  uint32_t PENDCH8:1;
705  uint32_t PENDCH9:1;
706  uint32_t PENDCH10:1;
707  uint32_t PENDCH11:1;
708  uint32_t PENDCH12:1;
709  uint32_t PENDCH13:1;
710  uint32_t PENDCH14:1;
711  uint32_t PENDCH15:1;
712  uint32_t PENDCH16:1;
713  uint32_t PENDCH17:1;
714  uint32_t PENDCH18:1;
715  uint32_t PENDCH19:1;
716  uint32_t PENDCH20:1;
717  uint32_t PENDCH21:1;
718  uint32_t PENDCH22:1;
719  uint32_t PENDCH23:1;
720  uint32_t PENDCH24:1;
721  uint32_t PENDCH25:1;
722  uint32_t PENDCH26:1;
723  uint32_t PENDCH27:1;
724  uint32_t PENDCH28:1;
725  uint32_t PENDCH29:1;
726  uint32_t PENDCH30:1;
727  uint32_t PENDCH31:1;
728  } bit;
729  struct {
730  uint32_t PENDCH:32;
731  } vec;
732  uint32_t reg;
734 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
735 
736 #define DMAC_PENDCH_OFFSET 0x2C
737 #define DMAC_PENDCH_RESETVALUE _U_(0x00000000)
739 #define DMAC_PENDCH_PENDCH0_Pos 0
740 #define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
741 #define DMAC_PENDCH_PENDCH1_Pos 1
742 #define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
743 #define DMAC_PENDCH_PENDCH2_Pos 2
744 #define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
745 #define DMAC_PENDCH_PENDCH3_Pos 3
746 #define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
747 #define DMAC_PENDCH_PENDCH4_Pos 4
748 #define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
749 #define DMAC_PENDCH_PENDCH5_Pos 5
750 #define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
751 #define DMAC_PENDCH_PENDCH6_Pos 6
752 #define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
753 #define DMAC_PENDCH_PENDCH7_Pos 7
754 #define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
755 #define DMAC_PENDCH_PENDCH8_Pos 8
756 #define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
757 #define DMAC_PENDCH_PENDCH9_Pos 9
758 #define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
759 #define DMAC_PENDCH_PENDCH10_Pos 10
760 #define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
761 #define DMAC_PENDCH_PENDCH11_Pos 11
762 #define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
763 #define DMAC_PENDCH_PENDCH12_Pos 12
764 #define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
765 #define DMAC_PENDCH_PENDCH13_Pos 13
766 #define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
767 #define DMAC_PENDCH_PENDCH14_Pos 14
768 #define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
769 #define DMAC_PENDCH_PENDCH15_Pos 15
770 #define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
771 #define DMAC_PENDCH_PENDCH16_Pos 16
772 #define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
773 #define DMAC_PENDCH_PENDCH17_Pos 17
774 #define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
775 #define DMAC_PENDCH_PENDCH18_Pos 18
776 #define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
777 #define DMAC_PENDCH_PENDCH19_Pos 19
778 #define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
779 #define DMAC_PENDCH_PENDCH20_Pos 20
780 #define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
781 #define DMAC_PENDCH_PENDCH21_Pos 21
782 #define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
783 #define DMAC_PENDCH_PENDCH22_Pos 22
784 #define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
785 #define DMAC_PENDCH_PENDCH23_Pos 23
786 #define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
787 #define DMAC_PENDCH_PENDCH24_Pos 24
788 #define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
789 #define DMAC_PENDCH_PENDCH25_Pos 25
790 #define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
791 #define DMAC_PENDCH_PENDCH26_Pos 26
792 #define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
793 #define DMAC_PENDCH_PENDCH27_Pos 27
794 #define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
795 #define DMAC_PENDCH_PENDCH28_Pos 28
796 #define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
797 #define DMAC_PENDCH_PENDCH29_Pos 29
798 #define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
799 #define DMAC_PENDCH_PENDCH30_Pos 30
800 #define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
801 #define DMAC_PENDCH_PENDCH31_Pos 31
802 #define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
803 #define DMAC_PENDCH_PENDCH_Pos 0
804 #define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
805 #define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
806 #define DMAC_PENDCH_MASK _U_(0xFFFFFFFF)
808 /* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
809 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
810 typedef union {
811  struct {
812  uint32_t LVLEX0:1;
813  uint32_t LVLEX1:1;
814  uint32_t LVLEX2:1;
815  uint32_t LVLEX3:1;
816  uint32_t :4;
817  uint32_t ID:5;
818  uint32_t :2;
819  uint32_t ABUSY:1;
820  uint32_t BTCNT:16;
821  } bit;
822  struct {
823  uint32_t LVLEX:4;
824  uint32_t :28;
825  } vec;
826  uint32_t reg;
828 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
829 
830 #define DMAC_ACTIVE_OFFSET 0x30
831 #define DMAC_ACTIVE_RESETVALUE _U_(0x00000000)
833 #define DMAC_ACTIVE_LVLEX0_Pos 0
834 #define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
835 #define DMAC_ACTIVE_LVLEX1_Pos 1
836 #define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
837 #define DMAC_ACTIVE_LVLEX2_Pos 2
838 #define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
839 #define DMAC_ACTIVE_LVLEX3_Pos 3
840 #define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
841 #define DMAC_ACTIVE_LVLEX_Pos 0
842 #define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
843 #define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
844 #define DMAC_ACTIVE_ID_Pos 8
845 #define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
846 #define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
847 #define DMAC_ACTIVE_ABUSY_Pos 15
848 #define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
849 #define DMAC_ACTIVE_BTCNT_Pos 16
850 #define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
851 #define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
852 #define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F)
854 /* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
855 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
856 typedef union {
857  struct {
858  uint32_t BASEADDR:32;
859  } bit;
860  uint32_t reg;
862 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
863 
864 #define DMAC_BASEADDR_OFFSET 0x34
865 #define DMAC_BASEADDR_RESETVALUE _U_(0x00000000)
867 #define DMAC_BASEADDR_BASEADDR_Pos 0
868 #define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
869 #define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
870 #define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF)
872 /* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
873 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
874 typedef union {
875  struct {
876  uint32_t WRBADDR:32;
877  } bit;
878  uint32_t reg;
880 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
881 
882 #define DMAC_WRBADDR_OFFSET 0x38
883 #define DMAC_WRBADDR_RESETVALUE _U_(0x00000000)
885 #define DMAC_WRBADDR_WRBADDR_Pos 0
886 #define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
887 #define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
888 #define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF)
890 /* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */
891 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
892 typedef union {
893  struct {
894  uint32_t SWRST:1;
895  uint32_t ENABLE:1;
896  uint32_t :4;
897  uint32_t RUNSTDBY:1;
898  uint32_t :1;
899  uint32_t TRIGSRC:7;
900  uint32_t :5;
901  uint32_t TRIGACT:2;
902  uint32_t :2;
903  uint32_t BURSTLEN:4;
904  uint32_t THRESHOLD:2;
905  uint32_t :2;
906  } bit;
907  uint32_t reg;
909 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
910 
911 #define DMAC_CHCTRLA_OFFSET 0x40
912 #define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000)
914 #define DMAC_CHCTRLA_SWRST_Pos 0
915 #define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
916 #define DMAC_CHCTRLA_ENABLE_Pos 1
917 #define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
918 #define DMAC_CHCTRLA_RUNSTDBY_Pos 6
919 #define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
920 #define DMAC_CHCTRLA_TRIGSRC_Pos 8
921 #define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
922 #define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
923 #define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0)
924 #define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
925 #define DMAC_CHCTRLA_TRIGACT_Pos 20
926 #define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
927 #define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
928 #define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0)
929 #define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2)
930 #define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3)
931 #define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
932 #define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
933 #define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
934 #define DMAC_CHCTRLA_BURSTLEN_Pos 24
935 #define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
936 #define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
937 #define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0)
938 #define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1)
939 #define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2)
940 #define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3)
941 #define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4)
942 #define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5)
943 #define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6)
944 #define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7)
945 #define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8)
946 #define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9)
947 #define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA)
948 #define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB)
949 #define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC)
950 #define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD)
951 #define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE)
952 #define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF)
953 #define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
954 #define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
955 #define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
956 #define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
957 #define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
958 #define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
959 #define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
960 #define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
961 #define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
962 #define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
963 #define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
964 #define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
965 #define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
966 #define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
967 #define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
968 #define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
969 #define DMAC_CHCTRLA_THRESHOLD_Pos 28
970 #define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
971 #define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
972 #define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0)
973 #define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1)
974 #define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2)
975 #define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3)
976 #define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
977 #define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
978 #define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
979 #define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
980 #define DMAC_CHCTRLA_MASK _U_(0x3F307F43)
982 /* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */
983 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
984 typedef union {
985  struct {
986  uint8_t CMD:2;
987  uint8_t :6;
988  } bit;
989  uint8_t reg;
991 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
992 
993 #define DMAC_CHCTRLB_OFFSET 0x44
994 #define DMAC_CHCTRLB_RESETVALUE _U_(0x00)
996 #define DMAC_CHCTRLB_CMD_Pos 0
997 #define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
998 #define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
999 #define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0)
1000 #define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1)
1001 #define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2)
1002 #define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
1003 #define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
1004 #define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
1005 #define DMAC_CHCTRLB_MASK _U_(0x03)
1007 /* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */
1008 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1009 typedef union {
1010  struct {
1011  uint8_t PRILVL:2;
1012  uint8_t :6;
1013  } bit;
1014  uint8_t reg;
1016 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1017 
1018 #define DMAC_CHPRILVL_OFFSET 0x45
1019 #define DMAC_CHPRILVL_RESETVALUE _U_(0x00)
1021 #define DMAC_CHPRILVL_PRILVL_Pos 0
1022 #define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
1023 #define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
1024 #define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0)
1025 #define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1)
1026 #define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2)
1027 #define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3)
1028 #define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4)
1029 #define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5)
1030 #define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6)
1031 #define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7)
1032 #define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
1033 #define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
1034 #define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
1035 #define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
1036 #define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
1037 #define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
1038 #define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
1039 #define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
1040 #define DMAC_CHPRILVL_MASK _U_(0x03)
1042 /* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */
1043 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1044 typedef union {
1045  struct {
1046  uint8_t EVACT:3;
1047  uint8_t :1;
1048  uint8_t EVOMODE:2;
1049  uint8_t EVIE:1;
1050  uint8_t EVOE:1;
1051  } bit;
1052  uint8_t reg;
1054 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1055 
1056 #define DMAC_CHEVCTRL_OFFSET 0x46
1057 #define DMAC_CHEVCTRL_RESETVALUE _U_(0x00)
1059 #define DMAC_CHEVCTRL_EVACT_Pos 0
1060 #define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
1061 #define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
1062 #define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0)
1063 #define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1)
1064 #define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2)
1065 #define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3)
1066 #define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4)
1067 #define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5)
1068 #define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6)
1069 #define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7)
1070 #define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
1071 #define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
1072 #define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
1073 #define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
1074 #define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
1075 #define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
1076 #define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
1077 #define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
1078 #define DMAC_CHEVCTRL_EVOMODE_Pos 4
1079 #define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
1080 #define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
1081 #define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0)
1082 #define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1)
1083 #define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
1084 #define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
1085 #define DMAC_CHEVCTRL_EVIE_Pos 6
1086 #define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
1087 #define DMAC_CHEVCTRL_EVOE_Pos 7
1088 #define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
1089 #define DMAC_CHEVCTRL_MASK _U_(0xF7)
1091 /* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
1092 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1093 typedef union {
1094  struct {
1095  uint8_t TERR:1;
1096  uint8_t TCMPL:1;
1097  uint8_t SUSP:1;
1098  uint8_t :5;
1099  } bit;
1100  uint8_t reg;
1102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1103 
1104 #define DMAC_CHINTENCLR_OFFSET 0x4C
1105 #define DMAC_CHINTENCLR_RESETVALUE _U_(0x00)
1107 #define DMAC_CHINTENCLR_TERR_Pos 0
1108 #define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
1109 #define DMAC_CHINTENCLR_TCMPL_Pos 1
1110 #define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
1111 #define DMAC_CHINTENCLR_SUSP_Pos 2
1112 #define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
1113 #define DMAC_CHINTENCLR_MASK _U_(0x07)
1115 /* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
1116 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1117 typedef union {
1118  struct {
1119  uint8_t TERR:1;
1120  uint8_t TCMPL:1;
1121  uint8_t SUSP:1;
1122  uint8_t :5;
1123  } bit;
1124  uint8_t reg;
1126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1127 
1128 #define DMAC_CHINTENSET_OFFSET 0x4D
1129 #define DMAC_CHINTENSET_RESETVALUE _U_(0x00)
1131 #define DMAC_CHINTENSET_TERR_Pos 0
1132 #define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
1133 #define DMAC_CHINTENSET_TCMPL_Pos 1
1134 #define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
1135 #define DMAC_CHINTENSET_SUSP_Pos 2
1136 #define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
1137 #define DMAC_CHINTENSET_MASK _U_(0x07)
1139 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
1140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1141 typedef union { // __I to avoid read-modify-write on write-to-clear register
1142  struct {
1143  __I uint8_t TERR:1;
1144  __I uint8_t TCMPL:1;
1145  __I uint8_t SUSP:1;
1146  __I uint8_t :5;
1147  } bit;
1148  uint8_t reg;
1150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1151 
1152 #define DMAC_CHINTFLAG_OFFSET 0x4E
1153 #define DMAC_CHINTFLAG_RESETVALUE _U_(0x00)
1155 #define DMAC_CHINTFLAG_TERR_Pos 0
1156 #define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
1157 #define DMAC_CHINTFLAG_TCMPL_Pos 1
1158 #define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
1159 #define DMAC_CHINTFLAG_SUSP_Pos 2
1160 #define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
1161 #define DMAC_CHINTFLAG_MASK _U_(0x07)
1163 /* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */
1164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1165 typedef union {
1166  struct {
1167  uint8_t PEND:1;
1168  uint8_t BUSY:1;
1169  uint8_t FERR:1;
1170  uint8_t CRCERR:1;
1171  uint8_t :4;
1172  } bit;
1173  uint8_t reg;
1175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1176 
1177 #define DMAC_CHSTATUS_OFFSET 0x4F
1178 #define DMAC_CHSTATUS_RESETVALUE _U_(0x00)
1180 #define DMAC_CHSTATUS_PEND_Pos 0
1181 #define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
1182 #define DMAC_CHSTATUS_BUSY_Pos 1
1183 #define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
1184 #define DMAC_CHSTATUS_FERR_Pos 2
1185 #define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
1186 #define DMAC_CHSTATUS_CRCERR_Pos 3
1187 #define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
1188 #define DMAC_CHSTATUS_MASK _U_(0x0F)
1190 /* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
1191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1192 typedef union {
1193  struct {
1194  uint16_t VALID:1;
1195  uint16_t EVOSEL:2;
1196  uint16_t BLOCKACT:2;
1197  uint16_t :3;
1198  uint16_t BEATSIZE:2;
1199  uint16_t SRCINC:1;
1200  uint16_t DSTINC:1;
1201  uint16_t STEPSEL:1;
1202  uint16_t STEPSIZE:3;
1203  } bit;
1204  uint16_t reg;
1206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1207 
1208 #define DMAC_BTCTRL_OFFSET 0x00
1209 #define DMAC_BTCTRL_RESETVALUE _U_(0x0000)
1211 #define DMAC_BTCTRL_VALID_Pos 0
1212 #define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
1213 #define DMAC_BTCTRL_EVOSEL_Pos 1
1214 #define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
1215 #define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
1216 #define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0)
1217 #define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1)
1218 #define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3)
1219 #define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
1220 #define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
1221 #define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos)
1222 #define DMAC_BTCTRL_BLOCKACT_Pos 3
1223 #define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
1224 #define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
1225 #define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0)
1226 #define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1)
1227 #define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2)
1228 #define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3)
1229 #define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
1230 #define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
1231 #define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
1232 #define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
1233 #define DMAC_BTCTRL_BEATSIZE_Pos 8
1234 #define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
1235 #define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
1236 #define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0)
1237 #define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1)
1238 #define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2)
1239 #define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
1240 #define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
1241 #define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
1242 #define DMAC_BTCTRL_SRCINC_Pos 10
1243 #define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
1244 #define DMAC_BTCTRL_DSTINC_Pos 11
1245 #define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
1246 #define DMAC_BTCTRL_STEPSEL_Pos 12
1247 #define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
1248 #define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0)
1249 #define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1)
1250 #define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
1251 #define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
1252 #define DMAC_BTCTRL_STEPSIZE_Pos 13
1253 #define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
1254 #define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
1255 #define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0)
1256 #define DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1)
1257 #define DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2)
1258 #define DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3)
1259 #define DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4)
1260 #define DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5)
1261 #define DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6)
1262 #define DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7)
1263 #define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1264 #define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1265 #define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1266 #define DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1267 #define DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1268 #define DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1269 #define DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1270 #define DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
1271 #define DMAC_BTCTRL_MASK _U_(0xFF1F)
1273 /* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
1274 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1275 typedef union {
1276  struct {
1277  uint16_t BTCNT:16;
1278  } bit;
1279  uint16_t reg;
1280 } DMAC_BTCNT_Type;
1281 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1282 
1283 #define DMAC_BTCNT_OFFSET 0x02
1284 #define DMAC_BTCNT_RESETVALUE _U_(0x0000)
1286 #define DMAC_BTCNT_BTCNT_Pos 0
1287 #define DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
1288 #define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
1289 #define DMAC_BTCNT_MASK _U_(0xFFFF)
1291 /* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
1292 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1293 typedef union {
1294  struct {
1295  uint32_t SRCADDR:32;
1296  } bit;
1297  uint32_t reg;
1299 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1300 
1301 #define DMAC_SRCADDR_OFFSET 0x04
1302 #define DMAC_SRCADDR_RESETVALUE _U_(0x00000000)
1304 #define DMAC_SRCADDR_SRCADDR_Pos 0
1305 #define DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
1306 #define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
1307 #define DMAC_SRCADDR_MASK _U_(0xFFFFFFFF)
1309 /* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
1310 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1311 typedef union {
1312  struct { // CRC mode
1313  uint32_t CHKINIT:32;
1314  } CRC;
1315  struct {
1316  uint32_t DSTADDR:32;
1317  } bit;
1318  uint32_t reg;
1320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1321 
1322 #define DMAC_DSTADDR_OFFSET 0x08
1324 // CRC mode
1325 #define DMAC_DSTADDR_CRC_CHKINIT_Pos 0
1326 #define DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
1327 #define DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
1328 #define DMAC_DSTADDR_CRC_MASK _U_(0xFFFFFFFF)
1330 #define DMAC_DSTADDR_DSTADDR_Pos 0
1331 #define DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
1332 #define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
1333 #define DMAC_DSTADDR_MASK _U_(0xFFFFFFFF)
1335 /* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
1336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1337 typedef union {
1338  struct {
1339  uint32_t DESCADDR:32;
1340  } bit;
1341  uint32_t reg;
1343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1344 
1345 #define DMAC_DESCADDR_OFFSET 0x0C
1347 #define DMAC_DESCADDR_DESCADDR_Pos 0
1348 #define DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
1349 #define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
1350 #define DMAC_DESCADDR_MASK _U_(0xFFFFFFFF)
1353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1354 typedef struct {
1359  RoReg8 Reserved1[0x5];
1364 } DmacChannel;
1365 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1366 
1368 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1369 typedef struct {
1376  RoReg8 Reserved1[0x2];
1379  RoReg8 Reserved2[0x8];
1381  RoReg8 Reserved3[0x2];
1388  RoReg8 Reserved4[0x4];
1389  DmacChannel Channel[32];
1390 } Dmac;
1391 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1392 
1394 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1395 typedef struct {
1402 #ifdef __GNUC__
1403  __attribute__ ((aligned (8)))
1404 #endif
1405 ;
1406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1407 
1408 #ifdef __GNUC__
1409  #define SECTION_DMAC_DESCRIPTOR __attribute__ ((section(".hsram")))
1410 #elif defined(__ICCARM__)
1411  #define SECTION_DMAC_DESCRIPTOR @".hsram"
1412 #endif
1413 
1416 #endif /* _SAME54_DMAC_COMPONENT_ */
Dmac::INTSTATUS
__I DMAC_INTSTATUS_Type INTSTATUS
Offset: 0x24 (R/ 32) Interrupt Status.
Definition: dmac.h:1382
DMAC_CHINTENSET_Type::TERR
uint8_t TERR
Definition: dmac.h:1119
DMAC_CTRL_Type
Definition: dmac.h:44
DMAC_BUSYCH_Type::BUSYCH2
uint32_t BUSYCH2
Definition: dmac.h:582
DMAC_PRICTRL0_Type::RRLVLEN0
uint32_t RRLVLEN0
Definition: dmac.h:335
DMAC_SWTRIGCTRL_Type::SWTRIG28
uint32_t SWTRIG28
Definition: dmac.h:245
DMAC_INTPEND_Type::ID
uint16_t ID
Definition: dmac.h:423
DmacDescriptor
DMAC Descriptor SRAM registers.
Definition: dmac.h:1395
DMAC_SWTRIGCTRL_Type::SWTRIG29
uint32_t SWTRIG29
Definition: dmac.h:246
DMAC_CHCTRLA_Type
Definition: dmac.h:892
DMAC_PENDCH_Type::PENDCH7
uint32_t PENDCH7
Definition: dmac.h:703
DMAC_PENDCH_Type::PENDCH21
uint32_t PENDCH21
Definition: dmac.h:717
DmacChannel::CHEVCTRL
__IO DMAC_CHEVCTRL_Type CHEVCTRL
Offset: 0x06 (R/W 8) Channel n Event Control.
Definition: dmac.h:1358
DMAC_BUSYCH_Type::BUSYCH20
uint32_t BUSYCH20
Definition: dmac.h:600
DmacChannel::CHCTRLA
__IO DMAC_CHCTRLA_Type CHCTRLA
Offset: 0x00 (R/W 32) Channel n Control A.
Definition: dmac.h:1355
DMAC_INTSTATUS_Type::CHINT23
uint32_t CHINT23
Definition: dmac.h:487
DMAC_INTPEND_Type::BUSY
uint16_t BUSY
Definition: dmac.h:431
DMAC_CHCTRLB_Type::reg
uint8_t reg
Definition: dmac.h:989
DMAC_INTPEND_Type
Definition: dmac.h:421
DMAC_SWTRIGCTRL_Type::SWTRIG26
uint32_t SWTRIG26
Definition: dmac.h:243
DMAC_SWTRIGCTRL_Type::SWTRIG27
uint32_t SWTRIG27
Definition: dmac.h:244
DMAC_SWTRIGCTRL_Type::SWTRIG6
uint32_t SWTRIG6
Definition: dmac.h:223
DMAC_CHINTENCLR_Type::TERR
uint8_t TERR
Definition: dmac.h:1095
DMAC_CHPRILVL_Type::reg
uint8_t reg
Definition: dmac.h:1014
Dmac::PRICTRL0
__IO DMAC_PRICTRL0_Type PRICTRL0
Offset: 0x14 (R/W 32) Priority Control 0.
Definition: dmac.h:1378
DMAC_PRICTRL0_Type::RRLVLEN3
uint32_t RRLVLEN3
Definition: dmac.h:344
DMAC_ACTIVE_Type::ABUSY
uint32_t ABUSY
Definition: dmac.h:819
DMAC_CRCDATAIN_Type::CRCDATAIN
uint32_t CRCDATAIN
Definition: dmac.h:139
DMAC_PRICTRL0_Type::QOS2
uint32_t QOS2
Definition: dmac.h:340
DMAC_PENDCH_Type::PENDCH18
uint32_t PENDCH18
Definition: dmac.h:714
DMAC_SWTRIGCTRL_Type::SWTRIG20
uint32_t SWTRIG20
Definition: dmac.h:237
DMAC_SWTRIGCTRL_Type::SWTRIG24
uint32_t SWTRIG24
Definition: dmac.h:241
DMAC_BUSYCH_Type::BUSYCH12
uint32_t BUSYCH12
Definition: dmac.h:592
Dmac::ACTIVE
__I DMAC_ACTIVE_Type ACTIVE
Offset: 0x30 (R/ 32) Active Channel and Levels.
Definition: dmac.h:1385
DMAC_SWTRIGCTRL_Type::SWTRIG0
uint32_t SWTRIG0
Definition: dmac.h:217
DMAC_CRCSTATUS_Type::CRCZERO
uint8_t CRCZERO
Definition: dmac.h:176
DMAC_CHINTENSET_Type::reg
uint8_t reg
Definition: dmac.h:1124
DMAC_BTCTRL_Type::EVOSEL
uint16_t EVOSEL
Definition: dmac.h:1195
DMAC_INTSTATUS_Type::CHINT27
uint32_t CHINT27
Definition: dmac.h:491
Dmac::BASEADDR
__IO DMAC_BASEADDR_Type BASEADDR
Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address.
Definition: dmac.h:1386
DMAC_INTSTATUS_Type::CHINT17
uint32_t CHINT17
Definition: dmac.h:481
DMAC_INTSTATUS_Type::CHINT11
uint32_t CHINT11
Definition: dmac.h:475
DMAC_INTSTATUS_Type::CHINT14
uint32_t CHINT14
Definition: dmac.h:478
DMAC_SWTRIGCTRL_Type::SWTRIG11
uint32_t SWTRIG11
Definition: dmac.h:228
DMAC_BTCNT_Type
Definition: dmac.h:1275
DMAC_ACTIVE_Type::LVLEX
uint32_t LVLEX
Definition: dmac.h:823
DmacChannel::CHPRILVL
__IO DMAC_CHPRILVL_Type CHPRILVL
Offset: 0x05 (R/W 8) Channel n Priority Level.
Definition: dmac.h:1357
DMAC_CHPRILVL_Type::PRILVL
uint8_t PRILVL
Definition: dmac.h:1011
DMAC_CHINTENSET_Type
Definition: dmac.h:1117
DMAC_CHCTRLA_Type::SWRST
uint32_t SWRST
Definition: dmac.h:894
DMAC_INTSTATUS_Type::CHINT3
uint32_t CHINT3
Definition: dmac.h:467
Dmac::WRBADDR
__IO DMAC_WRBADDR_Type WRBADDR
Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address.
Definition: dmac.h:1387
DMAC_PENDCH_Type::PENDCH24
uint32_t PENDCH24
Definition: dmac.h:720
DMAC_PENDCH_Type::PENDCH27
uint32_t PENDCH27
Definition: dmac.h:723
DMAC_SWTRIGCTRL_Type::SWTRIG13
uint32_t SWTRIG13
Definition: dmac.h:230
DMAC_DESCADDR_Type::reg
uint32_t reg
Definition: dmac.h:1341
DMAC_CHINTFLAG_Type::TCMPL
__I uint8_t TCMPL
Definition: dmac.h:1144
Dmac
DMAC APB hardware registers.
Definition: dmac.h:1369
DMAC_CTRL_Type::LVLEN0
uint16_t LVLEN0
Definition: dmac.h:49
DMAC_BUSYCH_Type::BUSYCH25
uint32_t BUSYCH25
Definition: dmac.h:605
Dmac::INTPEND
__IO DMAC_INTPEND_Type INTPEND
Offset: 0x20 (R/W 16) Interrupt Pending.
Definition: dmac.h:1380
DmacChannel::CHCTRLB
__IO DMAC_CHCTRLB_Type CHCTRLB
Offset: 0x04 (R/W 8) Channel n Control B.
Definition: dmac.h:1356
DMAC_PRICTRL0_Type::QOS1
uint32_t QOS1
Definition: dmac.h:337
DMAC_SWTRIGCTRL_Type::SWTRIG15
uint32_t SWTRIG15
Definition: dmac.h:232
DMAC_BUSYCH_Type::BUSYCH31
uint32_t BUSYCH31
Definition: dmac.h:611
DMAC_BUSYCH_Type::BUSYCH26
uint32_t BUSYCH26
Definition: dmac.h:606
DMAC_PRICTRL0_Type::LVLPRI1
uint32_t LVLPRI1
Definition: dmac.h:336
Dmac::CRCSTATUS
__IO DMAC_CRCSTATUS_Type CRCSTATUS
Offset: 0x0C (R/W 8) CRC Status.
Definition: dmac.h:1374
DMAC_CHINTENCLR_Type::SUSP
uint8_t SUSP
Definition: dmac.h:1097
DMAC_CHINTFLAG_Type::uint8_t
__I uint8_t
Definition: dmac.h:1146
DMAC_PENDCH_Type::PENDCH30
uint32_t PENDCH30
Definition: dmac.h:726
DMAC_BUSYCH_Type
Definition: dmac.h:578
DMAC_DESCADDR_Type::DESCADDR
uint32_t DESCADDR
Definition: dmac.h:1339
DMAC_BUSYCH_Type::BUSYCH18
uint32_t BUSYCH18
Definition: dmac.h:598
DMAC_PENDCH_Type::PENDCH16
uint32_t PENDCH16
Definition: dmac.h:712
DMAC_PENDCH_Type::PENDCH25
uint32_t PENDCH25
Definition: dmac.h:721
DMAC_CHSTATUS_Type
Definition: dmac.h:1165
DmacChannel::CHINTENCLR
__IO DMAC_CHINTENCLR_Type CHINTENCLR
Offset: 0x0C (R/W 8) Channel n Interrupt Enable Clear.
Definition: dmac.h:1360
DMAC_SWTRIGCTRL_Type::SWTRIG30
uint32_t SWTRIG30
Definition: dmac.h:247
DMAC_PENDCH_Type::PENDCH3
uint32_t PENDCH3
Definition: dmac.h:699
Dmac::BUSYCH
__I DMAC_BUSYCH_Type BUSYCH
Offset: 0x28 (R/ 32) Busy Channels.
Definition: dmac.h:1383
DMAC_BUSYCH_Type::BUSYCH13
uint32_t BUSYCH13
Definition: dmac.h:593
DMAC_PENDCH_Type::PENDCH28
uint32_t PENDCH28
Definition: dmac.h:724
DMAC_CTRL_Type::LVLEN1
uint16_t LVLEN1
Definition: dmac.h:50
DMAC_INTSTATUS_Type::CHINT4
uint32_t CHINT4
Definition: dmac.h:468
DMAC_BUSYCH_Type::BUSYCH15
uint32_t BUSYCH15
Definition: dmac.h:595
DMAC_BUSYCH_Type::BUSYCH22
uint32_t BUSYCH22
Definition: dmac.h:602
DmacDescriptor::DESCADDR
__IO DMAC_DESCADDR_Type DESCADDR
Offset: 0x0C (R/W 32) Next Descriptor Address.
Definition: dmac.h:1400
DMAC_ACTIVE_Type::LVLEX3
uint32_t LVLEX3
Definition: dmac.h:815
DMAC_BUSYCH_Type::BUSYCH16
uint32_t BUSYCH16
Definition: dmac.h:596
DMAC_BUSYCH_Type::BUSYCH0
uint32_t BUSYCH0
Definition: dmac.h:580
DMAC_CHEVCTRL_Type
Definition: dmac.h:1044
DMAC_CTRL_Type::LVLEN
uint16_t LVLEN
Definition: dmac.h:57
DMAC_CRCCHKSUM_Type::reg
uint32_t reg
Definition: dmac.h:159
DMAC_DBGCTRL_Type::DBGRUN
uint8_t DBGRUN
Definition: dmac.h:199
DMAC_ACTIVE_Type::reg
uint32_t reg
Definition: dmac.h:826
DMAC_PENDCH_Type::PENDCH
uint32_t PENDCH
Definition: dmac.h:730
DMAC_BTCNT_Type::reg
uint16_t reg
Definition: dmac.h:1279
DMAC_SWTRIGCTRL_Type::SWTRIG31
uint32_t SWTRIG31
Definition: dmac.h:248
DMAC_CHINTFLAG_Type::reg
uint8_t reg
Definition: dmac.h:1148
DMAC_INTSTATUS_Type::reg
uint32_t reg
Definition: dmac.h:500
DMAC_ACTIVE_Type::LVLEX1
uint32_t LVLEX1
Definition: dmac.h:813
DMAC_INTSTATUS_Type::CHINT20
uint32_t CHINT20
Definition: dmac.h:484
DMAC_SWTRIGCTRL_Type::SWTRIG4
uint32_t SWTRIG4
Definition: dmac.h:221
DMAC_CHCTRLA_Type::THRESHOLD
uint32_t THRESHOLD
Definition: dmac.h:904
DMAC_BTCTRL_Type
Definition: dmac.h:1192
DMAC_BUSYCH_Type::BUSYCH30
uint32_t BUSYCH30
Definition: dmac.h:610
DMAC_CRCSTATUS_Type::CRCBUSY
uint8_t CRCBUSY
Definition: dmac.h:175
DMAC_PRICTRL0_Type
Definition: dmac.h:331
DMAC_CRCDATAIN_Type::reg
uint32_t reg
Definition: dmac.h:141
DMAC_SWTRIGCTRL_Type::SWTRIG18
uint32_t SWTRIG18
Definition: dmac.h:235
DMAC_BUSYCH_Type::BUSYCH8
uint32_t BUSYCH8
Definition: dmac.h:588
DMAC_INTPEND_Type::FERR
uint16_t FERR
Definition: dmac.h:430
DMAC_BUSYCH_Type::BUSYCH24
uint32_t BUSYCH24
Definition: dmac.h:604
DMAC_BTCTRL_Type::STEPSEL
uint16_t STEPSEL
Definition: dmac.h:1201
DMAC_INTSTATUS_Type::CHINT10
uint32_t CHINT10
Definition: dmac.h:474
DMAC_BUSYCH_Type::BUSYCH21
uint32_t BUSYCH21
Definition: dmac.h:601
DMAC_PRICTRL0_Type::LVLPRI0
uint32_t LVLPRI0
Definition: dmac.h:333
DMAC_BUSYCH_Type::BUSYCH6
uint32_t BUSYCH6
Definition: dmac.h:586
DMAC_DSTADDR_Type::CHKINIT
uint32_t CHKINIT
Definition: dmac.h:1313
DMAC_DESCADDR_Type
Definition: dmac.h:1337
DMAC_INTSTATUS_Type::CHINT26
uint32_t CHINT26
Definition: dmac.h:490
DMAC_ACTIVE_Type
Definition: dmac.h:810
DMAC_CHCTRLA_Type::TRIGSRC
uint32_t TRIGSRC
Definition: dmac.h:899
DMAC_BTCNT_Type::BTCNT
uint16_t BTCNT
Definition: dmac.h:1277
DMAC_SWTRIGCTRL_Type::SWTRIG8
uint32_t SWTRIG8
Definition: dmac.h:225
DMAC_ACTIVE_Type::LVLEX0
uint32_t LVLEX0
Definition: dmac.h:812
DMAC_CHINTENCLR_Type::TCMPL
uint8_t TCMPL
Definition: dmac.h:1096
DMAC_CRCCTRL_Type::reg
uint16_t reg
Definition: dmac.h:94
DMAC_PENDCH_Type::PENDCH19
uint32_t PENDCH19
Definition: dmac.h:715
DmacDescriptor::BTCNT
__IO DMAC_BTCNT_Type BTCNT
Offset: 0x02 (R/W 16) Block Transfer Count.
Definition: dmac.h:1397
DMAC_PENDCH_Type::PENDCH8
uint32_t PENDCH8
Definition: dmac.h:704
DmacChannel::CHINTFLAG
__IO DMAC_CHINTFLAG_Type CHINTFLAG
Offset: 0x0E (R/W 8) Channel n Interrupt Flag Status and Clear.
Definition: dmac.h:1362
DMAC_CHSTATUS_Type::BUSY
uint8_t BUSY
Definition: dmac.h:1168
DMAC_SWTRIGCTRL_Type::SWTRIG19
uint32_t SWTRIG19
Definition: dmac.h:236
DMAC_CHCTRLB_Type::CMD
uint8_t CMD
Definition: dmac.h:986
DMAC_CTRL_Type::SWRST
uint16_t SWRST
Definition: dmac.h:46
DMAC_CHSTATUS_Type::CRCERR
uint8_t CRCERR
Definition: dmac.h:1170
DMAC_PRICTRL0_Type::LVLPRI3
uint32_t LVLPRI3
Definition: dmac.h:342
DMAC_INTSTATUS_Type::CHINT7
uint32_t CHINT7
Definition: dmac.h:471
DMAC_BUSYCH_Type::BUSYCH28
uint32_t BUSYCH28
Definition: dmac.h:608
DMAC_SWTRIGCTRL_Type::SWTRIG1
uint32_t SWTRIG1
Definition: dmac.h:218
DmacDescriptor::SRCADDR
__IO DMAC_SRCADDR_Type SRCADDR
Offset: 0x04 (R/W 32) Block Transfer Source Address.
Definition: dmac.h:1398
DMAC_BUSYCH_Type::BUSYCH27
uint32_t BUSYCH27
Definition: dmac.h:607
Dmac::DBGCTRL
__IO DMAC_DBGCTRL_Type DBGCTRL
Offset: 0x0D (R/W 8) Debug Control.
Definition: dmac.h:1375
DMAC_CTRL_Type::DMAENABLE
uint16_t DMAENABLE
Definition: dmac.h:47
DMAC_BUSYCH_Type::BUSYCH11
uint32_t BUSYCH11
Definition: dmac.h:591
DMAC_CHINTENSET_Type::TCMPL
uint8_t TCMPL
Definition: dmac.h:1120
DMAC_ACTIVE_Type::LVLEX2
uint32_t LVLEX2
Definition: dmac.h:814
DMAC_INTSTATUS_Type::CHINT1
uint32_t CHINT1
Definition: dmac.h:465
DMAC_CHCTRLA_Type::TRIGACT
uint32_t TRIGACT
Definition: dmac.h:901
DMAC_SWTRIGCTRL_Type::SWTRIG14
uint32_t SWTRIG14
Definition: dmac.h:231
DMAC_PENDCH_Type::PENDCH12
uint32_t PENDCH12
Definition: dmac.h:708
DMAC_INTSTATUS_Type::CHINT
uint32_t CHINT
Definition: dmac.h:498
DMAC_BTCTRL_Type::DSTINC
uint16_t DSTINC
Definition: dmac.h:1200
DMAC_INTSTATUS_Type::CHINT28
uint32_t CHINT28
Definition: dmac.h:492
DMAC_BUSYCH_Type::BUSYCH4
uint32_t BUSYCH4
Definition: dmac.h:584
DMAC_BTCTRL_Type::VALID
uint16_t VALID
Definition: dmac.h:1194
DMAC_BASEADDR_Type::BASEADDR
uint32_t BASEADDR
Definition: dmac.h:858
DMAC_INTSTATUS_Type::CHINT13
uint32_t CHINT13
Definition: dmac.h:477
DMAC_CRCCTRL_Type::CRCMODE
uint16_t CRCMODE
Definition: dmac.h:92
DMAC_PRICTRL0_Type::LVLPRI2
uint32_t LVLPRI2
Definition: dmac.h:339
DMAC_INTSTATUS_Type::CHINT30
uint32_t CHINT30
Definition: dmac.h:494
DMAC_CRCCHKSUM_Type::CRCCHKSUM
uint32_t CRCCHKSUM
Definition: dmac.h:157
DMAC_CHCTRLA_Type::ENABLE
uint32_t ENABLE
Definition: dmac.h:895
Dmac::PENDCH
__I DMAC_PENDCH_Type PENDCH
Offset: 0x2C (R/ 32) Pending Channels.
Definition: dmac.h:1384
DMAC_PENDCH_Type::PENDCH14
uint32_t PENDCH14
Definition: dmac.h:710
DMAC_CRCCHKSUM_Type
Definition: dmac.h:155
DMAC_PENDCH_Type::PENDCH10
uint32_t PENDCH10
Definition: dmac.h:706
DmacDescriptor::BTCTRL
__IO DMAC_BTCTRL_Type BTCTRL
Offset: 0x00 (R/W 16) Block Transfer Control.
Definition: dmac.h:1396
DMAC_PRICTRL0_Type::RRLVLEN2
uint32_t RRLVLEN2
Definition: dmac.h:341
DMAC_INTPEND_Type::TCMPL
uint16_t TCMPL
Definition: dmac.h:426
DMAC_PENDCH_Type::PENDCH5
uint32_t PENDCH5
Definition: dmac.h:701
DMAC_INTPEND_Type::SUSP
uint16_t SUSP
Definition: dmac.h:427
DMAC_SWTRIGCTRL_Type::SWTRIG17
uint32_t SWTRIG17
Definition: dmac.h:234
DMAC_CTRL_Type::LVLEN3
uint16_t LVLEN3
Definition: dmac.h:52
DMAC_PENDCH_Type::PENDCH20
uint32_t PENDCH20
Definition: dmac.h:716
DMAC_SWTRIGCTRL_Type::SWTRIG25
uint32_t SWTRIG25
Definition: dmac.h:242
DMAC_INTPEND_Type::CRCERR
uint16_t CRCERR
Definition: dmac.h:429
DMAC_DSTADDR_Type::DSTADDR
uint32_t DSTADDR
Definition: dmac.h:1316
DMAC_PRICTRL0_Type::QOS3
uint32_t QOS3
Definition: dmac.h:343
DMAC_BUSYCH_Type::BUSYCH17
uint32_t BUSYCH17
Definition: dmac.h:597
DMAC_PENDCH_Type
Definition: dmac.h:694
DMAC_PENDCH_Type::PENDCH1
uint32_t PENDCH1
Definition: dmac.h:697
DMAC_PRICTRL0_Type::RRLVLEN1
uint32_t RRLVLEN1
Definition: dmac.h:338
DMAC_PENDCH_Type::PENDCH22
uint32_t PENDCH22
Definition: dmac.h:718
DMAC_BUSYCH_Type::BUSYCH7
uint32_t BUSYCH7
Definition: dmac.h:587
Dmac::CRCCHKSUM
__IO DMAC_CRCCHKSUM_Type CRCCHKSUM
Offset: 0x08 (R/W 32) CRC Checksum.
Definition: dmac.h:1373
Dmac::CTRL
__IO DMAC_CTRL_Type CTRL
Offset: 0x00 (R/W 16) Control.
Definition: dmac.h:1370
DMAC_PENDCH_Type::PENDCH17
uint32_t PENDCH17
Definition: dmac.h:713
DMAC_DSTADDR_Type::reg
uint32_t reg
Definition: dmac.h:1318
DMAC_INTSTATUS_Type::CHINT25
uint32_t CHINT25
Definition: dmac.h:489
DMAC_INTPEND_Type::reg
uint16_t reg
Definition: dmac.h:434
DMAC_INTSTATUS_Type::CHINT21
uint32_t CHINT21
Definition: dmac.h:485
DMAC_INTSTATUS_Type::CHINT0
uint32_t CHINT0
Definition: dmac.h:464
DMAC_CHCTRLB_Type
Definition: dmac.h:984
DmacDescriptor::DSTADDR
__IO DMAC_DSTADDR_Type DSTADDR
Offset: 0x08 (R/W 32) Block Transfer Destination Address.
Definition: dmac.h:1399
DMAC_BASEADDR_Type::reg
uint32_t reg
Definition: dmac.h:860
DMAC_BTCTRL_Type::SRCINC
uint16_t SRCINC
Definition: dmac.h:1199
DMAC_CHEVCTRL_Type::EVOE
uint8_t EVOE
Definition: dmac.h:1050
DMAC_SWTRIGCTRL_Type::SWTRIG9
uint32_t SWTRIG9
Definition: dmac.h:226
DMAC_CHINTENSET_Type::SUSP
uint8_t SUSP
Definition: dmac.h:1121
DMAC_PRICTRL0_Type::QOS0
uint32_t QOS0
Definition: dmac.h:334
DMAC_PENDCH_Type::PENDCH31
uint32_t PENDCH31
Definition: dmac.h:727
DMAC_CHCTRLA_Type::reg
uint32_t reg
Definition: dmac.h:907
DMAC_INTSTATUS_Type::CHINT8
uint32_t CHINT8
Definition: dmac.h:472
DMAC_CRCCTRL_Type
Definition: dmac.h:86
DMAC_CHEVCTRL_Type::EVACT
uint8_t EVACT
Definition: dmac.h:1046
DMAC_CHCTRLA_Type::RUNSTDBY
uint32_t RUNSTDBY
Definition: dmac.h:897
DMAC_PENDCH_Type::PENDCH26
uint32_t PENDCH26
Definition: dmac.h:722
DMAC_BUSYCH_Type::BUSYCH5
uint32_t BUSYCH5
Definition: dmac.h:585
DMAC_DSTADDR_Type
Definition: dmac.h:1311
DMAC_CHSTATUS_Type::PEND
uint8_t PEND
Definition: dmac.h:1167
DMAC_SWTRIGCTRL_Type::SWTRIG7
uint32_t SWTRIG7
Definition: dmac.h:224
DMAC_SWTRIGCTRL_Type::SWTRIG22
uint32_t SWTRIG22
Definition: dmac.h:239
DMAC_SWTRIGCTRL_Type::SWTRIG3
uint32_t SWTRIG3
Definition: dmac.h:220
DMAC_INTSTATUS_Type::CHINT6
uint32_t CHINT6
Definition: dmac.h:470
DmacChannel::CHSTATUS
__IO DMAC_CHSTATUS_Type CHSTATUS
Offset: 0x0F (R/W 8) Channel n Status.
Definition: dmac.h:1363
DMAC_SWTRIGCTRL_Type::SWTRIG12
uint32_t SWTRIG12
Definition: dmac.h:229
DMAC_PENDCH_Type::PENDCH2
uint32_t PENDCH2
Definition: dmac.h:698
DMAC_BUSYCH_Type::BUSYCH29
uint32_t BUSYCH29
Definition: dmac.h:609
DMAC_SWTRIGCTRL_Type
Definition: dmac.h:215
Dmac::CRCCTRL
__IO DMAC_CRCCTRL_Type CRCCTRL
Offset: 0x02 (R/W 16) CRC Control.
Definition: dmac.h:1371
DMAC_SWTRIGCTRL_Type::SWTRIG10
uint32_t SWTRIG10
Definition: dmac.h:227
DMAC_BTCTRL_Type::reg
uint16_t reg
Definition: dmac.h:1204
DMAC_INTPEND_Type::PEND
uint16_t PEND
Definition: dmac.h:432
DMAC_CHSTATUS_Type::reg
uint8_t reg
Definition: dmac.h:1173
DMAC_CRCSTATUS_Type::CRCERR
uint8_t CRCERR
Definition: dmac.h:177
DMAC_CHINTFLAG_Type
Definition: dmac.h:1141
DMAC_INTSTATUS_Type::CHINT24
uint32_t CHINT24
Definition: dmac.h:488
DMAC_INTPEND_Type::TERR
uint16_t TERR
Definition: dmac.h:425
DMAC_DBGCTRL_Type
Definition: dmac.h:197
DMAC_SRCADDR_Type::reg
uint32_t reg
Definition: dmac.h:1297
DMAC_CHEVCTRL_Type::EVOMODE
uint8_t EVOMODE
Definition: dmac.h:1048
DMAC_CHEVCTRL_Type::reg
uint8_t reg
Definition: dmac.h:1052
DMAC_INTSTATUS_Type::CHINT19
uint32_t CHINT19
Definition: dmac.h:483
DMAC_INTSTATUS_Type::CHINT9
uint32_t CHINT9
Definition: dmac.h:473
DMAC_INTSTATUS_Type::CHINT15
uint32_t CHINT15
Definition: dmac.h:479
DMAC_PENDCH_Type::PENDCH11
uint32_t PENDCH11
Definition: dmac.h:707
DMAC_PENDCH_Type::PENDCH4
uint32_t PENDCH4
Definition: dmac.h:700
DMAC_CRCSTATUS_Type::reg
uint8_t reg
Definition: dmac.h:180
Dmac::CRCDATAIN
__IO DMAC_CRCDATAIN_Type CRCDATAIN
Offset: 0x04 (R/W 32) CRC Data Input.
Definition: dmac.h:1372
DMAC_CTRL_Type::LVLEN2
uint16_t LVLEN2
Definition: dmac.h:51
DMAC_BUSYCH_Type::BUSYCH
uint32_t BUSYCH
Definition: dmac.h:614
DMAC_SWTRIGCTRL_Type::SWTRIG21
uint32_t SWTRIG21
Definition: dmac.h:238
DMAC_BUSYCH_Type::BUSYCH9
uint32_t BUSYCH9
Definition: dmac.h:589
DMAC_BUSYCH_Type::BUSYCH19
uint32_t BUSYCH19
Definition: dmac.h:599
DMAC_INTSTATUS_Type::CHINT29
uint32_t CHINT29
Definition: dmac.h:493
DMAC_ACTIVE_Type::BTCNT
uint32_t BTCNT
Definition: dmac.h:820
DmacChannel
DmacChannel hardware registers.
Definition: dmac.h:1354
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
DMAC_BUSYCH_Type::BUSYCH1
uint32_t BUSYCH1
Definition: dmac.h:581
DMAC_CRCCTRL_Type::CRCBEATSIZE
uint16_t CRCBEATSIZE
Definition: dmac.h:88
DMAC_CTRL_Type::reg
uint16_t reg
Definition: dmac.h:60
DMAC_INTSTATUS_Type::CHINT31
uint32_t CHINT31
Definition: dmac.h:495
DMAC_BUSYCH_Type::BUSYCH23
uint32_t BUSYCH23
Definition: dmac.h:603
DMAC_BASEADDR_Type
Definition: dmac.h:856
DMAC_PRICTRL0_Type::reg
uint32_t reg
Definition: dmac.h:346
DMAC_CHINTFLAG_Type::SUSP
__I uint8_t SUSP
Definition: dmac.h:1145
DMAC_CRCCTRL_Type::CRCSRC
uint16_t CRCSRC
Definition: dmac.h:91
DMAC_INTSTATUS_Type
Definition: dmac.h:462
DMAC_WRBADDR_Type
Definition: dmac.h:874
DMAC_INTSTATUS_Type::CHINT12
uint32_t CHINT12
Definition: dmac.h:476
DMAC_BUSYCH_Type::BUSYCH3
uint32_t BUSYCH3
Definition: dmac.h:583
DMAC_BTCTRL_Type::BLOCKACT
uint16_t BLOCKACT
Definition: dmac.h:1196
DMAC_PENDCH_Type::PENDCH15
uint32_t PENDCH15
Definition: dmac.h:711
DMAC_INTSTATUS_Type::CHINT5
uint32_t CHINT5
Definition: dmac.h:469
DMAC_CHCTRLA_Type::BURSTLEN
uint32_t BURSTLEN
Definition: dmac.h:903
DMAC_INTSTATUS_Type::CHINT2
uint32_t CHINT2
Definition: dmac.h:466
DMAC_SWTRIGCTRL_Type::SWTRIG23
uint32_t SWTRIG23
Definition: dmac.h:240
DMAC_PENDCH_Type::reg
uint32_t reg
Definition: dmac.h:732
DMAC_CHINTENCLR_Type::reg
uint8_t reg
Definition: dmac.h:1100
DMAC_INTSTATUS_Type::CHINT18
uint32_t CHINT18
Definition: dmac.h:482
DMAC_SWTRIGCTRL_Type::SWTRIG16
uint32_t SWTRIG16
Definition: dmac.h:233
DMAC_SWTRIGCTRL_Type::SWTRIG2
uint32_t SWTRIG2
Definition: dmac.h:219
DMAC_BUSYCH_Type::reg
uint32_t reg
Definition: dmac.h:616
DMAC_CHINTENCLR_Type
Definition: dmac.h:1093
DMAC_INTSTATUS_Type::CHINT16
uint32_t CHINT16
Definition: dmac.h:480
DMAC_CRCDATAIN_Type
Definition: dmac.h:137
DMAC_SRCADDR_Type::SRCADDR
uint32_t SRCADDR
Definition: dmac.h:1295
DMAC_INTSTATUS_Type::CHINT22
uint32_t CHINT22
Definition: dmac.h:486
DMAC_WRBADDR_Type::reg
uint32_t reg
Definition: dmac.h:878
DMAC_PENDCH_Type::PENDCH29
uint32_t PENDCH29
Definition: dmac.h:725
DMAC_PENDCH_Type::PENDCH0
uint32_t PENDCH0
Definition: dmac.h:696
Dmac::SWTRIGCTRL
__IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL
Offset: 0x10 (R/W 32) Software Trigger Control.
Definition: dmac.h:1377
DMAC_CRCCTRL_Type::CRCPOLY
uint16_t CRCPOLY
Definition: dmac.h:89
DMAC_BTCTRL_Type::BEATSIZE
uint16_t BEATSIZE
Definition: dmac.h:1198
DMAC_ACTIVE_Type::ID
uint32_t ID
Definition: dmac.h:817
DMAC_SRCADDR_Type
Definition: dmac.h:1293
DMAC_CHINTFLAG_Type::TERR
__I uint8_t TERR
Definition: dmac.h:1143
DMAC_CRCSTATUS_Type
Definition: dmac.h:173
DMAC_PENDCH_Type::PENDCH6
uint32_t PENDCH6
Definition: dmac.h:702
DMAC_WRBADDR_Type::WRBADDR
uint32_t WRBADDR
Definition: dmac.h:876
DMAC_PENDCH_Type::PENDCH9
uint32_t PENDCH9
Definition: dmac.h:705
DMAC_BUSYCH_Type::BUSYCH14
uint32_t BUSYCH14
Definition: dmac.h:594
DmacChannel::CHINTENSET
__IO DMAC_CHINTENSET_Type CHINTENSET
Offset: 0x0D (R/W 8) Channel n Interrupt Enable Set.
Definition: dmac.h:1361
DMAC_SWTRIGCTRL_Type::SWTRIG
uint32_t SWTRIG
Definition: dmac.h:251
DMAC_DBGCTRL_Type::reg
uint8_t reg
Definition: dmac.h:202
DMAC_PENDCH_Type::PENDCH13
uint32_t PENDCH13
Definition: dmac.h:709
DMAC_BUSYCH_Type::BUSYCH10
uint32_t BUSYCH10
Definition: dmac.h:590
DMAC_PENDCH_Type::PENDCH23
uint32_t PENDCH23
Definition: dmac.h:719
DMAC_CHEVCTRL_Type::EVIE
uint8_t EVIE
Definition: dmac.h:1049
DMAC_CHSTATUS_Type::FERR
uint8_t FERR
Definition: dmac.h:1169
DMAC_CHPRILVL_Type
Definition: dmac.h:1009
DMAC_SWTRIGCTRL_Type::reg
uint32_t reg
Definition: dmac.h:253
DMAC_SWTRIGCTRL_Type::SWTRIG5
uint32_t SWTRIG5
Definition: dmac.h:222
DMAC_BTCTRL_Type::STEPSIZE
uint16_t STEPSIZE
Definition: dmac.h:1202