SAME54P20A Test Project
gclk.h
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1 
30 #ifndef _SAME54_GCLK_COMPONENT_
31 #define _SAME54_GCLK_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define GCLK_U2122
40 #define REV_GCLK 0x120
41 
42 /* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t SWRST:1;
47  uint8_t :7;
48  } bit;
49  uint8_t reg;
51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
52 
53 #define GCLK_CTRLA_OFFSET 0x00
54 #define GCLK_CTRLA_RESETVALUE _U_(0x00)
56 #define GCLK_CTRLA_SWRST_Pos 0
57 #define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
58 #define GCLK_CTRLA_MASK _U_(0x01)
60 /* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
62 typedef union {
63  struct {
64  uint32_t SWRST:1;
65  uint32_t :1;
66  uint32_t GENCTRL0:1;
67  uint32_t GENCTRL1:1;
68  uint32_t GENCTRL2:1;
69  uint32_t GENCTRL3:1;
70  uint32_t GENCTRL4:1;
71  uint32_t GENCTRL5:1;
72  uint32_t GENCTRL6:1;
73  uint32_t GENCTRL7:1;
74  uint32_t GENCTRL8:1;
75  uint32_t GENCTRL9:1;
76  uint32_t GENCTRL10:1;
77  uint32_t GENCTRL11:1;
78  uint32_t :18;
79  } bit;
80  struct {
81  uint32_t :2;
82  uint32_t GENCTRL:12;
83  uint32_t :18;
84  } vec;
85  uint32_t reg;
87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
88 
89 #define GCLK_SYNCBUSY_OFFSET 0x04
90 #define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000)
92 #define GCLK_SYNCBUSY_SWRST_Pos 0
93 #define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
94 #define GCLK_SYNCBUSY_GENCTRL0_Pos 2
95 #define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
96 #define GCLK_SYNCBUSY_GENCTRL1_Pos 3
97 #define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
98 #define GCLK_SYNCBUSY_GENCTRL2_Pos 4
99 #define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
100 #define GCLK_SYNCBUSY_GENCTRL3_Pos 5
101 #define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
102 #define GCLK_SYNCBUSY_GENCTRL4_Pos 6
103 #define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
104 #define GCLK_SYNCBUSY_GENCTRL5_Pos 7
105 #define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
106 #define GCLK_SYNCBUSY_GENCTRL6_Pos 8
107 #define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
108 #define GCLK_SYNCBUSY_GENCTRL7_Pos 9
109 #define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
110 #define GCLK_SYNCBUSY_GENCTRL8_Pos 10
111 #define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
112 #define GCLK_SYNCBUSY_GENCTRL9_Pos 11
113 #define GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
114 #define GCLK_SYNCBUSY_GENCTRL10_Pos 12
115 #define GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
116 #define GCLK_SYNCBUSY_GENCTRL11_Pos 13
117 #define GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
118 #define GCLK_SYNCBUSY_GENCTRL_Pos 2
119 #define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
120 #define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
121 #define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1)
122 #define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2)
123 #define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4)
124 #define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8)
125 #define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10)
126 #define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20)
127 #define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40)
128 #define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80)
129 #define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100)
130 #define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200)
131 #define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400)
132 #define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800)
133 #define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
134 #define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
135 #define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
136 #define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
137 #define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
138 #define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
139 #define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
140 #define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
141 #define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
142 #define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
143 #define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
144 #define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
145 #define GCLK_SYNCBUSY_MASK _U_(0x00003FFD)
147 /* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
149 typedef union {
150  struct {
151  uint32_t SRC:4;
152  uint32_t :4;
153  uint32_t GENEN:1;
154  uint32_t IDC:1;
155  uint32_t OOV:1;
156  uint32_t OE:1;
157  uint32_t DIVSEL:1;
158  uint32_t RUNSTDBY:1;
159  uint32_t :2;
160  uint32_t DIV:16;
161  } bit;
162  uint32_t reg;
164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
165 
166 #define GCLK_GENCTRL_OFFSET 0x20
167 #define GCLK_GENCTRL_RESETVALUE _U_(0x00000000)
169 #define GCLK_GENCTRL_SRC_Pos 0
170 #define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
171 #define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
172 #define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0)
173 #define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1)
174 #define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2)
175 #define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3)
176 #define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4)
177 #define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5)
178 #define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6)
179 #define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7)
180 #define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8)
181 #define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)
182 #define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)
183 #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
184 #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
185 #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
186 #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
187 #define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)
188 #define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)
189 #define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)
190 #define GCLK_GENCTRL_GENEN_Pos 8
191 #define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
192 #define GCLK_GENCTRL_IDC_Pos 9
193 #define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
194 #define GCLK_GENCTRL_OOV_Pos 10
195 #define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
196 #define GCLK_GENCTRL_OE_Pos 11
197 #define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
198 #define GCLK_GENCTRL_DIVSEL_Pos 12
199 #define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
200 #define GCLK_GENCTRL_RUNSTDBY_Pos 13
201 #define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
202 #define GCLK_GENCTRL_DIV_Pos 16
203 #define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
204 #define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
205 #define GCLK_GENCTRL_MASK _U_(0xFFFF3F0F)
207 /* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
209 typedef union {
210  struct {
211  uint32_t GEN:4;
212  uint32_t :2;
213  uint32_t CHEN:1;
214  uint32_t WRTLOCK:1;
215  uint32_t :24;
216  } bit;
217  uint32_t reg;
219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
220 
221 #define GCLK_PCHCTRL_OFFSET 0x80
222 #define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000)
224 #define GCLK_PCHCTRL_GEN_Pos 0
225 #define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
226 #define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
227 #define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0)
228 #define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1)
229 #define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2)
230 #define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3)
231 #define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4)
232 #define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5)
233 #define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6)
234 #define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7)
235 #define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8)
236 #define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9)
237 #define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA)
238 #define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB)
239 #define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
240 #define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
241 #define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
242 #define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
243 #define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
244 #define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
245 #define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
246 #define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
247 #define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
248 #define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)
249 #define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)
250 #define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)
251 #define GCLK_PCHCTRL_CHEN_Pos 6
252 #define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
253 #define GCLK_PCHCTRL_WRTLOCK_Pos 7
254 #define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
255 #define GCLK_PCHCTRL_MASK _U_(0x000000CF)
258 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
259 typedef struct {
261  RoReg8 Reserved1[0x3];
263  RoReg8 Reserved2[0x18];
264  __IO GCLK_GENCTRL_Type GENCTRL[12];
265  RoReg8 Reserved3[0x30];
266  __IO GCLK_PCHCTRL_Type PCHCTRL[48];
267 } Gclk;
268 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
269 
272 #endif /* _SAME54_GCLK_COMPONENT_ */
GCLK_GENCTRL_Type::reg
uint32_t reg
Definition: gclk.h:162
GCLK_GENCTRL_Type::GENEN
uint32_t GENEN
Definition: gclk.h:153
GCLK_SYNCBUSY_Type::GENCTRL10
uint32_t GENCTRL10
Definition: gclk.h:76
GCLK_GENCTRL_Type::DIV
uint32_t DIV
Definition: gclk.h:160
GCLK_PCHCTRL_Type::reg
uint32_t reg
Definition: gclk.h:217
GCLK_GENCTRL_Type::OOV
uint32_t OOV
Definition: gclk.h:155
GCLK_PCHCTRL_Type::GEN
uint32_t GEN
Definition: gclk.h:211
GCLK_PCHCTRL_Type::WRTLOCK
uint32_t WRTLOCK
Definition: gclk.h:214
GCLK_SYNCBUSY_Type::GENCTRL0
uint32_t GENCTRL0
Definition: gclk.h:66
GCLK_PCHCTRL_Type
Definition: gclk.h:209
GCLK_SYNCBUSY_Type::SWRST
uint32_t SWRST
Definition: gclk.h:64
GCLK_SYNCBUSY_Type::GENCTRL2
uint32_t GENCTRL2
Definition: gclk.h:68
GCLK_SYNCBUSY_Type
Definition: gclk.h:62
Gclk
GCLK hardware registers.
Definition: gclk.h:259
GCLK_SYNCBUSY_Type::GENCTRL9
uint32_t GENCTRL9
Definition: gclk.h:75
GCLK_SYNCBUSY_Type::GENCTRL8
uint32_t GENCTRL8
Definition: gclk.h:74
GCLK_SYNCBUSY_Type::GENCTRL4
uint32_t GENCTRL4
Definition: gclk.h:70
GCLK_SYNCBUSY_Type::GENCTRL5
uint32_t GENCTRL5
Definition: gclk.h:71
GCLK_GENCTRL_Type::IDC
uint32_t IDC
Definition: gclk.h:154
Gclk::SYNCBUSY
__I GCLK_SYNCBUSY_Type SYNCBUSY
Offset: 0x04 (R/ 32) Synchronization Busy.
Definition: gclk.h:262
GCLK_CTRLA_Type::reg
uint8_t reg
Definition: gclk.h:49
Gclk::CTRLA
__IO GCLK_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control.
Definition: gclk.h:260
GCLK_GENCTRL_Type::DIVSEL
uint32_t DIVSEL
Definition: gclk.h:157
GCLK_PCHCTRL_Type::CHEN
uint32_t CHEN
Definition: gclk.h:213
GCLK_SYNCBUSY_Type::GENCTRL7
uint32_t GENCTRL7
Definition: gclk.h:73
GCLK_CTRLA_Type::SWRST
uint8_t SWRST
Definition: gclk.h:46
GCLK_GENCTRL_Type
Definition: gclk.h:149
GCLK_SYNCBUSY_Type::GENCTRL1
uint32_t GENCTRL1
Definition: gclk.h:67
GCLK_SYNCBUSY_Type::GENCTRL3
uint32_t GENCTRL3
Definition: gclk.h:69
GCLK_GENCTRL_Type::OE
uint32_t OE
Definition: gclk.h:156
GCLK_CTRLA_Type
Definition: gclk.h:44
GCLK_GENCTRL_Type::SRC
uint32_t SRC
Definition: gclk.h:151
GCLK_SYNCBUSY_Type::GENCTRL6
uint32_t GENCTRL6
Definition: gclk.h:72
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
GCLK_SYNCBUSY_Type::reg
uint32_t reg
Definition: gclk.h:85
GCLK_SYNCBUSY_Type::GENCTRL
uint32_t GENCTRL
Definition: gclk.h:82
GCLK_SYNCBUSY_Type::GENCTRL11
uint32_t GENCTRL11
Definition: gclk.h:77
GCLK_GENCTRL_Type::RUNSTDBY
uint32_t RUNSTDBY
Definition: gclk.h:158