SAME54P20A Test Project
dac.h
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1 
30 #ifndef _SAME54_DAC_COMPONENT_
31 #define _SAME54_DAC_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define DAC_U2502
40 #define REV_DAC 0x100
41 
42 /* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t SWRST:1;
47  uint8_t ENABLE:1;
48  uint8_t :6;
49  } bit;
50  uint8_t reg;
52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
53 
54 #define DAC_CTRLA_OFFSET 0x00
55 #define DAC_CTRLA_RESETVALUE _U_(0x00)
57 #define DAC_CTRLA_SWRST_Pos 0
58 #define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
59 #define DAC_CTRLA_ENABLE_Pos 1
60 #define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
61 #define DAC_CTRLA_MASK _U_(0x03)
63 /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
65 typedef union {
66  struct {
67  uint8_t DIFF:1;
68  uint8_t REFSEL:2;
69  uint8_t :5;
70  } bit;
71  uint8_t reg;
73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
74 
75 #define DAC_CTRLB_OFFSET 0x01
76 #define DAC_CTRLB_RESETVALUE _U_(0x02)
78 #define DAC_CTRLB_DIFF_Pos 0
79 #define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
80 #define DAC_CTRLB_REFSEL_Pos 1
81 #define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
82 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
83 #define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0)
84 #define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1)
85 #define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2)
86 #define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3)
87 #define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)
88 #define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)
89 #define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)
90 #define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)
91 #define DAC_CTRLB_MASK _U_(0x07)
93 /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
95 typedef union {
96  struct {
97  uint8_t STARTEI0:1;
98  uint8_t STARTEI1:1;
99  uint8_t EMPTYEO0:1;
100  uint8_t EMPTYEO1:1;
101  uint8_t INVEI0:1;
102  uint8_t INVEI1:1;
103  uint8_t RESRDYEO0:1;
104  uint8_t RESRDYEO1:1;
105  } bit;
106  struct {
107  uint8_t STARTEI:2;
108  uint8_t EMPTYEO:2;
109  uint8_t INVEI:2;
110  uint8_t RESRDYEO:2;
111  } vec;
112  uint8_t reg;
114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
115 
116 #define DAC_EVCTRL_OFFSET 0x02
117 #define DAC_EVCTRL_RESETVALUE _U_(0x00)
119 #define DAC_EVCTRL_STARTEI0_Pos 0
120 #define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
121 #define DAC_EVCTRL_STARTEI1_Pos 1
122 #define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
123 #define DAC_EVCTRL_STARTEI_Pos 0
124 #define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
125 #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
126 #define DAC_EVCTRL_EMPTYEO0_Pos 2
127 #define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
128 #define DAC_EVCTRL_EMPTYEO1_Pos 3
129 #define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
130 #define DAC_EVCTRL_EMPTYEO_Pos 2
131 #define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
132 #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
133 #define DAC_EVCTRL_INVEI0_Pos 4
134 #define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
135 #define DAC_EVCTRL_INVEI1_Pos 5
136 #define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
137 #define DAC_EVCTRL_INVEI_Pos 4
138 #define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
139 #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
140 #define DAC_EVCTRL_RESRDYEO0_Pos 6
141 #define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
142 #define DAC_EVCTRL_RESRDYEO1_Pos 7
143 #define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
144 #define DAC_EVCTRL_RESRDYEO_Pos 6
145 #define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
146 #define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
147 #define DAC_EVCTRL_MASK _U_(0xFF)
149 /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
151 typedef union {
152  struct {
153  uint8_t UNDERRUN0:1;
154  uint8_t UNDERRUN1:1;
155  uint8_t EMPTY0:1;
156  uint8_t EMPTY1:1;
157  uint8_t RESRDY0:1;
158  uint8_t RESRDY1:1;
159  uint8_t OVERRUN0:1;
160  uint8_t OVERRUN1:1;
161  } bit;
162  struct {
163  uint8_t UNDERRUN:2;
164  uint8_t EMPTY:2;
165  uint8_t RESRDY:2;
166  uint8_t OVERRUN:2;
167  } vec;
168  uint8_t reg;
170 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
171 
172 #define DAC_INTENCLR_OFFSET 0x04
173 #define DAC_INTENCLR_RESETVALUE _U_(0x00)
175 #define DAC_INTENCLR_UNDERRUN0_Pos 0
176 #define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
177 #define DAC_INTENCLR_UNDERRUN1_Pos 1
178 #define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
179 #define DAC_INTENCLR_UNDERRUN_Pos 0
180 #define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
181 #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
182 #define DAC_INTENCLR_EMPTY0_Pos 2
183 #define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
184 #define DAC_INTENCLR_EMPTY1_Pos 3
185 #define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
186 #define DAC_INTENCLR_EMPTY_Pos 2
187 #define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
188 #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
189 #define DAC_INTENCLR_RESRDY0_Pos 4
190 #define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
191 #define DAC_INTENCLR_RESRDY1_Pos 5
192 #define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
193 #define DAC_INTENCLR_RESRDY_Pos 4
194 #define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
195 #define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
196 #define DAC_INTENCLR_OVERRUN0_Pos 6
197 #define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
198 #define DAC_INTENCLR_OVERRUN1_Pos 7
199 #define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
200 #define DAC_INTENCLR_OVERRUN_Pos 6
201 #define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
202 #define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
203 #define DAC_INTENCLR_MASK _U_(0xFF)
205 /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
207 typedef union {
208  struct {
209  uint8_t UNDERRUN0:1;
210  uint8_t UNDERRUN1:1;
211  uint8_t EMPTY0:1;
212  uint8_t EMPTY1:1;
213  uint8_t RESRDY0:1;
214  uint8_t RESRDY1:1;
215  uint8_t OVERRUN0:1;
216  uint8_t OVERRUN1:1;
217  } bit;
218  struct {
219  uint8_t UNDERRUN:2;
220  uint8_t EMPTY:2;
221  uint8_t RESRDY:2;
222  uint8_t OVERRUN:2;
223  } vec;
224  uint8_t reg;
226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
227 
228 #define DAC_INTENSET_OFFSET 0x05
229 #define DAC_INTENSET_RESETVALUE _U_(0x00)
231 #define DAC_INTENSET_UNDERRUN0_Pos 0
232 #define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
233 #define DAC_INTENSET_UNDERRUN1_Pos 1
234 #define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
235 #define DAC_INTENSET_UNDERRUN_Pos 0
236 #define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
237 #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
238 #define DAC_INTENSET_EMPTY0_Pos 2
239 #define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
240 #define DAC_INTENSET_EMPTY1_Pos 3
241 #define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
242 #define DAC_INTENSET_EMPTY_Pos 2
243 #define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
244 #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
245 #define DAC_INTENSET_RESRDY0_Pos 4
246 #define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
247 #define DAC_INTENSET_RESRDY1_Pos 5
248 #define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
249 #define DAC_INTENSET_RESRDY_Pos 4
250 #define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
251 #define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
252 #define DAC_INTENSET_OVERRUN0_Pos 6
253 #define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
254 #define DAC_INTENSET_OVERRUN1_Pos 7
255 #define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
256 #define DAC_INTENSET_OVERRUN_Pos 6
257 #define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
258 #define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
259 #define DAC_INTENSET_MASK _U_(0xFF)
261 /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
263 typedef union { // __I to avoid read-modify-write on write-to-clear register
264  struct {
265  __I uint8_t UNDERRUN0:1;
266  __I uint8_t UNDERRUN1:1;
267  __I uint8_t EMPTY0:1;
268  __I uint8_t EMPTY1:1;
269  __I uint8_t RESRDY0:1;
270  __I uint8_t RESRDY1:1;
271  __I uint8_t OVERRUN0:1;
272  __I uint8_t OVERRUN1:1;
273  } bit;
274  struct {
275  __I uint8_t UNDERRUN:2;
276  __I uint8_t EMPTY:2;
277  __I uint8_t RESRDY:2;
278  __I uint8_t OVERRUN:2;
279  } vec;
280  uint8_t reg;
282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
283 
284 #define DAC_INTFLAG_OFFSET 0x06
285 #define DAC_INTFLAG_RESETVALUE _U_(0x00)
287 #define DAC_INTFLAG_UNDERRUN0_Pos 0
288 #define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
289 #define DAC_INTFLAG_UNDERRUN1_Pos 1
290 #define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
291 #define DAC_INTFLAG_UNDERRUN_Pos 0
292 #define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
293 #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
294 #define DAC_INTFLAG_EMPTY0_Pos 2
295 #define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
296 #define DAC_INTFLAG_EMPTY1_Pos 3
297 #define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
298 #define DAC_INTFLAG_EMPTY_Pos 2
299 #define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
300 #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
301 #define DAC_INTFLAG_RESRDY0_Pos 4
302 #define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
303 #define DAC_INTFLAG_RESRDY1_Pos 5
304 #define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
305 #define DAC_INTFLAG_RESRDY_Pos 4
306 #define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
307 #define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
308 #define DAC_INTFLAG_OVERRUN0_Pos 6
309 #define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
310 #define DAC_INTFLAG_OVERRUN1_Pos 7
311 #define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
312 #define DAC_INTFLAG_OVERRUN_Pos 6
313 #define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
314 #define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
315 #define DAC_INTFLAG_MASK _U_(0xFF)
317 /* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */
318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
319 typedef union {
320  struct {
321  uint8_t READY0:1;
322  uint8_t READY1:1;
323  uint8_t EOC0:1;
324  uint8_t EOC1:1;
325  uint8_t :4;
326  } bit;
327  struct {
328  uint8_t READY:2;
329  uint8_t EOC:2;
330  uint8_t :4;
331  } vec;
332  uint8_t reg;
334 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
335 
336 #define DAC_STATUS_OFFSET 0x07
337 #define DAC_STATUS_RESETVALUE _U_(0x00)
339 #define DAC_STATUS_READY0_Pos 0
340 #define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)
341 #define DAC_STATUS_READY1_Pos 1
342 #define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)
343 #define DAC_STATUS_READY_Pos 0
344 #define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)
345 #define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
346 #define DAC_STATUS_EOC0_Pos 2
347 #define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)
348 #define DAC_STATUS_EOC1_Pos 3
349 #define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)
350 #define DAC_STATUS_EOC_Pos 2
351 #define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)
352 #define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
353 #define DAC_STATUS_MASK _U_(0x0F)
355 /* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */
356 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
357 typedef union {
358  struct {
359  uint32_t SWRST:1;
360  uint32_t ENABLE:1;
361  uint32_t DATA0:1;
362  uint32_t DATA1:1;
363  uint32_t DATABUF0:1;
364  uint32_t DATABUF1:1;
365  uint32_t :26;
366  } bit;
367  struct {
368  uint32_t :2;
369  uint32_t DATA:2;
370  uint32_t DATABUF:2;
371  uint32_t :26;
372  } vec;
373  uint32_t reg;
375 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
376 
377 #define DAC_SYNCBUSY_OFFSET 0x08
378 #define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000)
380 #define DAC_SYNCBUSY_SWRST_Pos 0
381 #define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
382 #define DAC_SYNCBUSY_ENABLE_Pos 1
383 #define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
384 #define DAC_SYNCBUSY_DATA0_Pos 2
385 #define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
386 #define DAC_SYNCBUSY_DATA1_Pos 3
387 #define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
388 #define DAC_SYNCBUSY_DATA_Pos 2
389 #define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
390 #define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
391 #define DAC_SYNCBUSY_DATABUF0_Pos 4
392 #define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
393 #define DAC_SYNCBUSY_DATABUF1_Pos 5
394 #define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
395 #define DAC_SYNCBUSY_DATABUF_Pos 4
396 #define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
397 #define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
398 #define DAC_SYNCBUSY_MASK _U_(0x0000003F)
400 /* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */
401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
402 typedef union {
403  struct {
404  uint16_t LEFTADJ:1;
405  uint16_t ENABLE:1;
406  uint16_t CCTRL:2;
407  uint16_t :1;
408  uint16_t FEXT:1;
409  uint16_t RUNSTDBY:1;
410  uint16_t DITHER:1;
411  uint16_t REFRESH:4;
412  uint16_t :1;
413  uint16_t OSR:3;
414  } bit;
415  uint16_t reg;
417 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
418 
419 #define DAC_DACCTRL_OFFSET 0x0C
420 #define DAC_DACCTRL_RESETVALUE _U_(0x0000)
422 #define DAC_DACCTRL_LEFTADJ_Pos 0
423 #define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
424 #define DAC_DACCTRL_ENABLE_Pos 1
425 #define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
426 #define DAC_DACCTRL_CCTRL_Pos 2
427 #define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
428 #define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
429 #define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0)
430 #define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1)
431 #define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2)
432 #define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)
433 #define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)
434 #define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)
435 #define DAC_DACCTRL_FEXT_Pos 5
436 #define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
437 #define DAC_DACCTRL_RUNSTDBY_Pos 6
438 #define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
439 #define DAC_DACCTRL_DITHER_Pos 7
440 #define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
441 #define DAC_DACCTRL_REFRESH_Pos 8
442 #define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
443 #define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
444 #define DAC_DACCTRL_OSR_Pos 13
445 #define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
446 #define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
447 #define DAC_DACCTRL_MASK _U_(0xEFEF)
449 /* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */
450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
451 typedef union {
452  struct {
453  uint16_t DATA:16;
454  } bit;
455  uint16_t reg;
456 } DAC_DATA_Type;
457 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
458 
459 #define DAC_DATA_OFFSET 0x10
460 #define DAC_DATA_RESETVALUE _U_(0x0000)
462 #define DAC_DATA_DATA_Pos 0
463 #define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
464 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
465 #define DAC_DATA_MASK _U_(0xFFFF)
467 /* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */
468 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
469 typedef union {
470  struct {
471  uint16_t DATABUF:16;
472  } bit;
473  uint16_t reg;
475 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
476 
477 #define DAC_DATABUF_OFFSET 0x14
478 #define DAC_DATABUF_RESETVALUE _U_(0x0000)
480 #define DAC_DATABUF_DATABUF_Pos 0
481 #define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
482 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
483 #define DAC_DATABUF_MASK _U_(0xFFFF)
485 /* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */
486 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
487 typedef union {
488  struct {
489  uint8_t DBGRUN:1;
490  uint8_t :7;
491  } bit;
492  uint8_t reg;
494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
495 
496 #define DAC_DBGCTRL_OFFSET 0x18
497 #define DAC_DBGCTRL_RESETVALUE _U_(0x00)
499 #define DAC_DBGCTRL_DBGRUN_Pos 0
500 #define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
501 #define DAC_DBGCTRL_MASK _U_(0x01)
503 /* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */
504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
505 typedef union {
506  struct {
507  uint16_t RESULT:16;
508  } bit;
509  uint16_t reg;
511 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
512 
513 #define DAC_RESULT_OFFSET 0x1C
514 #define DAC_RESULT_RESETVALUE _U_(0x0000)
516 #define DAC_RESULT_RESULT_Pos 0
517 #define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
518 #define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
519 #define DAC_RESULT_MASK _U_(0xFFFF)
522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
523 typedef struct {
527  RoReg8 Reserved1[0x1];
533  __IO DAC_DACCTRL_Type DACCTRL[2];
534  __O DAC_DATA_Type DATA[2];
535  __O DAC_DATABUF_Type DATABUF[2];
537  RoReg8 Reserved2[0x3];
538  __I DAC_RESULT_Type RESULT[2];
539 } Dac;
540 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
541 
544 #endif /* _SAME54_DAC_COMPONENT_ */
DAC_INTFLAG_Type::UNDERRUN0
__I uint8_t UNDERRUN0
Definition: dac.h:265
DAC_SYNCBUSY_Type::ENABLE
uint32_t ENABLE
Definition: dac.h:360
DAC_DACCTRL_Type::OSR
uint16_t OSR
Definition: dac.h:413
DAC_INTENCLR_Type::UNDERRUN0
uint8_t UNDERRUN0
Definition: dac.h:153
DAC_DACCTRL_Type::ENABLE
uint16_t ENABLE
Definition: dac.h:405
DAC_INTENCLR_Type::reg
uint8_t reg
Definition: dac.h:168
DAC_INTENSET_Type::OVERRUN0
uint8_t OVERRUN0
Definition: dac.h:215
DAC_DACCTRL_Type
Definition: dac.h:402
DAC_INTFLAG_Type::UNDERRUN
__I uint8_t UNDERRUN
Definition: dac.h:275
DAC_EVCTRL_Type::INVEI0
uint8_t INVEI0
Definition: dac.h:101
DAC_STATUS_Type::EOC0
uint8_t EOC0
Definition: dac.h:323
Dac::STATUS
__I DAC_STATUS_Type STATUS
Offset: 0x07 (R/ 8) Status.
Definition: dac.h:531
DAC_CTRLA_Type
Definition: dac.h:44
DAC_INTENSET_Type::UNDERRUN1
uint8_t UNDERRUN1
Definition: dac.h:210
DAC_INTENSET_Type::RESRDY0
uint8_t RESRDY0
Definition: dac.h:213
Dac::SYNCBUSY
__I DAC_SYNCBUSY_Type SYNCBUSY
Offset: 0x08 (R/ 32) Synchronization Busy.
Definition: dac.h:532
DAC_INTENCLR_Type::UNDERRUN
uint8_t UNDERRUN
Definition: dac.h:163
DAC_DBGCTRL_Type
Definition: dac.h:487
DAC_INTENCLR_Type::OVERRUN0
uint8_t OVERRUN0
Definition: dac.h:159
DAC_STATUS_Type::READY0
uint8_t READY0
Definition: dac.h:321
DAC_RESULT_Type
Definition: dac.h:505
DAC_EVCTRL_Type::STARTEI1
uint8_t STARTEI1
Definition: dac.h:98
Dac::DBGCTRL
__IO DAC_DBGCTRL_Type DBGCTRL
Offset: 0x18 (R/W 8) Debug Control.
Definition: dac.h:536
DAC_EVCTRL_Type::EMPTYEO1
uint8_t EMPTYEO1
Definition: dac.h:100
DAC_CTRLB_Type
Definition: dac.h:65
DAC_SYNCBUSY_Type::DATA
uint32_t DATA
Definition: dac.h:369
DAC_INTFLAG_Type::OVERRUN
__I uint8_t OVERRUN
Definition: dac.h:278
Dac::EVCTRL
__IO DAC_EVCTRL_Type EVCTRL
Offset: 0x02 (R/W 8) Event Control.
Definition: dac.h:526
DAC_CTRLB_Type::reg
uint8_t reg
Definition: dac.h:71
DAC_CTRLA_Type::reg
uint8_t reg
Definition: dac.h:50
DAC_INTENSET_Type::RESRDY
uint8_t RESRDY
Definition: dac.h:221
DAC_INTENSET_Type::UNDERRUN0
uint8_t UNDERRUN0
Definition: dac.h:209
DAC_SYNCBUSY_Type::DATA0
uint32_t DATA0
Definition: dac.h:361
DAC_DBGCTRL_Type::DBGRUN
uint8_t DBGRUN
Definition: dac.h:489
DAC_INTENCLR_Type::RESRDY1
uint8_t RESRDY1
Definition: dac.h:158
DAC_INTENSET_Type::UNDERRUN
uint8_t UNDERRUN
Definition: dac.h:219
DAC_INTENCLR_Type::OVERRUN
uint8_t OVERRUN
Definition: dac.h:166
DAC_EVCTRL_Type::RESRDYEO
uint8_t RESRDYEO
Definition: dac.h:110
DAC_INTENSET_Type::OVERRUN
uint8_t OVERRUN
Definition: dac.h:222
DAC_STATUS_Type::READY1
uint8_t READY1
Definition: dac.h:322
DAC_INTFLAG_Type::EMPTY0
__I uint8_t EMPTY0
Definition: dac.h:267
Dac
DAC hardware registers.
Definition: dac.h:523
DAC_INTENCLR_Type::EMPTY1
uint8_t EMPTY1
Definition: dac.h:156
DAC_INTENSET_Type::RESRDY1
uint8_t RESRDY1
Definition: dac.h:214
DAC_SYNCBUSY_Type::DATABUF1
uint32_t DATABUF1
Definition: dac.h:364
DAC_RESULT_Type::RESULT
uint16_t RESULT
Definition: dac.h:507
DAC_INTFLAG_Type::RESRDY1
__I uint8_t RESRDY1
Definition: dac.h:270
DAC_DBGCTRL_Type::reg
uint8_t reg
Definition: dac.h:492
DAC_STATUS_Type::reg
uint8_t reg
Definition: dac.h:332
DAC_INTENCLR_Type::EMPTY0
uint8_t EMPTY0
Definition: dac.h:155
DAC_EVCTRL_Type::EMPTYEO
uint8_t EMPTYEO
Definition: dac.h:108
DAC_EVCTRL_Type::reg
uint8_t reg
Definition: dac.h:112
DAC_CTRLB_Type::DIFF
uint8_t DIFF
Definition: dac.h:67
DAC_DACCTRL_Type::CCTRL
uint16_t CCTRL
Definition: dac.h:406
DAC_INTENSET_Type::EMPTY
uint8_t EMPTY
Definition: dac.h:220
DAC_CTRLA_Type::SWRST
uint8_t SWRST
Definition: dac.h:46
DAC_INTENSET_Type::EMPTY1
uint8_t EMPTY1
Definition: dac.h:212
DAC_INTFLAG_Type::RESRDY
__I uint8_t RESRDY
Definition: dac.h:277
DAC_EVCTRL_Type::INVEI1
uint8_t INVEI1
Definition: dac.h:102
DAC_INTFLAG_Type::OVERRUN0
__I uint8_t OVERRUN0
Definition: dac.h:271
DAC_INTENCLR_Type::RESRDY0
uint8_t RESRDY0
Definition: dac.h:157
DAC_DACCTRL_Type::RUNSTDBY
uint16_t RUNSTDBY
Definition: dac.h:409
DAC_INTENSET_Type::OVERRUN1
uint8_t OVERRUN1
Definition: dac.h:216
DAC_INTENCLR_Type::OVERRUN1
uint8_t OVERRUN1
Definition: dac.h:160
DAC_DATABUF_Type
Definition: dac.h:469
DAC_INTFLAG_Type::EMPTY
__I uint8_t EMPTY
Definition: dac.h:276
DAC_DACCTRL_Type::LEFTADJ
uint16_t LEFTADJ
Definition: dac.h:404
DAC_EVCTRL_Type::RESRDYEO0
uint8_t RESRDYEO0
Definition: dac.h:103
DAC_INTENSET_Type::reg
uint8_t reg
Definition: dac.h:224
DAC_DATA_Type
Definition: dac.h:451
Dac::CTRLB
__IO DAC_CTRLB_Type CTRLB
Offset: 0x01 (R/W 8) Control B.
Definition: dac.h:525
DAC_SYNCBUSY_Type::DATABUF0
uint32_t DATABUF0
Definition: dac.h:363
DAC_EVCTRL_Type::EMPTYEO0
uint8_t EMPTYEO0
Definition: dac.h:99
DAC_SYNCBUSY_Type::reg
uint32_t reg
Definition: dac.h:373
DAC_INTENCLR_Type::UNDERRUN1
uint8_t UNDERRUN1
Definition: dac.h:154
DAC_INTFLAG_Type
Definition: dac.h:263
DAC_INTENSET_Type::EMPTY0
uint8_t EMPTY0
Definition: dac.h:211
DAC_SYNCBUSY_Type::SWRST
uint32_t SWRST
Definition: dac.h:359
Dac::INTENCLR
__IO DAC_INTENCLR_Type INTENCLR
Offset: 0x04 (R/W 8) Interrupt Enable Clear.
Definition: dac.h:528
DAC_DACCTRL_Type::REFRESH
uint16_t REFRESH
Definition: dac.h:411
DAC_STATUS_Type
Definition: dac.h:319
DAC_INTFLAG_Type::OVERRUN1
__I uint8_t OVERRUN1
Definition: dac.h:272
DAC_INTFLAG_Type::RESRDY0
__I uint8_t RESRDY0
Definition: dac.h:269
DAC_INTENCLR_Type
Definition: dac.h:151
DAC_SYNCBUSY_Type
Definition: dac.h:357
Dac::CTRLA
__IO DAC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A.
Definition: dac.h:524
DAC_DATA_Type::reg
uint16_t reg
Definition: dac.h:455
DAC_DACCTRL_Type::DITHER
uint16_t DITHER
Definition: dac.h:410
DAC_DATABUF_Type::DATABUF
uint16_t DATABUF
Definition: dac.h:471
DAC_STATUS_Type::EOC1
uint8_t EOC1
Definition: dac.h:324
Dac::INTFLAG
__IO DAC_INTFLAG_Type INTFLAG
Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear.
Definition: dac.h:530
DAC_EVCTRL_Type::STARTEI0
uint8_t STARTEI0
Definition: dac.h:97
DAC_EVCTRL_Type
Definition: dac.h:95
DAC_EVCTRL_Type::RESRDYEO1
uint8_t RESRDYEO1
Definition: dac.h:104
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
DAC_SYNCBUSY_Type::DATA1
uint32_t DATA1
Definition: dac.h:362
DAC_CTRLB_Type::REFSEL
uint8_t REFSEL
Definition: dac.h:68
DAC_RESULT_Type::reg
uint16_t reg
Definition: dac.h:509
DAC_CTRLA_Type::ENABLE
uint8_t ENABLE
Definition: dac.h:47
DAC_INTFLAG_Type::reg
uint8_t reg
Definition: dac.h:280
DAC_INTENSET_Type
Definition: dac.h:207
DAC_EVCTRL_Type::STARTEI
uint8_t STARTEI
Definition: dac.h:107
DAC_STATUS_Type::EOC
uint8_t EOC
Definition: dac.h:329
DAC_DATA_Type::DATA
uint16_t DATA
Definition: dac.h:453
DAC_SYNCBUSY_Type::DATABUF
uint32_t DATABUF
Definition: dac.h:370
DAC_INTENCLR_Type::RESRDY
uint8_t RESRDY
Definition: dac.h:165
DAC_DACCTRL_Type::FEXT
uint16_t FEXT
Definition: dac.h:408
DAC_INTFLAG_Type::EMPTY1
__I uint8_t EMPTY1
Definition: dac.h:268
DAC_INTFLAG_Type::UNDERRUN1
__I uint8_t UNDERRUN1
Definition: dac.h:266
DAC_INTENCLR_Type::EMPTY
uint8_t EMPTY
Definition: dac.h:164
DAC_DACCTRL_Type::reg
uint16_t reg
Definition: dac.h:415
Dac::INTENSET
__IO DAC_INTENSET_Type INTENSET
Offset: 0x05 (R/W 8) Interrupt Enable Set.
Definition: dac.h:529
DAC_STATUS_Type::READY
uint8_t READY
Definition: dac.h:328
DAC_DATABUF_Type::reg
uint16_t reg
Definition: dac.h:473
DAC_EVCTRL_Type::INVEI
uint8_t INVEI
Definition: dac.h:109