SAME54P20A Test Project
pac.h
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1 
30 #ifndef _SAME54_PAC_COMPONENT_
31 #define _SAME54_PAC_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define PAC_U2120
40 #define REV_PAC 0x120
41 
42 /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t PERID:16;
47  uint32_t KEY:8;
48  uint32_t :8;
49  } bit;
50  uint32_t reg;
52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
53 
54 #define PAC_WRCTRL_OFFSET 0x00
55 #define PAC_WRCTRL_RESETVALUE _U_(0x00000000)
57 #define PAC_WRCTRL_PERID_Pos 0
58 #define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
59 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
60 #define PAC_WRCTRL_KEY_Pos 16
61 #define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
62 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
63 #define PAC_WRCTRL_KEY_OFF_Val _U_(0x0)
64 #define PAC_WRCTRL_KEY_CLR_Val _U_(0x1)
65 #define PAC_WRCTRL_KEY_SET_Val _U_(0x2)
66 #define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3)
67 #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)
68 #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)
69 #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)
70 #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)
71 #define PAC_WRCTRL_MASK _U_(0x00FFFFFF)
73 /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
75 typedef union {
76  struct {
77  uint8_t ERREO:1;
78  uint8_t :7;
79  } bit;
80  uint8_t reg;
82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
83 
84 #define PAC_EVCTRL_OFFSET 0x04
85 #define PAC_EVCTRL_RESETVALUE _U_(0x00)
87 #define PAC_EVCTRL_ERREO_Pos 0
88 #define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
89 #define PAC_EVCTRL_MASK _U_(0x01)
91 /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
93 typedef union {
94  struct {
95  uint8_t ERR:1;
96  uint8_t :7;
97  } bit;
98  uint8_t reg;
100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
101 
102 #define PAC_INTENCLR_OFFSET 0x08
103 #define PAC_INTENCLR_RESETVALUE _U_(0x00)
105 #define PAC_INTENCLR_ERR_Pos 0
106 #define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
107 #define PAC_INTENCLR_MASK _U_(0x01)
109 /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
111 typedef union {
112  struct {
113  uint8_t ERR:1;
114  uint8_t :7;
115  } bit;
116  uint8_t reg;
118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
119 
120 #define PAC_INTENSET_OFFSET 0x09
121 #define PAC_INTENSET_RESETVALUE _U_(0x00)
123 #define PAC_INTENSET_ERR_Pos 0
124 #define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos)
125 #define PAC_INTENSET_MASK _U_(0x01)
127 /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
129 typedef union { // __I to avoid read-modify-write on write-to-clear register
130  struct {
131  __I uint32_t FLASH_:1;
132  __I uint32_t FLASH_ALT_:1;
133  __I uint32_t SEEPROM_:1;
134  __I uint32_t RAMCM4S_:1;
135  __I uint32_t RAMPPPDSU_:1;
136  __I uint32_t RAMDMAWR_:1;
137  __I uint32_t RAMDMACICM_:1;
138  __I uint32_t HPB0_:1;
139  __I uint32_t HPB1_:1;
140  __I uint32_t HPB2_:1;
141  __I uint32_t HPB3_:1;
142  __I uint32_t PUKCC_:1;
143  __I uint32_t SDHC0_:1;
144  __I uint32_t SDHC1_:1;
145  __I uint32_t QSPI_:1;
146  __I uint32_t BKUPRAM_:1;
147  __I uint32_t :16;
148  } bit;
149  uint32_t reg;
151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
152 
153 #define PAC_INTFLAGAHB_OFFSET 0x10
154 #define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000)
156 #define PAC_INTFLAGAHB_FLASH_Pos 0
157 #define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
158 #define PAC_INTFLAGAHB_FLASH_ALT_Pos 1
159 #define PAC_INTFLAGAHB_FLASH_ALT (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
160 #define PAC_INTFLAGAHB_SEEPROM_Pos 2
161 #define PAC_INTFLAGAHB_SEEPROM (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
162 #define PAC_INTFLAGAHB_RAMCM4S_Pos 3
163 #define PAC_INTFLAGAHB_RAMCM4S (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
164 #define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4
165 #define PAC_INTFLAGAHB_RAMPPPDSU (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
166 #define PAC_INTFLAGAHB_RAMDMAWR_Pos 5
167 #define PAC_INTFLAGAHB_RAMDMAWR (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
168 #define PAC_INTFLAGAHB_RAMDMACICM_Pos 6
169 #define PAC_INTFLAGAHB_RAMDMACICM (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
170 #define PAC_INTFLAGAHB_HPB0_Pos 7
171 #define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
172 #define PAC_INTFLAGAHB_HPB1_Pos 8
173 #define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
174 #define PAC_INTFLAGAHB_HPB2_Pos 9
175 #define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
176 #define PAC_INTFLAGAHB_HPB3_Pos 10
177 #define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
178 #define PAC_INTFLAGAHB_PUKCC_Pos 11
179 #define PAC_INTFLAGAHB_PUKCC (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
180 #define PAC_INTFLAGAHB_SDHC0_Pos 12
181 #define PAC_INTFLAGAHB_SDHC0 (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
182 #define PAC_INTFLAGAHB_SDHC1_Pos 13
183 #define PAC_INTFLAGAHB_SDHC1 (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
184 #define PAC_INTFLAGAHB_QSPI_Pos 14
185 #define PAC_INTFLAGAHB_QSPI (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
186 #define PAC_INTFLAGAHB_BKUPRAM_Pos 15
187 #define PAC_INTFLAGAHB_BKUPRAM (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
188 #define PAC_INTFLAGAHB_MASK _U_(0x0000FFFF)
190 /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
192 typedef union { // __I to avoid read-modify-write on write-to-clear register
193  struct {
194  __I uint32_t PAC_:1;
195  __I uint32_t PM_:1;
196  __I uint32_t MCLK_:1;
197  __I uint32_t RSTC_:1;
198  __I uint32_t OSCCTRL_:1;
199  __I uint32_t OSC32KCTRL_:1;
200  __I uint32_t SUPC_:1;
201  __I uint32_t GCLK_:1;
202  __I uint32_t WDT_:1;
203  __I uint32_t RTC_:1;
204  __I uint32_t EIC_:1;
205  __I uint32_t FREQM_:1;
206  __I uint32_t SERCOM0_:1;
207  __I uint32_t SERCOM1_:1;
208  __I uint32_t TC0_:1;
209  __I uint32_t TC1_:1;
210  __I uint32_t :16;
211  } bit;
212  uint32_t reg;
214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
215 
216 #define PAC_INTFLAGA_OFFSET 0x14
217 #define PAC_INTFLAGA_RESETVALUE _U_(0x00000000)
219 #define PAC_INTFLAGA_PAC_Pos 0
220 #define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
221 #define PAC_INTFLAGA_PM_Pos 1
222 #define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
223 #define PAC_INTFLAGA_MCLK_Pos 2
224 #define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
225 #define PAC_INTFLAGA_RSTC_Pos 3
226 #define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
227 #define PAC_INTFLAGA_OSCCTRL_Pos 4
228 #define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
229 #define PAC_INTFLAGA_OSC32KCTRL_Pos 5
230 #define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
231 #define PAC_INTFLAGA_SUPC_Pos 6
232 #define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
233 #define PAC_INTFLAGA_GCLK_Pos 7
234 #define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
235 #define PAC_INTFLAGA_WDT_Pos 8
236 #define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
237 #define PAC_INTFLAGA_RTC_Pos 9
238 #define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
239 #define PAC_INTFLAGA_EIC_Pos 10
240 #define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
241 #define PAC_INTFLAGA_FREQM_Pos 11
242 #define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
243 #define PAC_INTFLAGA_SERCOM0_Pos 12
244 #define PAC_INTFLAGA_SERCOM0 (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
245 #define PAC_INTFLAGA_SERCOM1_Pos 13
246 #define PAC_INTFLAGA_SERCOM1 (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
247 #define PAC_INTFLAGA_TC0_Pos 14
248 #define PAC_INTFLAGA_TC0 (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
249 #define PAC_INTFLAGA_TC1_Pos 15
250 #define PAC_INTFLAGA_TC1 (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
251 #define PAC_INTFLAGA_MASK _U_(0x0000FFFF)
253 /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
254 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
255 typedef union { // __I to avoid read-modify-write on write-to-clear register
256  struct {
257  __I uint32_t USB_:1;
258  __I uint32_t DSU_:1;
259  __I uint32_t NVMCTRL_:1;
260  __I uint32_t CMCC_:1;
261  __I uint32_t PORT_:1;
262  __I uint32_t DMAC_:1;
263  __I uint32_t HMATRIX_:1;
264  __I uint32_t EVSYS_:1;
265  __I uint32_t :1;
266  __I uint32_t SERCOM2_:1;
267  __I uint32_t SERCOM3_:1;
268  __I uint32_t TCC0_:1;
269  __I uint32_t TCC1_:1;
270  __I uint32_t TC2_:1;
271  __I uint32_t TC3_:1;
272  __I uint32_t :1;
273  __I uint32_t RAMECC_:1;
274  __I uint32_t :15;
275  } bit;
276  uint32_t reg;
278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
279 
280 #define PAC_INTFLAGB_OFFSET 0x18
281 #define PAC_INTFLAGB_RESETVALUE _U_(0x00000000)
283 #define PAC_INTFLAGB_USB_Pos 0
284 #define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
285 #define PAC_INTFLAGB_DSU_Pos 1
286 #define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
287 #define PAC_INTFLAGB_NVMCTRL_Pos 2
288 #define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
289 #define PAC_INTFLAGB_CMCC_Pos 3
290 #define PAC_INTFLAGB_CMCC (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
291 #define PAC_INTFLAGB_PORT_Pos 4
292 #define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
293 #define PAC_INTFLAGB_DMAC_Pos 5
294 #define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
295 #define PAC_INTFLAGB_HMATRIX_Pos 6
296 #define PAC_INTFLAGB_HMATRIX (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
297 #define PAC_INTFLAGB_EVSYS_Pos 7
298 #define PAC_INTFLAGB_EVSYS (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
299 #define PAC_INTFLAGB_SERCOM2_Pos 9
300 #define PAC_INTFLAGB_SERCOM2 (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
301 #define PAC_INTFLAGB_SERCOM3_Pos 10
302 #define PAC_INTFLAGB_SERCOM3 (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
303 #define PAC_INTFLAGB_TCC0_Pos 11
304 #define PAC_INTFLAGB_TCC0 (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
305 #define PAC_INTFLAGB_TCC1_Pos 12
306 #define PAC_INTFLAGB_TCC1 (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
307 #define PAC_INTFLAGB_TC2_Pos 13
308 #define PAC_INTFLAGB_TC2 (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
309 #define PAC_INTFLAGB_TC3_Pos 14
310 #define PAC_INTFLAGB_TC3 (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
311 #define PAC_INTFLAGB_RAMECC_Pos 16
312 #define PAC_INTFLAGB_RAMECC (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
313 #define PAC_INTFLAGB_MASK _U_(0x00017EFF)
315 /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
316 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
317 typedef union { // __I to avoid read-modify-write on write-to-clear register
318  struct {
319  __I uint32_t CAN0_:1;
320  __I uint32_t CAN1_:1;
321  __I uint32_t GMAC_:1;
322  __I uint32_t TCC2_:1;
323  __I uint32_t TCC3_:1;
324  __I uint32_t TC4_:1;
325  __I uint32_t TC5_:1;
326  __I uint32_t PDEC_:1;
327  __I uint32_t AC_:1;
328  __I uint32_t AES_:1;
329  __I uint32_t TRNG_:1;
330  __I uint32_t ICM_:1;
331  __I uint32_t PUKCC_:1;
332  __I uint32_t QSPI_:1;
333  __I uint32_t CCL_:1;
334  __I uint32_t :17;
335  } bit;
336  uint32_t reg;
338 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
339 
340 #define PAC_INTFLAGC_OFFSET 0x1C
341 #define PAC_INTFLAGC_RESETVALUE _U_(0x00000000)
343 #define PAC_INTFLAGC_CAN0_Pos 0
344 #define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos)
345 #define PAC_INTFLAGC_CAN1_Pos 1
346 #define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos)
347 #define PAC_INTFLAGC_GMAC_Pos 2
348 #define PAC_INTFLAGC_GMAC (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos)
349 #define PAC_INTFLAGC_TCC2_Pos 3
350 #define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
351 #define PAC_INTFLAGC_TCC3_Pos 4
352 #define PAC_INTFLAGC_TCC3 (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
353 #define PAC_INTFLAGC_TC4_Pos 5
354 #define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
355 #define PAC_INTFLAGC_TC5_Pos 6
356 #define PAC_INTFLAGC_TC5 (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
357 #define PAC_INTFLAGC_PDEC_Pos 7
358 #define PAC_INTFLAGC_PDEC (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
359 #define PAC_INTFLAGC_AC_Pos 8
360 #define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
361 #define PAC_INTFLAGC_AES_Pos 9
362 #define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
363 #define PAC_INTFLAGC_TRNG_Pos 10
364 #define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
365 #define PAC_INTFLAGC_ICM_Pos 11
366 #define PAC_INTFLAGC_ICM (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
367 #define PAC_INTFLAGC_PUKCC_Pos 12
368 #define PAC_INTFLAGC_PUKCC (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
369 #define PAC_INTFLAGC_QSPI_Pos 13
370 #define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
371 #define PAC_INTFLAGC_CCL_Pos 14
372 #define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
373 #define PAC_INTFLAGC_MASK _U_(0x00007FFF)
375 /* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */
376 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
377 typedef union { // __I to avoid read-modify-write on write-to-clear register
378  struct {
379  __I uint32_t SERCOM4_:1;
380  __I uint32_t SERCOM5_:1;
381  __I uint32_t SERCOM6_:1;
382  __I uint32_t SERCOM7_:1;
383  __I uint32_t TCC4_:1;
384  __I uint32_t TC6_:1;
385  __I uint32_t TC7_:1;
386  __I uint32_t ADC0_:1;
387  __I uint32_t ADC1_:1;
388  __I uint32_t DAC_:1;
389  __I uint32_t I2S_:1;
390  __I uint32_t PCC_:1;
391  __I uint32_t :20;
392  } bit;
393  uint32_t reg;
395 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
396 
397 #define PAC_INTFLAGD_OFFSET 0x20
398 #define PAC_INTFLAGD_RESETVALUE _U_(0x00000000)
400 #define PAC_INTFLAGD_SERCOM4_Pos 0
401 #define PAC_INTFLAGD_SERCOM4 (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
402 #define PAC_INTFLAGD_SERCOM5_Pos 1
403 #define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
404 #define PAC_INTFLAGD_SERCOM6_Pos 2
405 #define PAC_INTFLAGD_SERCOM6 (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
406 #define PAC_INTFLAGD_SERCOM7_Pos 3
407 #define PAC_INTFLAGD_SERCOM7 (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
408 #define PAC_INTFLAGD_TCC4_Pos 4
409 #define PAC_INTFLAGD_TCC4 (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
410 #define PAC_INTFLAGD_TC6_Pos 5
411 #define PAC_INTFLAGD_TC6 (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
412 #define PAC_INTFLAGD_TC7_Pos 6
413 #define PAC_INTFLAGD_TC7 (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
414 #define PAC_INTFLAGD_ADC0_Pos 7
415 #define PAC_INTFLAGD_ADC0 (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
416 #define PAC_INTFLAGD_ADC1_Pos 8
417 #define PAC_INTFLAGD_ADC1 (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
418 #define PAC_INTFLAGD_DAC_Pos 9
419 #define PAC_INTFLAGD_DAC (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
420 #define PAC_INTFLAGD_I2S_Pos 10
421 #define PAC_INTFLAGD_I2S (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
422 #define PAC_INTFLAGD_PCC_Pos 11
423 #define PAC_INTFLAGD_PCC (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
424 #define PAC_INTFLAGD_MASK _U_(0x00000FFF)
426 /* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */
427 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
428 typedef union {
429  struct {
430  uint32_t PAC_:1;
431  uint32_t PM_:1;
432  uint32_t MCLK_:1;
433  uint32_t RSTC_:1;
434  uint32_t OSCCTRL_:1;
435  uint32_t OSC32KCTRL_:1;
436  uint32_t SUPC_:1;
437  uint32_t GCLK_:1;
438  uint32_t WDT_:1;
439  uint32_t RTC_:1;
440  uint32_t EIC_:1;
441  uint32_t FREQM_:1;
442  uint32_t SERCOM0_:1;
443  uint32_t SERCOM1_:1;
444  uint32_t TC0_:1;
445  uint32_t TC1_:1;
446  uint32_t :16;
447  } bit;
448  uint32_t reg;
450 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
451 
452 #define PAC_STATUSA_OFFSET 0x34
453 #define PAC_STATUSA_RESETVALUE _U_(0x00010000)
455 #define PAC_STATUSA_PAC_Pos 0
456 #define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos)
457 #define PAC_STATUSA_PM_Pos 1
458 #define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos)
459 #define PAC_STATUSA_MCLK_Pos 2
460 #define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
461 #define PAC_STATUSA_RSTC_Pos 3
462 #define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
463 #define PAC_STATUSA_OSCCTRL_Pos 4
464 #define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
465 #define PAC_STATUSA_OSC32KCTRL_Pos 5
466 #define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
467 #define PAC_STATUSA_SUPC_Pos 6
468 #define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
469 #define PAC_STATUSA_GCLK_Pos 7
470 #define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
471 #define PAC_STATUSA_WDT_Pos 8
472 #define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos)
473 #define PAC_STATUSA_RTC_Pos 9
474 #define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos)
475 #define PAC_STATUSA_EIC_Pos 10
476 #define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos)
477 #define PAC_STATUSA_FREQM_Pos 11
478 #define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
479 #define PAC_STATUSA_SERCOM0_Pos 12
480 #define PAC_STATUSA_SERCOM0 (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
481 #define PAC_STATUSA_SERCOM1_Pos 13
482 #define PAC_STATUSA_SERCOM1 (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
483 #define PAC_STATUSA_TC0_Pos 14
484 #define PAC_STATUSA_TC0 (_U_(0x1) << PAC_STATUSA_TC0_Pos)
485 #define PAC_STATUSA_TC1_Pos 15
486 #define PAC_STATUSA_TC1 (_U_(0x1) << PAC_STATUSA_TC1_Pos)
487 #define PAC_STATUSA_MASK _U_(0x0000FFFF)
489 /* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */
490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
491 typedef union {
492  struct {
493  uint32_t USB_:1;
494  uint32_t DSU_:1;
495  uint32_t NVMCTRL_:1;
496  uint32_t CMCC_:1;
497  uint32_t PORT_:1;
498  uint32_t DMAC_:1;
499  uint32_t HMATRIX_:1;
500  uint32_t EVSYS_:1;
501  uint32_t :1;
502  uint32_t SERCOM2_:1;
503  uint32_t SERCOM3_:1;
504  uint32_t TCC0_:1;
505  uint32_t TCC1_:1;
506  uint32_t TC2_:1;
507  uint32_t TC3_:1;
508  uint32_t :1;
509  uint32_t RAMECC_:1;
510  uint32_t :15;
511  } bit;
512  uint32_t reg;
514 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
515 
516 #define PAC_STATUSB_OFFSET 0x38
517 #define PAC_STATUSB_RESETVALUE _U_(0x00000002)
519 #define PAC_STATUSB_USB_Pos 0
520 #define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos)
521 #define PAC_STATUSB_DSU_Pos 1
522 #define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos)
523 #define PAC_STATUSB_NVMCTRL_Pos 2
524 #define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
525 #define PAC_STATUSB_CMCC_Pos 3
526 #define PAC_STATUSB_CMCC (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
527 #define PAC_STATUSB_PORT_Pos 4
528 #define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos)
529 #define PAC_STATUSB_DMAC_Pos 5
530 #define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
531 #define PAC_STATUSB_HMATRIX_Pos 6
532 #define PAC_STATUSB_HMATRIX (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
533 #define PAC_STATUSB_EVSYS_Pos 7
534 #define PAC_STATUSB_EVSYS (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
535 #define PAC_STATUSB_SERCOM2_Pos 9
536 #define PAC_STATUSB_SERCOM2 (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
537 #define PAC_STATUSB_SERCOM3_Pos 10
538 #define PAC_STATUSB_SERCOM3 (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
539 #define PAC_STATUSB_TCC0_Pos 11
540 #define PAC_STATUSB_TCC0 (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
541 #define PAC_STATUSB_TCC1_Pos 12
542 #define PAC_STATUSB_TCC1 (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
543 #define PAC_STATUSB_TC2_Pos 13
544 #define PAC_STATUSB_TC2 (_U_(0x1) << PAC_STATUSB_TC2_Pos)
545 #define PAC_STATUSB_TC3_Pos 14
546 #define PAC_STATUSB_TC3 (_U_(0x1) << PAC_STATUSB_TC3_Pos)
547 #define PAC_STATUSB_RAMECC_Pos 16
548 #define PAC_STATUSB_RAMECC (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
549 #define PAC_STATUSB_MASK _U_(0x00017EFF)
551 /* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */
552 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
553 typedef union {
554  struct {
555  uint32_t CAN0_:1;
556  uint32_t CAN1_:1;
557  uint32_t GMAC_:1;
558  uint32_t TCC2_:1;
559  uint32_t TCC3_:1;
560  uint32_t TC4_:1;
561  uint32_t TC5_:1;
562  uint32_t PDEC_:1;
563  uint32_t AC_:1;
564  uint32_t AES_:1;
565  uint32_t TRNG_:1;
566  uint32_t ICM_:1;
567  uint32_t PUKCC_:1;
568  uint32_t QSPI_:1;
569  uint32_t CCL_:1;
570  uint32_t :17;
571  } bit;
572  uint32_t reg;
574 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
575 
576 #define PAC_STATUSC_OFFSET 0x3C
577 #define PAC_STATUSC_RESETVALUE _U_(0x00000000)
579 #define PAC_STATUSC_CAN0_Pos 0
580 #define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos)
581 #define PAC_STATUSC_CAN1_Pos 1
582 #define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos)
583 #define PAC_STATUSC_GMAC_Pos 2
584 #define PAC_STATUSC_GMAC (_U_(0x1) << PAC_STATUSC_GMAC_Pos)
585 #define PAC_STATUSC_TCC2_Pos 3
586 #define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
587 #define PAC_STATUSC_TCC3_Pos 4
588 #define PAC_STATUSC_TCC3 (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
589 #define PAC_STATUSC_TC4_Pos 5
590 #define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos)
591 #define PAC_STATUSC_TC5_Pos 6
592 #define PAC_STATUSC_TC5 (_U_(0x1) << PAC_STATUSC_TC5_Pos)
593 #define PAC_STATUSC_PDEC_Pos 7
594 #define PAC_STATUSC_PDEC (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
595 #define PAC_STATUSC_AC_Pos 8
596 #define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos)
597 #define PAC_STATUSC_AES_Pos 9
598 #define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos)
599 #define PAC_STATUSC_TRNG_Pos 10
600 #define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
601 #define PAC_STATUSC_ICM_Pos 11
602 #define PAC_STATUSC_ICM (_U_(0x1) << PAC_STATUSC_ICM_Pos)
603 #define PAC_STATUSC_PUKCC_Pos 12
604 #define PAC_STATUSC_PUKCC (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
605 #define PAC_STATUSC_QSPI_Pos 13
606 #define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
607 #define PAC_STATUSC_CCL_Pos 14
608 #define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
609 #define PAC_STATUSC_MASK _U_(0x00007FFF)
611 /* -------- PAC_STATUSD : (PAC Offset: 0x40) (R/ 32) Peripheral write protection status - Bridge D -------- */
612 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
613 typedef union {
614  struct {
615  uint32_t SERCOM4_:1;
616  uint32_t SERCOM5_:1;
617  uint32_t SERCOM6_:1;
618  uint32_t SERCOM7_:1;
619  uint32_t TCC4_:1;
620  uint32_t TC6_:1;
621  uint32_t TC7_:1;
622  uint32_t ADC0_:1;
623  uint32_t ADC1_:1;
624  uint32_t DAC_:1;
625  uint32_t I2S_:1;
626  uint32_t PCC_:1;
627  uint32_t :20;
628  } bit;
629  uint32_t reg;
631 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
632 
633 #define PAC_STATUSD_OFFSET 0x40
634 #define PAC_STATUSD_RESETVALUE _U_(0x00000000)
636 #define PAC_STATUSD_SERCOM4_Pos 0
637 #define PAC_STATUSD_SERCOM4 (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
638 #define PAC_STATUSD_SERCOM5_Pos 1
639 #define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
640 #define PAC_STATUSD_SERCOM6_Pos 2
641 #define PAC_STATUSD_SERCOM6 (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
642 #define PAC_STATUSD_SERCOM7_Pos 3
643 #define PAC_STATUSD_SERCOM7 (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
644 #define PAC_STATUSD_TCC4_Pos 4
645 #define PAC_STATUSD_TCC4 (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
646 #define PAC_STATUSD_TC6_Pos 5
647 #define PAC_STATUSD_TC6 (_U_(0x1) << PAC_STATUSD_TC6_Pos)
648 #define PAC_STATUSD_TC7_Pos 6
649 #define PAC_STATUSD_TC7 (_U_(0x1) << PAC_STATUSD_TC7_Pos)
650 #define PAC_STATUSD_ADC0_Pos 7
651 #define PAC_STATUSD_ADC0 (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
652 #define PAC_STATUSD_ADC1_Pos 8
653 #define PAC_STATUSD_ADC1 (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
654 #define PAC_STATUSD_DAC_Pos 9
655 #define PAC_STATUSD_DAC (_U_(0x1) << PAC_STATUSD_DAC_Pos)
656 #define PAC_STATUSD_I2S_Pos 10
657 #define PAC_STATUSD_I2S (_U_(0x1) << PAC_STATUSD_I2S_Pos)
658 #define PAC_STATUSD_PCC_Pos 11
659 #define PAC_STATUSD_PCC (_U_(0x1) << PAC_STATUSD_PCC_Pos)
660 #define PAC_STATUSD_MASK _U_(0x00000FFF)
663 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
664 typedef struct {
667  RoReg8 Reserved1[0x3];
670  RoReg8 Reserved2[0x6];
676  RoReg8 Reserved3[0x10];
681 } Pac;
682 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
683 
686 #endif /* _SAME54_PAC_COMPONENT_ */
PAC_INTFLAGAHB_Type::HPB2_
__I uint32_t HPB2_
Definition: pac.h:140
PAC_STATUSD_Type::reg
uint32_t reg
Definition: pac.h:629
PAC_INTFLAGB_Type::HMATRIX_
__I uint32_t HMATRIX_
Definition: pac.h:263
Pac::EVCTRL
__IO PAC_EVCTRL_Type EVCTRL
Offset: 0x04 (R/W 8) Event control.
Definition: pac.h:666
PAC_INTFLAGA_Type::SUPC_
__I uint32_t SUPC_
Definition: pac.h:200
PAC_WRCTRL_Type::KEY
uint32_t KEY
Definition: pac.h:47
PAC_STATUSD_Type::ADC0_
uint32_t ADC0_
Definition: pac.h:622
PAC_STATUSA_Type::GCLK_
uint32_t GCLK_
Definition: pac.h:437
PAC_INTFLAGA_Type::TC1_
__I uint32_t TC1_
Definition: pac.h:209
PAC_STATUSB_Type::reg
uint32_t reg
Definition: pac.h:512
PAC_INTFLAGAHB_Type::BKUPRAM_
__I uint32_t BKUPRAM_
Definition: pac.h:146
PAC_INTFLAGAHB_Type::RAMPPPDSU_
__I uint32_t RAMPPPDSU_
Definition: pac.h:135
PAC_INTFLAGB_Type::SERCOM2_
__I uint32_t SERCOM2_
Definition: pac.h:266
PAC_INTFLAGC_Type
Definition: pac.h:317
PAC_INTFLAGD_Type::DAC_
__I uint32_t DAC_
Definition: pac.h:388
PAC_INTFLAGAHB_Type::FLASH_ALT_
__I uint32_t FLASH_ALT_
Definition: pac.h:132
PAC_INTFLAGAHB_Type::SDHC1_
__I uint32_t SDHC1_
Definition: pac.h:144
PAC_STATUSA_Type::TC1_
uint32_t TC1_
Definition: pac.h:445
PAC_STATUSD_Type::TC7_
uint32_t TC7_
Definition: pac.h:621
PAC_STATUSC_Type::ICM_
uint32_t ICM_
Definition: pac.h:566
PAC_INTFLAGAHB_Type::RAMDMAWR_
__I uint32_t RAMDMAWR_
Definition: pac.h:136
PAC_WRCTRL_Type::PERID
uint32_t PERID
Definition: pac.h:46
PAC_INTFLAGC_Type::CAN0_
__I uint32_t CAN0_
Definition: pac.h:319
PAC_INTFLAGC_Type::TCC3_
__I uint32_t TCC3_
Definition: pac.h:323
PAC_INTFLAGAHB_Type::SEEPROM_
__I uint32_t SEEPROM_
Definition: pac.h:133
Pac::STATUSA
__I PAC_STATUSA_Type STATUSA
Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A.
Definition: pac.h:677
PAC_STATUSD_Type::SERCOM6_
uint32_t SERCOM6_
Definition: pac.h:617
PAC_EVCTRL_Type::ERREO
uint8_t ERREO
Definition: pac.h:77
PAC_STATUSC_Type::PUKCC_
uint32_t PUKCC_
Definition: pac.h:567
Pac::INTENCLR
__IO PAC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt enable clear.
Definition: pac.h:668
PAC_INTFLAGA_Type::PAC_
__I uint32_t PAC_
Definition: pac.h:194
PAC_INTFLAGAHB_Type::SDHC0_
__I uint32_t SDHC0_
Definition: pac.h:143
PAC_STATUSA_Type
Definition: pac.h:428
PAC_STATUSC_Type::TRNG_
uint32_t TRNG_
Definition: pac.h:565
PAC_INTFLAGA_Type::GCLK_
__I uint32_t GCLK_
Definition: pac.h:201
PAC_STATUSC_Type::CCL_
uint32_t CCL_
Definition: pac.h:569
PAC_STATUSD_Type::I2S_
uint32_t I2S_
Definition: pac.h:625
PAC_INTFLAGB_Type::SERCOM3_
__I uint32_t SERCOM3_
Definition: pac.h:267
PAC_INTFLAGB_Type::TCC1_
__I uint32_t TCC1_
Definition: pac.h:269
PAC_INTFLAGD_Type::TCC4_
__I uint32_t TCC4_
Definition: pac.h:383
PAC_STATUSA_Type::MCLK_
uint32_t MCLK_
Definition: pac.h:432
PAC_STATUSD_Type
Definition: pac.h:613
PAC_STATUSD_Type::TC6_
uint32_t TC6_
Definition: pac.h:620
PAC_INTFLAGAHB_Type
Definition: pac.h:129
PAC_INTFLAGAHB_Type::RAMDMACICM_
__I uint32_t RAMDMACICM_
Definition: pac.h:137
PAC_STATUSB_Type
Definition: pac.h:491
Pac::INTFLAGC
__IO PAC_INTFLAGC_Type INTFLAGC
Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C.
Definition: pac.h:674
PAC_STATUSA_Type::RSTC_
uint32_t RSTC_
Definition: pac.h:433
PAC_INTENCLR_Type::ERR
uint8_t ERR
Definition: pac.h:95
PAC_STATUSD_Type::PCC_
uint32_t PCC_
Definition: pac.h:626
PAC_STATUSA_Type::RTC_
uint32_t RTC_
Definition: pac.h:439
PAC_INTFLAGAHB_Type::HPB1_
__I uint32_t HPB1_
Definition: pac.h:139
PAC_INTFLAGD_Type::ADC1_
__I uint32_t ADC1_
Definition: pac.h:387
PAC_STATUSB_Type::TCC0_
uint32_t TCC0_
Definition: pac.h:504
PAC_INTFLAGA_Type::OSC32KCTRL_
__I uint32_t OSC32KCTRL_
Definition: pac.h:199
PAC_STATUSD_Type::DAC_
uint32_t DAC_
Definition: pac.h:624
PAC_STATUSA_Type::OSC32KCTRL_
uint32_t OSC32KCTRL_
Definition: pac.h:435
PAC_INTFLAGA_Type::RSTC_
__I uint32_t RSTC_
Definition: pac.h:197
PAC_INTFLAGA_Type::TC0_
__I uint32_t TC0_
Definition: pac.h:208
PAC_INTFLAGB_Type::DSU_
__I uint32_t DSU_
Definition: pac.h:258
PAC_INTFLAGA_Type::uint32_t
__I uint32_t
Definition: pac.h:210
PAC_INTFLAGA_Type::MCLK_
__I uint32_t MCLK_
Definition: pac.h:196
PAC_INTFLAGC_Type::TCC2_
__I uint32_t TCC2_
Definition: pac.h:322
PAC_INTFLAGC_Type::QSPI_
__I uint32_t QSPI_
Definition: pac.h:332
PAC_INTFLAGB_Type::PORT_
__I uint32_t PORT_
Definition: pac.h:261
PAC_INTFLAGC_Type::PDEC_
__I uint32_t PDEC_
Definition: pac.h:326
PAC_INTFLAGB_Type::CMCC_
__I uint32_t CMCC_
Definition: pac.h:260
PAC_INTFLAGB_Type::uint32_t
__I uint32_t
Definition: pac.h:265
PAC_STATUSA_Type::EIC_
uint32_t EIC_
Definition: pac.h:440
PAC_STATUSC_Type::TC5_
uint32_t TC5_
Definition: pac.h:561
PAC_WRCTRL_Type
Definition: pac.h:44
PAC_STATUSB_Type::USB_
uint32_t USB_
Definition: pac.h:493
PAC_INTFLAGB_Type::DMAC_
__I uint32_t DMAC_
Definition: pac.h:262
PAC_INTFLAGC_Type::AES_
__I uint32_t AES_
Definition: pac.h:328
PAC_INTENSET_Type::ERR
uint8_t ERR
Definition: pac.h:113
PAC_STATUSC_Type::reg
uint32_t reg
Definition: pac.h:572
PAC_STATUSC_Type::CAN1_
uint32_t CAN1_
Definition: pac.h:556
PAC_INTFLAGAHB_Type::FLASH_
__I uint32_t FLASH_
Definition: pac.h:131
Pac
PAC hardware registers.
Definition: pac.h:664
PAC_INTFLAGB_Type::EVSYS_
__I uint32_t EVSYS_
Definition: pac.h:264
PAC_STATUSB_Type::TC2_
uint32_t TC2_
Definition: pac.h:506
PAC_STATUSB_Type::SERCOM2_
uint32_t SERCOM2_
Definition: pac.h:502
PAC_STATUSD_Type::SERCOM5_
uint32_t SERCOM5_
Definition: pac.h:616
PAC_STATUSA_Type::SERCOM0_
uint32_t SERCOM0_
Definition: pac.h:442
PAC_INTFLAGD_Type::uint32_t
__I uint32_t
Definition: pac.h:391
PAC_STATUSB_Type::TC3_
uint32_t TC3_
Definition: pac.h:507
PAC_STATUSC_Type::TC4_
uint32_t TC4_
Definition: pac.h:560
Pac::INTFLAGA
__IO PAC_INTFLAGA_Type INTFLAGA
Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A.
Definition: pac.h:672
PAC_STATUSD_Type::TCC4_
uint32_t TCC4_
Definition: pac.h:619
PAC_INTFLAGAHB_Type::HPB3_
__I uint32_t HPB3_
Definition: pac.h:141
PAC_STATUSC_Type::AES_
uint32_t AES_
Definition: pac.h:564
PAC_INTFLAGC_Type::CCL_
__I uint32_t CCL_
Definition: pac.h:333
PAC_STATUSA_Type::TC0_
uint32_t TC0_
Definition: pac.h:444
PAC_INTFLAGB_Type::reg
uint32_t reg
Definition: pac.h:276
PAC_INTFLAGA_Type
Definition: pac.h:192
PAC_STATUSB_Type::SERCOM3_
uint32_t SERCOM3_
Definition: pac.h:503
PAC_INTFLAGD_Type::reg
uint32_t reg
Definition: pac.h:393
PAC_STATUSC_Type::AC_
uint32_t AC_
Definition: pac.h:563
PAC_INTFLAGA_Type::SERCOM1_
__I uint32_t SERCOM1_
Definition: pac.h:207
PAC_INTFLAGA_Type::WDT_
__I uint32_t WDT_
Definition: pac.h:202
PAC_STATUSA_Type::SERCOM1_
uint32_t SERCOM1_
Definition: pac.h:443
PAC_STATUSB_Type::RAMECC_
uint32_t RAMECC_
Definition: pac.h:509
PAC_INTFLAGC_Type::uint32_t
__I uint32_t
Definition: pac.h:334
PAC_INTFLAGC_Type::TC4_
__I uint32_t TC4_
Definition: pac.h:324
PAC_STATUSB_Type::EVSYS_
uint32_t EVSYS_
Definition: pac.h:500
PAC_STATUSC_Type::TCC2_
uint32_t TCC2_
Definition: pac.h:558
PAC_INTFLAGA_Type::RTC_
__I uint32_t RTC_
Definition: pac.h:203
PAC_INTFLAGC_Type::TC5_
__I uint32_t TC5_
Definition: pac.h:325
PAC_INTFLAGB_Type::RAMECC_
__I uint32_t RAMECC_
Definition: pac.h:273
PAC_STATUSD_Type::SERCOM4_
uint32_t SERCOM4_
Definition: pac.h:615
PAC_INTFLAGB_Type::NVMCTRL_
__I uint32_t NVMCTRL_
Definition: pac.h:259
PAC_INTFLAGA_Type::OSCCTRL_
__I uint32_t OSCCTRL_
Definition: pac.h:198
PAC_INTFLAGAHB_Type::HPB0_
__I uint32_t HPB0_
Definition: pac.h:138
PAC_INTFLAGD_Type::TC6_
__I uint32_t TC6_
Definition: pac.h:384
PAC_INTFLAGC_Type::GMAC_
__I uint32_t GMAC_
Definition: pac.h:321
Pac::STATUSB
__I PAC_STATUSB_Type STATUSB
Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B.
Definition: pac.h:678
PAC_INTFLAGAHB_Type::uint32_t
__I uint32_t
Definition: pac.h:147
Pac::INTFLAGB
__IO PAC_INTFLAGB_Type INTFLAGB
Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B.
Definition: pac.h:673
PAC_STATUSC_Type::PDEC_
uint32_t PDEC_
Definition: pac.h:562
PAC_STATUSC_Type::QSPI_
uint32_t QSPI_
Definition: pac.h:568
Pac::STATUSC
__I PAC_STATUSC_Type STATUSC
Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C.
Definition: pac.h:679
PAC_WRCTRL_Type::reg
uint32_t reg
Definition: pac.h:50
PAC_STATUSB_Type::CMCC_
uint32_t CMCC_
Definition: pac.h:496
PAC_INTFLAGA_Type::EIC_
__I uint32_t EIC_
Definition: pac.h:204
PAC_STATUSD_Type::ADC1_
uint32_t ADC1_
Definition: pac.h:623
PAC_STATUSB_Type::PORT_
uint32_t PORT_
Definition: pac.h:497
PAC_INTFLAGAHB_Type::PUKCC_
__I uint32_t PUKCC_
Definition: pac.h:142
Pac::INTENSET
__IO PAC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt enable set.
Definition: pac.h:669
PAC_STATUSB_Type::DSU_
uint32_t DSU_
Definition: pac.h:494
PAC_STATUSA_Type::PM_
uint32_t PM_
Definition: pac.h:431
PAC_INTFLAGD_Type::SERCOM7_
__I uint32_t SERCOM7_
Definition: pac.h:382
PAC_INTFLAGD_Type
Definition: pac.h:377
PAC_STATUSC_Type::CAN0_
uint32_t CAN0_
Definition: pac.h:555
PAC_INTENSET_Type
Definition: pac.h:111
PAC_INTFLAGAHB_Type::reg
uint32_t reg
Definition: pac.h:149
PAC_INTFLAGB_Type::TC3_
__I uint32_t TC3_
Definition: pac.h:271
PAC_INTFLAGC_Type::AC_
__I uint32_t AC_
Definition: pac.h:327
PAC_STATUSB_Type::DMAC_
uint32_t DMAC_
Definition: pac.h:498
PAC_INTFLAGA_Type::FREQM_
__I uint32_t FREQM_
Definition: pac.h:205
PAC_INTFLAGA_Type::SERCOM0_
__I uint32_t SERCOM0_
Definition: pac.h:206
PAC_INTENCLR_Type::reg
uint8_t reg
Definition: pac.h:98
Pac::INTFLAGD
__IO PAC_INTFLAGD_Type INTFLAGD
Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D.
Definition: pac.h:675
PAC_STATUSA_Type::FREQM_
uint32_t FREQM_
Definition: pac.h:441
PAC_INTFLAGAHB_Type::QSPI_
__I uint32_t QSPI_
Definition: pac.h:145
PAC_STATUSB_Type::HMATRIX_
uint32_t HMATRIX_
Definition: pac.h:499
PAC_INTFLAGD_Type::I2S_
__I uint32_t I2S_
Definition: pac.h:389
Pac::STATUSD
__I PAC_STATUSD_Type STATUSD
Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D.
Definition: pac.h:680
PAC_STATUSA_Type::reg
uint32_t reg
Definition: pac.h:448
PAC_STATUSC_Type::TCC3_
uint32_t TCC3_
Definition: pac.h:559
PAC_INTFLAGD_Type::TC7_
__I uint32_t TC7_
Definition: pac.h:385
PAC_INTFLAGD_Type::ADC0_
__I uint32_t ADC0_
Definition: pac.h:386
PAC_INTFLAGA_Type::reg
uint32_t reg
Definition: pac.h:212
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
PAC_INTFLAGB_Type::TCC0_
__I uint32_t TCC0_
Definition: pac.h:268
PAC_STATUSC_Type::GMAC_
uint32_t GMAC_
Definition: pac.h:557
PAC_INTFLAGC_Type::ICM_
__I uint32_t ICM_
Definition: pac.h:330
PAC_STATUSB_Type::NVMCTRL_
uint32_t NVMCTRL_
Definition: pac.h:495
PAC_STATUSB_Type::TCC1_
uint32_t TCC1_
Definition: pac.h:505
PAC_INTFLAGB_Type::USB_
__I uint32_t USB_
Definition: pac.h:257
PAC_STATUSA_Type::WDT_
uint32_t WDT_
Definition: pac.h:438
PAC_INTFLAGB_Type
Definition: pac.h:255
PAC_INTENSET_Type::reg
uint8_t reg
Definition: pac.h:116
PAC_INTFLAGD_Type::SERCOM5_
__I uint32_t SERCOM5_
Definition: pac.h:380
PAC_INTFLAGC_Type::TRNG_
__I uint32_t TRNG_
Definition: pac.h:329
PAC_INTFLAGAHB_Type::RAMCM4S_
__I uint32_t RAMCM4S_
Definition: pac.h:134
PAC_INTFLAGB_Type::TC2_
__I uint32_t TC2_
Definition: pac.h:270
PAC_EVCTRL_Type::reg
uint8_t reg
Definition: pac.h:80
PAC_INTENCLR_Type
Definition: pac.h:93
PAC_STATUSC_Type
Definition: pac.h:553
PAC_INTFLAGD_Type::SERCOM4_
__I uint32_t SERCOM4_
Definition: pac.h:379
Pac::INTFLAGAHB
__IO PAC_INTFLAGAHB_Type INTFLAGAHB
Offset: 0x10 (R/W 32) Bridge interrupt flag status.
Definition: pac.h:671
PAC_INTFLAGD_Type::SERCOM6_
__I uint32_t SERCOM6_
Definition: pac.h:381
PAC_STATUSA_Type::SUPC_
uint32_t SUPC_
Definition: pac.h:436
Pac::WRCTRL
__IO PAC_WRCTRL_Type WRCTRL
Offset: 0x00 (R/W 32) Write control.
Definition: pac.h:665
PAC_INTFLAGC_Type::PUKCC_
__I uint32_t PUKCC_
Definition: pac.h:331
PAC_INTFLAGC_Type::CAN1_
__I uint32_t CAN1_
Definition: pac.h:320
PAC_STATUSD_Type::SERCOM7_
uint32_t SERCOM7_
Definition: pac.h:618
PAC_INTFLAGD_Type::PCC_
__I uint32_t PCC_
Definition: pac.h:390
PAC_INTFLAGA_Type::PM_
__I uint32_t PM_
Definition: pac.h:195
PAC_EVCTRL_Type
Definition: pac.h:75
PAC_STATUSA_Type::PAC_
uint32_t PAC_
Definition: pac.h:430
PAC_INTFLAGC_Type::reg
uint32_t reg
Definition: pac.h:336
PAC_STATUSA_Type::OSCCTRL_
uint32_t OSCCTRL_
Definition: pac.h:434