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30 #ifndef _SAME54_OSCCTRL_INSTANCE_
31 #define _SAME54_OSCCTRL_INSTANCE_
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_OSCCTRL_EVCTRL (0x40001000)
36 #define REG_OSCCTRL_INTENCLR (0x40001004)
37 #define REG_OSCCTRL_INTENSET (0x40001008)
38 #define REG_OSCCTRL_INTFLAG (0x4000100C)
39 #define REG_OSCCTRL_STATUS (0x40001010)
40 #define REG_OSCCTRL_XOSCCTRL0 (0x40001014)
41 #define REG_OSCCTRL_XOSCCTRL1 (0x40001018)
42 #define REG_OSCCTRL_DFLLCTRLA (0x4000101C)
43 #define REG_OSCCTRL_DFLLCTRLB (0x40001020)
44 #define REG_OSCCTRL_DFLLVAL (0x40001024)
45 #define REG_OSCCTRL_DFLLMUL (0x40001028)
46 #define REG_OSCCTRL_DFLLSYNC (0x4000102C)
47 #define REG_OSCCTRL_DPLLCTRLA0 (0x40001030)
48 #define REG_OSCCTRL_DPLLRATIO0 (0x40001034)
49 #define REG_OSCCTRL_DPLLCTRLB0 (0x40001038)
50 #define REG_OSCCTRL_DPLLSYNCBUSY0 (0x4000103C)
51 #define REG_OSCCTRL_DPLLSTATUS0 (0x40001040)
52 #define REG_OSCCTRL_DPLLCTRLA1 (0x40001044)
53 #define REG_OSCCTRL_DPLLRATIO1 (0x40001048)
54 #define REG_OSCCTRL_DPLLCTRLB1 (0x4000104C)
55 #define REG_OSCCTRL_DPLLSYNCBUSY1 (0x40001050)
56 #define REG_OSCCTRL_DPLLSTATUS1 (0x40001054)
58 #define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001000UL)
59 #define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001004UL)
60 #define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001008UL)
61 #define REG_OSCCTRL_INTFLAG (*(RwReg *)0x4000100CUL)
62 #define REG_OSCCTRL_STATUS (*(RoReg *)0x40001010UL)
63 #define REG_OSCCTRL_XOSCCTRL0 (*(RwReg *)0x40001014UL)
64 #define REG_OSCCTRL_XOSCCTRL1 (*(RwReg *)0x40001018UL)
65 #define REG_OSCCTRL_DFLLCTRLA (*(RwReg8 *)0x4000101CUL)
66 #define REG_OSCCTRL_DFLLCTRLB (*(RwReg8 *)0x40001020UL)
67 #define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40001024UL)
68 #define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001028UL)
69 #define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x4000102CUL)
70 #define REG_OSCCTRL_DPLLCTRLA0 (*(RwReg8 *)0x40001030UL)
71 #define REG_OSCCTRL_DPLLRATIO0 (*(RwReg *)0x40001034UL)
72 #define REG_OSCCTRL_DPLLCTRLB0 (*(RwReg *)0x40001038UL)
73 #define REG_OSCCTRL_DPLLSYNCBUSY0 (*(RoReg *)0x4000103CUL)
74 #define REG_OSCCTRL_DPLLSTATUS0 (*(RoReg *)0x40001040UL)
75 #define REG_OSCCTRL_DPLLCTRLA1 (*(RwReg8 *)0x40001044UL)
76 #define REG_OSCCTRL_DPLLRATIO1 (*(RwReg *)0x40001048UL)
77 #define REG_OSCCTRL_DPLLCTRLB1 (*(RwReg *)0x4000104CUL)
78 #define REG_OSCCTRL_DPLLSYNCBUSY1 (*(RoReg *)0x40001050UL)
79 #define REG_OSCCTRL_DPLLSTATUS1 (*(RoReg *)0x40001054UL)
83 #define OSCCTRL_DFLLS_NUM 1 // Number of DFLLs
84 #define OSCCTRL_DFLL_IMPLEMENTED 1 // DFLL implemented
85 #define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0 // DFLL48M bias test mode implemented
86 #define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2 // Size COARSE DAC STEP
87 #define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32 // DFLL48M Frequency Coarse Reset Value (Before Calibration)
88 #define OSCCTRL_DFLL48M_COARSE_SIZE 6 // Size COARSE CALIBRATION
89 #define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1 // Run oscillator at reset
90 #define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2 // Size FINE DAC STEP
91 #define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128 // DFLL48M Frequency Fine Reset Value (Before Calibration)
92 #define OSCCTRL_DFLL48M_FINE_SIZE 8 // Size FINE CALIBRATION
93 #define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
94 #define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
95 #define OSCCTRL_DFLL48M_TCAL_SIZE 4 // Size TEMP CALIBRATION
96 #define OSCCTRL_DFLL48M_TCBIAS_SIZE 2 // Size TC BIAS CALIBRATION
97 #define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3 // Size TEST POINT SELECTOR
98 #define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1 // Enable Wait Lock Feature
99 #define OSCCTRL_DPLLS_NUM 2 // Number of DPLLs
100 #define OSCCTRL_DPLL0_IMPLEMENTED 1 // DPLL0 implemented
101 #define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
102 #define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1 // DPLL0 OCC Implemented
103 #define OSCCTRL_DPLL1_IMPLEMENTED 1 // DPLL1 implemented
104 #define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
105 #define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0 // DPLL1 OCC Implemented
106 #define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
107 #define OSCCTRL_GCLK_ID_FDPLL0 1 // Index of Generic Clock for DPLL0
108 #define OSCCTRL_GCLK_ID_FDPLL1 2 // Index of Generic Clock for DPLL1
109 #define OSCCTRL_GCLK_ID_FDPLL032K 3 // Index of Generic Clock for DPLL0 32K
110 #define OSCCTRL_GCLK_ID_FDPLL132K 3 // Index of Generic Clock for DPLL1 32K
111 #define OSCCTRL_OSC16M_IMPLEMENTED 0 // OSC16M implemented
112 #define OSCCTRL_OSC48M_IMPLEMENTED 0 // OSC48M implemented
113 #define OSCCTRL_OSC48M_NUM 1
114 #define OSCCTRL_RCOSCS_NUM 1 // Number of RCOSCs (min 1)
115 #define OSCCTRL_XOSCS_NUM 2 // Number of XOSCs
116 #define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
117 #define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
118 #define OSCCTRL_XOSC0_IMPLEMENTED 1 // XOSC0 implemented
119 #define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
120 #define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
121 #define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
122 #define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
123 #define OSCCTRL_XOSC1_IMPLEMENTED 1 // XOSC1 implemented
124 #define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
125 #define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
126 #define OSCCTRL_DFLL48M_VERSION 0x100
127 #define OSCCTRL_FDPLL_VERSION 0x100
128 #define OSCCTRL_XOSC_VERSION 0x100