SAME54P20A Test Project
qspi.h
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1 
30 #ifndef _SAME54_QSPI_COMPONENT_
31 #define _SAME54_QSPI_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define QSPI_U2008
40 #define REV_QSPI 0x163
41 
42 /* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t SWRST:1;
47  uint32_t ENABLE:1;
48  uint32_t :22;
49  uint32_t LASTXFER:1;
50  uint32_t :7;
51  } bit;
52  uint32_t reg;
54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
55 
56 #define QSPI_CTRLA_OFFSET 0x00
57 #define QSPI_CTRLA_RESETVALUE _U_(0x00000000)
59 #define QSPI_CTRLA_SWRST_Pos 0
60 #define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
61 #define QSPI_CTRLA_ENABLE_Pos 1
62 #define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
63 #define QSPI_CTRLA_LASTXFER_Pos 24
64 #define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
65 #define QSPI_CTRLA_MASK _U_(0x01000003)
67 /* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */
68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
69 typedef union {
70  struct {
71  uint32_t MODE:1;
72  uint32_t LOOPEN:1;
73  uint32_t WDRBT:1;
74  uint32_t SMEMREG:1;
75  uint32_t CSMODE:2;
76  uint32_t :2;
77  uint32_t DATALEN:4;
78  uint32_t :4;
79  uint32_t DLYBCT:8;
80  uint32_t DLYCS:8;
81  } bit;
82  uint32_t reg;
84 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
85 
86 #define QSPI_CTRLB_OFFSET 0x04
87 #define QSPI_CTRLB_RESETVALUE _U_(0x00000000)
89 #define QSPI_CTRLB_MODE_Pos 0
90 #define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
91 #define QSPI_CTRLB_MODE_SPI_Val _U_(0x0)
92 #define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1)
93 #define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
94 #define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
95 #define QSPI_CTRLB_LOOPEN_Pos 1
96 #define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
97 #define QSPI_CTRLB_WDRBT_Pos 2
98 #define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
99 #define QSPI_CTRLB_SMEMREG_Pos 3
100 #define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
101 #define QSPI_CTRLB_CSMODE_Pos 4
102 #define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
103 #define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
104 #define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0)
105 #define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1)
106 #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2)
107 #define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
108 #define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
109 #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
110 #define QSPI_CTRLB_DATALEN_Pos 8
111 #define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
112 #define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
113 #define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0)
114 #define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1)
115 #define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2)
116 #define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3)
117 #define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4)
118 #define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5)
119 #define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6)
120 #define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7)
121 #define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8)
122 #define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
123 #define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
124 #define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
125 #define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
126 #define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
127 #define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
128 #define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
129 #define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
130 #define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
131 #define QSPI_CTRLB_DLYBCT_Pos 16
132 #define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
133 #define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
134 #define QSPI_CTRLB_DLYCS_Pos 24
135 #define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
136 #define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
137 #define QSPI_CTRLB_MASK _U_(0xFFFF0F3F)
139 /* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */
140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
141 typedef union {
142  struct {
143  uint32_t CPOL:1;
144  uint32_t CPHA:1;
145  uint32_t :6;
146  uint32_t BAUD:8;
147  uint32_t DLYBS:8;
148  uint32_t :8;
149  } bit;
150  uint32_t reg;
152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
153 
154 #define QSPI_BAUD_OFFSET 0x08
155 #define QSPI_BAUD_RESETVALUE _U_(0x00000000)
157 #define QSPI_BAUD_CPOL_Pos 0
158 #define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
159 #define QSPI_BAUD_CPHA_Pos 1
160 #define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
161 #define QSPI_BAUD_BAUD_Pos 8
162 #define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
163 #define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
164 #define QSPI_BAUD_DLYBS_Pos 16
165 #define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
166 #define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
167 #define QSPI_BAUD_MASK _U_(0x00FFFF03)
169 /* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/ 32) Receive Data -------- */
170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
171 typedef union {
172  struct {
173  uint32_t DATA:16;
174  uint32_t :16;
175  } bit;
176  uint32_t reg;
178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
179 
180 #define QSPI_RXDATA_OFFSET 0x0C
181 #define QSPI_RXDATA_RESETVALUE _U_(0x00000000)
183 #define QSPI_RXDATA_DATA_Pos 0
184 #define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
185 #define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
186 #define QSPI_RXDATA_MASK _U_(0x0000FFFF)
188 /* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */
189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
190 typedef union {
191  struct {
192  uint32_t DATA:16;
193  uint32_t :16;
194  } bit;
195  uint32_t reg;
197 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
198 
199 #define QSPI_TXDATA_OFFSET 0x10
200 #define QSPI_TXDATA_RESETVALUE _U_(0x00000000)
202 #define QSPI_TXDATA_DATA_Pos 0
203 #define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
204 #define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
205 #define QSPI_TXDATA_MASK _U_(0x0000FFFF)
207 /* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */
208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
209 typedef union {
210  struct {
211  uint32_t RXC:1;
212  uint32_t DRE:1;
213  uint32_t TXC:1;
214  uint32_t ERROR:1;
215  uint32_t :4;
216  uint32_t CSRISE:1;
217  uint32_t :1;
218  uint32_t INSTREND:1;
219  uint32_t :21;
220  } bit;
221  uint32_t reg;
223 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
224 
225 #define QSPI_INTENCLR_OFFSET 0x14
226 #define QSPI_INTENCLR_RESETVALUE _U_(0x00000000)
228 #define QSPI_INTENCLR_RXC_Pos 0
229 #define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
230 #define QSPI_INTENCLR_DRE_Pos 1
231 #define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
232 #define QSPI_INTENCLR_TXC_Pos 2
233 #define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
234 #define QSPI_INTENCLR_ERROR_Pos 3
235 #define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
236 #define QSPI_INTENCLR_CSRISE_Pos 8
237 #define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
238 #define QSPI_INTENCLR_INSTREND_Pos 10
239 #define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
240 #define QSPI_INTENCLR_MASK _U_(0x0000050F)
242 /* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */
243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
244 typedef union {
245  struct {
246  uint32_t RXC:1;
247  uint32_t DRE:1;
248  uint32_t TXC:1;
249  uint32_t ERROR:1;
250  uint32_t :4;
251  uint32_t CSRISE:1;
252  uint32_t :1;
253  uint32_t INSTREND:1;
254  uint32_t :21;
255  } bit;
256  uint32_t reg;
258 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
259 
260 #define QSPI_INTENSET_OFFSET 0x18
261 #define QSPI_INTENSET_RESETVALUE _U_(0x00000000)
263 #define QSPI_INTENSET_RXC_Pos 0
264 #define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
265 #define QSPI_INTENSET_DRE_Pos 1
266 #define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
267 #define QSPI_INTENSET_TXC_Pos 2
268 #define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
269 #define QSPI_INTENSET_ERROR_Pos 3
270 #define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
271 #define QSPI_INTENSET_CSRISE_Pos 8
272 #define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
273 #define QSPI_INTENSET_INSTREND_Pos 10
274 #define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
275 #define QSPI_INTENSET_MASK _U_(0x0000050F)
277 /* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */
278 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
279 typedef union { // __I to avoid read-modify-write on write-to-clear register
280  struct {
281  __I uint32_t RXC:1;
282  __I uint32_t DRE:1;
283  __I uint32_t TXC:1;
284  __I uint32_t ERROR:1;
285  __I uint32_t :4;
286  __I uint32_t CSRISE:1;
287  __I uint32_t :1;
288  __I uint32_t INSTREND:1;
289  __I uint32_t :21;
290  } bit;
291  uint32_t reg;
293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
294 
295 #define QSPI_INTFLAG_OFFSET 0x1C
296 #define QSPI_INTFLAG_RESETVALUE _U_(0x00000000)
298 #define QSPI_INTFLAG_RXC_Pos 0
299 #define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
300 #define QSPI_INTFLAG_DRE_Pos 1
301 #define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
302 #define QSPI_INTFLAG_TXC_Pos 2
303 #define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
304 #define QSPI_INTFLAG_ERROR_Pos 3
305 #define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
306 #define QSPI_INTFLAG_CSRISE_Pos 8
307 #define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
308 #define QSPI_INTFLAG_INSTREND_Pos 10
309 #define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
310 #define QSPI_INTFLAG_MASK _U_(0x0000050F)
312 /* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/ 32) Status Register -------- */
313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
314 typedef union {
315  struct {
316  uint32_t :1;
317  uint32_t ENABLE:1;
318  uint32_t :7;
319  uint32_t CSSTATUS:1;
320  uint32_t :22;
321  } bit;
322  uint32_t reg;
324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
325 
326 #define QSPI_STATUS_OFFSET 0x20
327 #define QSPI_STATUS_RESETVALUE _U_(0x00000200)
329 #define QSPI_STATUS_ENABLE_Pos 1
330 #define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
331 #define QSPI_STATUS_CSSTATUS_Pos 9
332 #define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
333 #define QSPI_STATUS_MASK _U_(0x00000202)
335 /* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */
336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
337 typedef union {
338  struct {
339  uint32_t ADDR:32;
340  } bit;
341  uint32_t reg;
343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
344 
345 #define QSPI_INSTRADDR_OFFSET 0x30
346 #define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000)
348 #define QSPI_INSTRADDR_ADDR_Pos 0
349 #define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
350 #define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
351 #define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF)
353 /* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */
354 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
355 typedef union {
356  struct {
357  uint32_t INSTR:8;
358  uint32_t :8;
359  uint32_t OPTCODE:8;
360  uint32_t :8;
361  } bit;
362  uint32_t reg;
364 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
365 
366 #define QSPI_INSTRCTRL_OFFSET 0x34
367 #define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000)
369 #define QSPI_INSTRCTRL_INSTR_Pos 0
370 #define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
371 #define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
372 #define QSPI_INSTRCTRL_OPTCODE_Pos 16
373 #define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
374 #define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
375 #define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF)
377 /* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */
378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
379 typedef union {
380  struct {
381  uint32_t WIDTH:3;
382  uint32_t :1;
383  uint32_t INSTREN:1;
384  uint32_t ADDREN:1;
385  uint32_t OPTCODEEN:1;
386  uint32_t DATAEN:1;
387  uint32_t OPTCODELEN:2;
388  uint32_t ADDRLEN:1;
389  uint32_t :1;
390  uint32_t TFRTYPE:2;
391  uint32_t CRMODE:1;
392  uint32_t DDREN:1;
393  uint32_t DUMMYLEN:5;
394  uint32_t :11;
395  } bit;
396  uint32_t reg;
398 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
399 
400 #define QSPI_INSTRFRAME_OFFSET 0x38
401 #define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000)
403 #define QSPI_INSTRFRAME_WIDTH_Pos 0
404 #define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
405 #define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
406 #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0)
407 #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1)
408 #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2)
409 #define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3)
410 #define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4)
411 #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5)
412 #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6)
413 #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
414 #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
415 #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
416 #define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
417 #define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
418 #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
419 #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
420 #define QSPI_INSTRFRAME_INSTREN_Pos 4
421 #define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
422 #define QSPI_INSTRFRAME_ADDREN_Pos 5
423 #define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
424 #define QSPI_INSTRFRAME_OPTCODEEN_Pos 6
425 #define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
426 #define QSPI_INSTRFRAME_DATAEN_Pos 7
427 #define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
428 #define QSPI_INSTRFRAME_OPTCODELEN_Pos 8
429 #define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
430 #define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
431 #define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0)
432 #define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1)
433 #define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2)
434 #define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3)
435 #define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
436 #define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
437 #define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
438 #define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
439 #define QSPI_INSTRFRAME_ADDRLEN_Pos 10
440 #define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
441 #define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0)
442 #define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1)
443 #define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
444 #define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
445 #define QSPI_INSTRFRAME_TFRTYPE_Pos 12
446 #define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
447 #define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
448 #define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0)
449 #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1)
450 #define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2)
451 #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3)
452 #define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
453 #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
454 #define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
455 #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
456 #define QSPI_INSTRFRAME_CRMODE_Pos 14
457 #define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
458 #define QSPI_INSTRFRAME_DDREN_Pos 15
459 #define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
460 #define QSPI_INSTRFRAME_DUMMYLEN_Pos 16
461 #define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
462 #define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
463 #define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7)
465 /* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */
466 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
467 typedef union {
468  struct {
469  uint32_t ENABLE:1;
470  uint32_t RANDOMDIS:1;
471  uint32_t :30;
472  } bit;
473  uint32_t reg;
475 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
476 
477 #define QSPI_SCRAMBCTRL_OFFSET 0x40
478 #define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000)
480 #define QSPI_SCRAMBCTRL_ENABLE_Pos 0
481 #define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
482 #define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1
483 #define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
484 #define QSPI_SCRAMBCTRL_MASK _U_(0x00000003)
486 /* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */
487 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
488 typedef union {
489  struct {
490  uint32_t KEY:32;
491  } bit;
492  uint32_t reg;
494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
495 
496 #define QSPI_SCRAMBKEY_OFFSET 0x44
497 #define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000)
499 #define QSPI_SCRAMBKEY_KEY_Pos 0
500 #define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
501 #define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
502 #define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF)
505 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
506 typedef struct {
516  RoReg8 Reserved1[0xC];
520  RoReg8 Reserved2[0x4];
523 } Qspi;
524 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
525 
528 #endif /* _SAME54_QSPI_COMPONENT_ */
QSPI_INTFLAG_Type::INSTREND
__I uint32_t INSTREND
Definition: qspi.h:288
QSPI_STATUS_Type::reg
uint32_t reg
Definition: qspi.h:322
QSPI_RXDATA_Type
Definition: qspi.h:171
QSPI_CTRLB_Type::WDRBT
uint32_t WDRBT
Definition: qspi.h:73
QSPI_INTENSET_Type::ERROR
uint32_t ERROR
Definition: qspi.h:249
QSPI_INTENSET_Type::CSRISE
uint32_t CSRISE
Definition: qspi.h:251
QSPI_INSTRFRAME_Type::ADDRLEN
uint32_t ADDRLEN
Definition: qspi.h:388
QSPI_INTENCLR_Type
Definition: qspi.h:209
QSPI_INSTRFRAME_Type::ADDREN
uint32_t ADDREN
Definition: qspi.h:384
QSPI_INTFLAG_Type::CSRISE
__I uint32_t CSRISE
Definition: qspi.h:286
QSPI_CTRLB_Type::MODE
uint32_t MODE
Definition: qspi.h:71
Qspi::INTENSET
__IO QSPI_INTENSET_Type INTENSET
Offset: 0x18 (R/W 32) Interrupt Enable Set.
Definition: qspi.h:513
Qspi::CTRLA
__IO QSPI_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
Definition: qspi.h:507
QSPI_CTRLA_Type
Definition: qspi.h:44
QSPI_INSTRFRAME_Type::WIDTH
uint32_t WIDTH
Definition: qspi.h:381
QSPI_INTENCLR_Type::reg
uint32_t reg
Definition: qspi.h:221
QSPI_INTENCLR_Type::RXC
uint32_t RXC
Definition: qspi.h:211
QSPI_INTENCLR_Type::TXC
uint32_t TXC
Definition: qspi.h:213
Qspi::INSTRFRAME
__IO QSPI_INSTRFRAME_Type INSTRFRAME
Offset: 0x38 (R/W 32) Instruction Frame.
Definition: qspi.h:519
QSPI_INTENCLR_Type::INSTREND
uint32_t INSTREND
Definition: qspi.h:218
QSPI_INTENCLR_Type::ERROR
uint32_t ERROR
Definition: qspi.h:214
QSPI_SCRAMBKEY_Type
Definition: qspi.h:488
QSPI_CTRLB_Type::CSMODE
uint32_t CSMODE
Definition: qspi.h:75
QSPI_INTENSET_Type::TXC
uint32_t TXC
Definition: qspi.h:248
QSPI_INTENSET_Type
Definition: qspi.h:244
Qspi::INTENCLR
__IO QSPI_INTENCLR_Type INTENCLR
Offset: 0x14 (R/W 32) Interrupt Enable Clear.
Definition: qspi.h:512
QSPI_STATUS_Type::CSSTATUS
uint32_t CSSTATUS
Definition: qspi.h:319
QSPI_INTENSET_Type::DRE
uint32_t DRE
Definition: qspi.h:247
QSPI_INSTRFRAME_Type::reg
uint32_t reg
Definition: qspi.h:396
QSPI_INSTRADDR_Type
Definition: qspi.h:337
QSPI_INTFLAG_Type::ERROR
__I uint32_t ERROR
Definition: qspi.h:284
QSPI_INSTRFRAME_Type::OPTCODEEN
uint32_t OPTCODEEN
Definition: qspi.h:385
Qspi::RXDATA
__I QSPI_RXDATA_Type RXDATA
Offset: 0x0C (R/ 32) Receive Data.
Definition: qspi.h:510
QSPI_CTRLB_Type::DLYBCT
uint32_t DLYBCT
Definition: qspi.h:79
QSPI_INSTRFRAME_Type
Definition: qspi.h:379
QSPI_INTFLAG_Type::TXC
__I uint32_t TXC
Definition: qspi.h:283
QSPI_CTRLB_Type::DLYCS
uint32_t DLYCS
Definition: qspi.h:80
QSPI_INSTRFRAME_Type::TFRTYPE
uint32_t TFRTYPE
Definition: qspi.h:390
QSPI_INSTRFRAME_Type::OPTCODELEN
uint32_t OPTCODELEN
Definition: qspi.h:387
QSPI_RXDATA_Type::reg
uint32_t reg
Definition: qspi.h:176
QSPI_RXDATA_Type::DATA
uint32_t DATA
Definition: qspi.h:173
QSPI_BAUD_Type::BAUD
uint32_t BAUD
Definition: qspi.h:146
QSPI_CTRLB_Type::DATALEN
uint32_t DATALEN
Definition: qspi.h:77
Qspi::INSTRADDR
__IO QSPI_INSTRADDR_Type INSTRADDR
Offset: 0x30 (R/W 32) Instruction Address.
Definition: qspi.h:517
QSPI_INSTRFRAME_Type::INSTREN
uint32_t INSTREN
Definition: qspi.h:383
QSPI_INSTRADDR_Type::ADDR
uint32_t ADDR
Definition: qspi.h:339
QSPI_INTFLAG_Type
Definition: qspi.h:279
QSPI_STATUS_Type
Definition: qspi.h:314
QSPI_INSTRFRAME_Type::DDREN
uint32_t DDREN
Definition: qspi.h:392
Qspi::TXDATA
__O QSPI_TXDATA_Type TXDATA
Offset: 0x10 ( /W 32) Transmit Data.
Definition: qspi.h:511
QSPI_CTRLA_Type::reg
uint32_t reg
Definition: qspi.h:52
QSPI_TXDATA_Type::reg
uint32_t reg
Definition: qspi.h:195
QSPI_CTRLA_Type::SWRST
uint32_t SWRST
Definition: qspi.h:46
QSPI_CTRLB_Type
Definition: qspi.h:69
QSPI_SCRAMBCTRL_Type::RANDOMDIS
uint32_t RANDOMDIS
Definition: qspi.h:470
Qspi::BAUD
__IO QSPI_BAUD_Type BAUD
Offset: 0x08 (R/W 32) Baud Rate.
Definition: qspi.h:509
QSPI_BAUD_Type
Definition: qspi.h:141
QSPI_INTFLAG_Type::DRE
__I uint32_t DRE
Definition: qspi.h:282
QSPI_TXDATA_Type
Definition: qspi.h:190
QSPI_STATUS_Type::ENABLE
uint32_t ENABLE
Definition: qspi.h:317
QSPI_CTRLB_Type::LOOPEN
uint32_t LOOPEN
Definition: qspi.h:72
QSPI_CTRLA_Type::ENABLE
uint32_t ENABLE
Definition: qspi.h:47
QSPI_CTRLB_Type::reg
uint32_t reg
Definition: qspi.h:82
Qspi::INSTRCTRL
__IO QSPI_INSTRCTRL_Type INSTRCTRL
Offset: 0x34 (R/W 32) Instruction Code.
Definition: qspi.h:518
QSPI_CTRLA_Type::LASTXFER
uint32_t LASTXFER
Definition: qspi.h:49
QSPI_INSTRFRAME_Type::CRMODE
uint32_t CRMODE
Definition: qspi.h:391
QSPI_BAUD_Type::reg
uint32_t reg
Definition: qspi.h:150
QSPI_INTENSET_Type::reg
uint32_t reg
Definition: qspi.h:256
Qspi::CTRLB
__IO QSPI_CTRLB_Type CTRLB
Offset: 0x04 (R/W 32) Control B.
Definition: qspi.h:508
QSPI_SCRAMBKEY_Type::reg
uint32_t reg
Definition: qspi.h:492
QSPI_INSTRADDR_Type::reg
uint32_t reg
Definition: qspi.h:341
QSPI_INTENSET_Type::RXC
uint32_t RXC
Definition: qspi.h:246
QSPI_CTRLB_Type::SMEMREG
uint32_t SMEMREG
Definition: qspi.h:74
QSPI_INSTRCTRL_Type
Definition: qspi.h:355
Qspi::SCRAMBKEY
__O QSPI_SCRAMBKEY_Type SCRAMBKEY
Offset: 0x44 ( /W 32) Scrambling Key.
Definition: qspi.h:522
QSPI_INSTRFRAME_Type::DUMMYLEN
uint32_t DUMMYLEN
Definition: qspi.h:393
QSPI_BAUD_Type::CPOL
uint32_t CPOL
Definition: qspi.h:143
QSPI_BAUD_Type::DLYBS
uint32_t DLYBS
Definition: qspi.h:147
Qspi::SCRAMBCTRL
__IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL
Offset: 0x40 (R/W 32) Scrambling Mode.
Definition: qspi.h:521
QSPI_INSTRCTRL_Type::reg
uint32_t reg
Definition: qspi.h:362
Qspi::STATUS
__I QSPI_STATUS_Type STATUS
Offset: 0x20 (R/ 32) Status Register.
Definition: qspi.h:515
QSPI_INTENCLR_Type::DRE
uint32_t DRE
Definition: qspi.h:212
QSPI_INTENCLR_Type::CSRISE
uint32_t CSRISE
Definition: qspi.h:216
QSPI_INTFLAG_Type::RXC
__I uint32_t RXC
Definition: qspi.h:281
QSPI_SCRAMBCTRL_Type::ENABLE
uint32_t ENABLE
Definition: qspi.h:469
Qspi
QSPI APB hardware registers.
Definition: qspi.h:506
QSPI_SCRAMBCTRL_Type
Definition: qspi.h:467
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
QSPI_INSTRCTRL_Type::OPTCODE
uint32_t OPTCODE
Definition: qspi.h:359
QSPI_BAUD_Type::CPHA
uint32_t CPHA
Definition: qspi.h:144
QSPI_TXDATA_Type::DATA
uint32_t DATA
Definition: qspi.h:192
QSPI_INSTRFRAME_Type::DATAEN
uint32_t DATAEN
Definition: qspi.h:386
QSPI_SCRAMBCTRL_Type::reg
uint32_t reg
Definition: qspi.h:473
Qspi::INTFLAG
__IO QSPI_INTFLAG_Type INTFLAG
Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear.
Definition: qspi.h:514
QSPI_INTFLAG_Type::reg
uint32_t reg
Definition: qspi.h:291
QSPI_SCRAMBKEY_Type::KEY
uint32_t KEY
Definition: qspi.h:490
QSPI_INTFLAG_Type::uint32_t
__I uint32_t
Definition: qspi.h:285
QSPI_INTENSET_Type::INSTREND
uint32_t INSTREND
Definition: qspi.h:253
QSPI_INSTRCTRL_Type::INSTR
uint32_t INSTR
Definition: qspi.h:357