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30 #ifndef _SAME54_RAMECC_COMPONENT_
31 #define _SAME54_RAMECC_COMPONENT_
40 #define REV_RAMECC 0x100
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
54 #define RAMECC_INTENCLR_OFFSET 0x0
55 #define RAMECC_INTENCLR_RESETVALUE _U_(0x00)
57 #define RAMECC_INTENCLR_SINGLEE_Pos 0
58 #define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
59 #define RAMECC_INTENCLR_DUALE_Pos 1
60 #define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
61 #define RAMECC_INTENCLR_MASK _U_(0x03)
64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
75 #define RAMECC_INTENSET_OFFSET 0x1
76 #define RAMECC_INTENSET_RESETVALUE _U_(0x00)
78 #define RAMECC_INTENSET_SINGLEE_Pos 0
79 #define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
80 #define RAMECC_INTENSET_DUALE_Pos 1
81 #define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
82 #define RAMECC_INTENSET_MASK _U_(0x03)
85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
96 #define RAMECC_INTFLAG_OFFSET 0x2
97 #define RAMECC_INTFLAG_RESETVALUE _U_(0x00)
99 #define RAMECC_INTFLAG_SINGLEE_Pos 0
100 #define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
101 #define RAMECC_INTFLAG_DUALE_Pos 1
102 #define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
103 #define RAMECC_INTFLAG_MASK _U_(0x03)
106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
116 #define RAMECC_STATUS_OFFSET 0x3
117 #define RAMECC_STATUS_RESETVALUE _U_(0x00)
119 #define RAMECC_STATUS_ECCDIS_Pos 0
120 #define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
121 #define RAMECC_STATUS_MASK _U_(0x01)
124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
134 #define RAMECC_ERRADDR_OFFSET 0x4
135 #define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000)
137 #define RAMECC_ERRADDR_ERRADDR_Pos 0
138 #define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
139 #define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
140 #define RAMECC_ERRADDR_MASK _U_(0x0001FFFF)
143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
154 #define RAMECC_DBGCTRL_OFFSET 0xF
155 #define RAMECC_DBGCTRL_RESETVALUE _U_(0x00)
157 #define RAMECC_DBGCTRL_ECCDIS_Pos 0
158 #define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
159 #define RAMECC_DBGCTRL_ECCELOG_Pos 1
160 #define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
161 #define RAMECC_DBGCTRL_MASK _U_(0x03)
164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__I RAMECC_STATUS_Type STATUS
Offset: 0x3 (R/ 8) Status.
RAMECC hardware registers.
__I RAMECC_ERRADDR_Type ERRADDR
Offset: 0x4 (R/ 32) Error Address.
__IO RAMECC_DBGCTRL_Type DBGCTRL
Offset: 0xF (R/W 8) Debug Control.
__IO RAMECC_INTENSET_Type INTENSET
Offset: 0x1 (R/W 8) Interrupt Enable Set.
__IO RAMECC_INTENCLR_Type INTENCLR
Offset: 0x0 (R/W 8) Interrupt Enable Clear.
volatile const uint8_t RoReg8
__IO RAMECC_INTFLAG_Type INTFLAG
Offset: 0x2 (R/W 8) Interrupt Flag.