Go to the documentation of this file.
30 #ifndef _SAME54_USB_COMPONENT_
31 #define _SAME54_USB_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
56 #define USB_CTRLA_OFFSET 0x000
57 #define USB_CTRLA_RESETVALUE _U_(0x00)
59 #define USB_CTRLA_SWRST_Pos 0
60 #define USB_CTRLA_SWRST (_U_(0x1) << USB_CTRLA_SWRST_Pos)
61 #define USB_CTRLA_ENABLE_Pos 1
62 #define USB_CTRLA_ENABLE (_U_(0x1) << USB_CTRLA_ENABLE_Pos)
63 #define USB_CTRLA_RUNSTDBY_Pos 2
64 #define USB_CTRLA_RUNSTDBY (_U_(0x1) << USB_CTRLA_RUNSTDBY_Pos)
65 #define USB_CTRLA_MODE_Pos 7
66 #define USB_CTRLA_MODE (_U_(0x1) << USB_CTRLA_MODE_Pos)
67 #define USB_CTRLA_MODE_DEVICE_Val _U_(0x0)
68 #define USB_CTRLA_MODE_HOST_Val _U_(0x1)
69 #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos)
70 #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos)
71 #define USB_CTRLA_MASK _U_(0x87)
74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
85 #define USB_SYNCBUSY_OFFSET 0x002
86 #define USB_SYNCBUSY_RESETVALUE _U_(0x00)
88 #define USB_SYNCBUSY_SWRST_Pos 0
89 #define USB_SYNCBUSY_SWRST (_U_(0x1) << USB_SYNCBUSY_SWRST_Pos)
90 #define USB_SYNCBUSY_ENABLE_Pos 1
91 #define USB_SYNCBUSY_ENABLE (_U_(0x1) << USB_SYNCBUSY_ENABLE_Pos)
92 #define USB_SYNCBUSY_MASK _U_(0x03)
95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
106 #define USB_QOSCTRL_OFFSET 0x003
107 #define USB_QOSCTRL_RESETVALUE _U_(0x0F)
109 #define USB_QOSCTRL_CQOS_Pos 0
110 #define USB_QOSCTRL_CQOS_Msk (_U_(0x3) << USB_QOSCTRL_CQOS_Pos)
111 #define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
112 #define USB_QOSCTRL_DQOS_Pos 2
113 #define USB_QOSCTRL_DQOS_Msk (_U_(0x3) << USB_QOSCTRL_DQOS_Pos)
114 #define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
115 #define USB_QOSCTRL_MASK _U_(0x0F)
118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
137 #define USB_DEVICE_CTRLB_OFFSET 0x008
138 #define USB_DEVICE_CTRLB_RESETVALUE _U_(0x0001)
140 #define USB_DEVICE_CTRLB_DETACH_Pos 0
141 #define USB_DEVICE_CTRLB_DETACH (_U_(0x1) << USB_DEVICE_CTRLB_DETACH_Pos)
142 #define USB_DEVICE_CTRLB_UPRSM_Pos 1
143 #define USB_DEVICE_CTRLB_UPRSM (_U_(0x1) << USB_DEVICE_CTRLB_UPRSM_Pos)
144 #define USB_DEVICE_CTRLB_SPDCONF_Pos 2
145 #define USB_DEVICE_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_DEVICE_CTRLB_SPDCONF_Pos)
146 #define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
147 #define USB_DEVICE_CTRLB_SPDCONF_FS_Val _U_(0x0)
148 #define USB_DEVICE_CTRLB_SPDCONF_LS_Val _U_(0x1)
149 #define USB_DEVICE_CTRLB_SPDCONF_HS_Val _U_(0x2)
150 #define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val _U_(0x3)
151 #define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
152 #define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
153 #define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
154 #define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos)
155 #define USB_DEVICE_CTRLB_NREPLY_Pos 4
156 #define USB_DEVICE_CTRLB_NREPLY (_U_(0x1) << USB_DEVICE_CTRLB_NREPLY_Pos)
157 #define USB_DEVICE_CTRLB_TSTJ_Pos 5
158 #define USB_DEVICE_CTRLB_TSTJ (_U_(0x1) << USB_DEVICE_CTRLB_TSTJ_Pos)
159 #define USB_DEVICE_CTRLB_TSTK_Pos 6
160 #define USB_DEVICE_CTRLB_TSTK (_U_(0x1) << USB_DEVICE_CTRLB_TSTK_Pos)
161 #define USB_DEVICE_CTRLB_TSTPCKT_Pos 7
162 #define USB_DEVICE_CTRLB_TSTPCKT (_U_(0x1) << USB_DEVICE_CTRLB_TSTPCKT_Pos)
163 #define USB_DEVICE_CTRLB_OPMODE2_Pos 8
164 #define USB_DEVICE_CTRLB_OPMODE2 (_U_(0x1) << USB_DEVICE_CTRLB_OPMODE2_Pos)
165 #define USB_DEVICE_CTRLB_GNAK_Pos 9
166 #define USB_DEVICE_CTRLB_GNAK (_U_(0x1) << USB_DEVICE_CTRLB_GNAK_Pos)
167 #define USB_DEVICE_CTRLB_LPMHDSK_Pos 10
168 #define USB_DEVICE_CTRLB_LPMHDSK_Msk (_U_(0x3) << USB_DEVICE_CTRLB_LPMHDSK_Pos)
169 #define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
170 #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val _U_(0x0)
171 #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val _U_(0x1)
172 #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val _U_(0x2)
173 #define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val _U_(0x3)
174 #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
175 #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
176 #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
177 #define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos)
178 #define USB_DEVICE_CTRLB_MASK _U_(0x0FFF)
181 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
201 #define USB_HOST_CTRLB_OFFSET 0x008
202 #define USB_HOST_CTRLB_RESETVALUE _U_(0x0000)
204 #define USB_HOST_CTRLB_RESUME_Pos 1
205 #define USB_HOST_CTRLB_RESUME (_U_(0x1) << USB_HOST_CTRLB_RESUME_Pos)
206 #define USB_HOST_CTRLB_SPDCONF_Pos 2
207 #define USB_HOST_CTRLB_SPDCONF_Msk (_U_(0x3) << USB_HOST_CTRLB_SPDCONF_Pos)
208 #define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
209 #define USB_HOST_CTRLB_SPDCONF_NORMAL_Val _U_(0x0)
210 #define USB_HOST_CTRLB_SPDCONF_FS_Val _U_(0x3)
211 #define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
212 #define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos)
213 #define USB_HOST_CTRLB_AUTORESUME_Pos 4
214 #define USB_HOST_CTRLB_AUTORESUME (_U_(0x1) << USB_HOST_CTRLB_AUTORESUME_Pos)
215 #define USB_HOST_CTRLB_TSTJ_Pos 5
216 #define USB_HOST_CTRLB_TSTJ (_U_(0x1) << USB_HOST_CTRLB_TSTJ_Pos)
217 #define USB_HOST_CTRLB_TSTK_Pos 6
218 #define USB_HOST_CTRLB_TSTK (_U_(0x1) << USB_HOST_CTRLB_TSTK_Pos)
219 #define USB_HOST_CTRLB_SOFE_Pos 8
220 #define USB_HOST_CTRLB_SOFE (_U_(0x1) << USB_HOST_CTRLB_SOFE_Pos)
221 #define USB_HOST_CTRLB_BUSRESET_Pos 9
222 #define USB_HOST_CTRLB_BUSRESET (_U_(0x1) << USB_HOST_CTRLB_BUSRESET_Pos)
223 #define USB_HOST_CTRLB_VBUSOK_Pos 10
224 #define USB_HOST_CTRLB_VBUSOK (_U_(0x1) << USB_HOST_CTRLB_VBUSOK_Pos)
225 #define USB_HOST_CTRLB_L1RESUME_Pos 11
226 #define USB_HOST_CTRLB_L1RESUME (_U_(0x1) << USB_HOST_CTRLB_L1RESUME_Pos)
227 #define USB_HOST_CTRLB_MASK _U_(0x0F7E)
230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
240 #define USB_DEVICE_DADD_OFFSET 0x00A
241 #define USB_DEVICE_DADD_RESETVALUE _U_(0x00)
243 #define USB_DEVICE_DADD_DADD_Pos 0
244 #define USB_DEVICE_DADD_DADD_Msk (_U_(0x7F) << USB_DEVICE_DADD_DADD_Pos)
245 #define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
246 #define USB_DEVICE_DADD_ADDEN_Pos 7
247 #define USB_DEVICE_DADD_ADDEN (_U_(0x1) << USB_DEVICE_DADD_ADDEN_Pos)
248 #define USB_DEVICE_DADD_MASK _U_(0xFF)
251 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
262 #define USB_HOST_HSOFC_OFFSET 0x00A
263 #define USB_HOST_HSOFC_RESETVALUE _U_(0x00)
265 #define USB_HOST_HSOFC_FLENC_Pos 0
266 #define USB_HOST_HSOFC_FLENC_Msk (_U_(0xF) << USB_HOST_HSOFC_FLENC_Pos)
267 #define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
268 #define USB_HOST_HSOFC_FLENCE_Pos 7
269 #define USB_HOST_HSOFC_FLENCE (_U_(0x1) << USB_HOST_HSOFC_FLENCE_Pos)
270 #define USB_HOST_HSOFC_MASK _U_(0x8F)
273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
285 #define USB_DEVICE_STATUS_OFFSET 0x00C
286 #define USB_DEVICE_STATUS_RESETVALUE _U_(0x40)
288 #define USB_DEVICE_STATUS_SPEED_Pos 2
289 #define USB_DEVICE_STATUS_SPEED_Msk (_U_(0x3) << USB_DEVICE_STATUS_SPEED_Pos)
290 #define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
291 #define USB_DEVICE_STATUS_SPEED_FS_Val _U_(0x0)
292 #define USB_DEVICE_STATUS_SPEED_LS_Val _U_(0x1)
293 #define USB_DEVICE_STATUS_SPEED_HS_Val _U_(0x2)
294 #define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos)
295 #define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
296 #define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos)
297 #define USB_DEVICE_STATUS_LINESTATE_Pos 6
298 #define USB_DEVICE_STATUS_LINESTATE_Msk (_U_(0x3) << USB_DEVICE_STATUS_LINESTATE_Pos)
299 #define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
300 #define USB_DEVICE_STATUS_LINESTATE_0_Val _U_(0x0)
301 #define USB_DEVICE_STATUS_LINESTATE_1_Val _U_(0x1)
302 #define USB_DEVICE_STATUS_LINESTATE_2_Val _U_(0x2)
303 #define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
304 #define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
305 #define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos)
306 #define USB_DEVICE_STATUS_MASK _U_(0xCC)
309 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
321 #define USB_HOST_STATUS_OFFSET 0x00C
322 #define USB_HOST_STATUS_RESETVALUE _U_(0x00)
324 #define USB_HOST_STATUS_SPEED_Pos 2
325 #define USB_HOST_STATUS_SPEED_Msk (_U_(0x3) << USB_HOST_STATUS_SPEED_Pos)
326 #define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
327 #define USB_HOST_STATUS_LINESTATE_Pos 6
328 #define USB_HOST_STATUS_LINESTATE_Msk (_U_(0x3) << USB_HOST_STATUS_LINESTATE_Pos)
329 #define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
330 #define USB_HOST_STATUS_MASK _U_(0xCC)
333 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
343 #define USB_FSMSTATUS_OFFSET 0x00D
344 #define USB_FSMSTATUS_RESETVALUE _U_(0x01)
346 #define USB_FSMSTATUS_FSMSTATE_Pos 0
347 #define USB_FSMSTATUS_FSMSTATE_Msk (_U_(0x7F) << USB_FSMSTATUS_FSMSTATE_Pos)
348 #define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
349 #define USB_FSMSTATUS_FSMSTATE_OFF_Val _U_(0x1)
350 #define USB_FSMSTATUS_FSMSTATE_ON_Val _U_(0x2)
351 #define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val _U_(0x4)
352 #define USB_FSMSTATUS_FSMSTATE_SLEEP_Val _U_(0x8)
353 #define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val _U_(0x10)
354 #define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val _U_(0x20)
355 #define USB_FSMSTATUS_FSMSTATE_RESET_Val _U_(0x40)
356 #define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos)
357 #define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos)
358 #define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos)
359 #define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos)
360 #define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
361 #define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
362 #define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
363 #define USB_FSMSTATUS_MASK _U_(0x7F)
366 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
378 #define USB_DEVICE_FNUM_OFFSET 0x010
379 #define USB_DEVICE_FNUM_RESETVALUE _U_(0x0000)
381 #define USB_DEVICE_FNUM_MFNUM_Pos 0
382 #define USB_DEVICE_FNUM_MFNUM_Msk (_U_(0x7) << USB_DEVICE_FNUM_MFNUM_Pos)
383 #define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
384 #define USB_DEVICE_FNUM_FNUM_Pos 3
385 #define USB_DEVICE_FNUM_FNUM_Msk (_U_(0x7FF) << USB_DEVICE_FNUM_FNUM_Pos)
386 #define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
387 #define USB_DEVICE_FNUM_FNCERR_Pos 15
388 #define USB_DEVICE_FNUM_FNCERR (_U_(0x1) << USB_DEVICE_FNUM_FNCERR_Pos)
389 #define USB_DEVICE_FNUM_MASK _U_(0xBFFF)
392 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
403 #define USB_HOST_FNUM_OFFSET 0x010
404 #define USB_HOST_FNUM_RESETVALUE _U_(0x0000)
406 #define USB_HOST_FNUM_MFNUM_Pos 0
407 #define USB_HOST_FNUM_MFNUM_Msk (_U_(0x7) << USB_HOST_FNUM_MFNUM_Pos)
408 #define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
409 #define USB_HOST_FNUM_FNUM_Pos 3
410 #define USB_HOST_FNUM_FNUM_Msk (_U_(0x7FF) << USB_HOST_FNUM_FNUM_Pos)
411 #define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
412 #define USB_HOST_FNUM_MASK _U_(0x3FFF)
415 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
424 #define USB_HOST_FLENHIGH_OFFSET 0x012
425 #define USB_HOST_FLENHIGH_RESETVALUE _U_(0x00)
427 #define USB_HOST_FLENHIGH_FLENHIGH_Pos 0
428 #define USB_HOST_FLENHIGH_FLENHIGH_Msk (_U_(0xFF) << USB_HOST_FLENHIGH_FLENHIGH_Pos)
429 #define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
430 #define USB_HOST_FLENHIGH_MASK _U_(0xFF)
433 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
452 #define USB_DEVICE_INTENCLR_OFFSET 0x014
453 #define USB_DEVICE_INTENCLR_RESETVALUE _U_(0x0000)
455 #define USB_DEVICE_INTENCLR_SUSPEND_Pos 0
456 #define USB_DEVICE_INTENCLR_SUSPEND (_U_(0x1) << USB_DEVICE_INTENCLR_SUSPEND_Pos)
457 #define USB_DEVICE_INTENCLR_MSOF_Pos 1
458 #define USB_DEVICE_INTENCLR_MSOF (_U_(0x1) << USB_DEVICE_INTENCLR_MSOF_Pos)
459 #define USB_DEVICE_INTENCLR_SOF_Pos 2
460 #define USB_DEVICE_INTENCLR_SOF (_U_(0x1) << USB_DEVICE_INTENCLR_SOF_Pos)
461 #define USB_DEVICE_INTENCLR_EORST_Pos 3
462 #define USB_DEVICE_INTENCLR_EORST (_U_(0x1) << USB_DEVICE_INTENCLR_EORST_Pos)
463 #define USB_DEVICE_INTENCLR_WAKEUP_Pos 4
464 #define USB_DEVICE_INTENCLR_WAKEUP (_U_(0x1) << USB_DEVICE_INTENCLR_WAKEUP_Pos)
465 #define USB_DEVICE_INTENCLR_EORSM_Pos 5
466 #define USB_DEVICE_INTENCLR_EORSM (_U_(0x1) << USB_DEVICE_INTENCLR_EORSM_Pos)
467 #define USB_DEVICE_INTENCLR_UPRSM_Pos 6
468 #define USB_DEVICE_INTENCLR_UPRSM (_U_(0x1) << USB_DEVICE_INTENCLR_UPRSM_Pos)
469 #define USB_DEVICE_INTENCLR_RAMACER_Pos 7
470 #define USB_DEVICE_INTENCLR_RAMACER (_U_(0x1) << USB_DEVICE_INTENCLR_RAMACER_Pos)
471 #define USB_DEVICE_INTENCLR_LPMNYET_Pos 8
472 #define USB_DEVICE_INTENCLR_LPMNYET (_U_(0x1) << USB_DEVICE_INTENCLR_LPMNYET_Pos)
473 #define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9
474 #define USB_DEVICE_INTENCLR_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENCLR_LPMSUSP_Pos)
475 #define USB_DEVICE_INTENCLR_MASK _U_(0x03FF)
478 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
496 #define USB_HOST_INTENCLR_OFFSET 0x014
497 #define USB_HOST_INTENCLR_RESETVALUE _U_(0x0000)
499 #define USB_HOST_INTENCLR_HSOF_Pos 2
500 #define USB_HOST_INTENCLR_HSOF (_U_(0x1) << USB_HOST_INTENCLR_HSOF_Pos)
501 #define USB_HOST_INTENCLR_RST_Pos 3
502 #define USB_HOST_INTENCLR_RST (_U_(0x1) << USB_HOST_INTENCLR_RST_Pos)
503 #define USB_HOST_INTENCLR_WAKEUP_Pos 4
504 #define USB_HOST_INTENCLR_WAKEUP (_U_(0x1) << USB_HOST_INTENCLR_WAKEUP_Pos)
505 #define USB_HOST_INTENCLR_DNRSM_Pos 5
506 #define USB_HOST_INTENCLR_DNRSM (_U_(0x1) << USB_HOST_INTENCLR_DNRSM_Pos)
507 #define USB_HOST_INTENCLR_UPRSM_Pos 6
508 #define USB_HOST_INTENCLR_UPRSM (_U_(0x1) << USB_HOST_INTENCLR_UPRSM_Pos)
509 #define USB_HOST_INTENCLR_RAMACER_Pos 7
510 #define USB_HOST_INTENCLR_RAMACER (_U_(0x1) << USB_HOST_INTENCLR_RAMACER_Pos)
511 #define USB_HOST_INTENCLR_DCONN_Pos 8
512 #define USB_HOST_INTENCLR_DCONN (_U_(0x1) << USB_HOST_INTENCLR_DCONN_Pos)
513 #define USB_HOST_INTENCLR_DDISC_Pos 9
514 #define USB_HOST_INTENCLR_DDISC (_U_(0x1) << USB_HOST_INTENCLR_DDISC_Pos)
515 #define USB_HOST_INTENCLR_MASK _U_(0x03FC)
518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
537 #define USB_DEVICE_INTENSET_OFFSET 0x018
538 #define USB_DEVICE_INTENSET_RESETVALUE _U_(0x0000)
540 #define USB_DEVICE_INTENSET_SUSPEND_Pos 0
541 #define USB_DEVICE_INTENSET_SUSPEND (_U_(0x1) << USB_DEVICE_INTENSET_SUSPEND_Pos)
542 #define USB_DEVICE_INTENSET_MSOF_Pos 1
543 #define USB_DEVICE_INTENSET_MSOF (_U_(0x1) << USB_DEVICE_INTENSET_MSOF_Pos)
544 #define USB_DEVICE_INTENSET_SOF_Pos 2
545 #define USB_DEVICE_INTENSET_SOF (_U_(0x1) << USB_DEVICE_INTENSET_SOF_Pos)
546 #define USB_DEVICE_INTENSET_EORST_Pos 3
547 #define USB_DEVICE_INTENSET_EORST (_U_(0x1) << USB_DEVICE_INTENSET_EORST_Pos)
548 #define USB_DEVICE_INTENSET_WAKEUP_Pos 4
549 #define USB_DEVICE_INTENSET_WAKEUP (_U_(0x1) << USB_DEVICE_INTENSET_WAKEUP_Pos)
550 #define USB_DEVICE_INTENSET_EORSM_Pos 5
551 #define USB_DEVICE_INTENSET_EORSM (_U_(0x1) << USB_DEVICE_INTENSET_EORSM_Pos)
552 #define USB_DEVICE_INTENSET_UPRSM_Pos 6
553 #define USB_DEVICE_INTENSET_UPRSM (_U_(0x1) << USB_DEVICE_INTENSET_UPRSM_Pos)
554 #define USB_DEVICE_INTENSET_RAMACER_Pos 7
555 #define USB_DEVICE_INTENSET_RAMACER (_U_(0x1) << USB_DEVICE_INTENSET_RAMACER_Pos)
556 #define USB_DEVICE_INTENSET_LPMNYET_Pos 8
557 #define USB_DEVICE_INTENSET_LPMNYET (_U_(0x1) << USB_DEVICE_INTENSET_LPMNYET_Pos)
558 #define USB_DEVICE_INTENSET_LPMSUSP_Pos 9
559 #define USB_DEVICE_INTENSET_LPMSUSP (_U_(0x1) << USB_DEVICE_INTENSET_LPMSUSP_Pos)
560 #define USB_DEVICE_INTENSET_MASK _U_(0x03FF)
563 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
581 #define USB_HOST_INTENSET_OFFSET 0x018
582 #define USB_HOST_INTENSET_RESETVALUE _U_(0x0000)
584 #define USB_HOST_INTENSET_HSOF_Pos 2
585 #define USB_HOST_INTENSET_HSOF (_U_(0x1) << USB_HOST_INTENSET_HSOF_Pos)
586 #define USB_HOST_INTENSET_RST_Pos 3
587 #define USB_HOST_INTENSET_RST (_U_(0x1) << USB_HOST_INTENSET_RST_Pos)
588 #define USB_HOST_INTENSET_WAKEUP_Pos 4
589 #define USB_HOST_INTENSET_WAKEUP (_U_(0x1) << USB_HOST_INTENSET_WAKEUP_Pos)
590 #define USB_HOST_INTENSET_DNRSM_Pos 5
591 #define USB_HOST_INTENSET_DNRSM (_U_(0x1) << USB_HOST_INTENSET_DNRSM_Pos)
592 #define USB_HOST_INTENSET_UPRSM_Pos 6
593 #define USB_HOST_INTENSET_UPRSM (_U_(0x1) << USB_HOST_INTENSET_UPRSM_Pos)
594 #define USB_HOST_INTENSET_RAMACER_Pos 7
595 #define USB_HOST_INTENSET_RAMACER (_U_(0x1) << USB_HOST_INTENSET_RAMACER_Pos)
596 #define USB_HOST_INTENSET_DCONN_Pos 8
597 #define USB_HOST_INTENSET_DCONN (_U_(0x1) << USB_HOST_INTENSET_DCONN_Pos)
598 #define USB_HOST_INTENSET_DDISC_Pos 9
599 #define USB_HOST_INTENSET_DDISC (_U_(0x1) << USB_HOST_INTENSET_DDISC_Pos)
600 #define USB_HOST_INTENSET_MASK _U_(0x03FC)
603 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
622 #define USB_DEVICE_INTFLAG_OFFSET 0x01C
623 #define USB_DEVICE_INTFLAG_RESETVALUE _U_(0x0000)
625 #define USB_DEVICE_INTFLAG_SUSPEND_Pos 0
626 #define USB_DEVICE_INTFLAG_SUSPEND (_U_(0x1) << USB_DEVICE_INTFLAG_SUSPEND_Pos)
627 #define USB_DEVICE_INTFLAG_MSOF_Pos 1
628 #define USB_DEVICE_INTFLAG_MSOF (_U_(0x1) << USB_DEVICE_INTFLAG_MSOF_Pos)
629 #define USB_DEVICE_INTFLAG_SOF_Pos 2
630 #define USB_DEVICE_INTFLAG_SOF (_U_(0x1) << USB_DEVICE_INTFLAG_SOF_Pos)
631 #define USB_DEVICE_INTFLAG_EORST_Pos 3
632 #define USB_DEVICE_INTFLAG_EORST (_U_(0x1) << USB_DEVICE_INTFLAG_EORST_Pos)
633 #define USB_DEVICE_INTFLAG_WAKEUP_Pos 4
634 #define USB_DEVICE_INTFLAG_WAKEUP (_U_(0x1) << USB_DEVICE_INTFLAG_WAKEUP_Pos)
635 #define USB_DEVICE_INTFLAG_EORSM_Pos 5
636 #define USB_DEVICE_INTFLAG_EORSM (_U_(0x1) << USB_DEVICE_INTFLAG_EORSM_Pos)
637 #define USB_DEVICE_INTFLAG_UPRSM_Pos 6
638 #define USB_DEVICE_INTFLAG_UPRSM (_U_(0x1) << USB_DEVICE_INTFLAG_UPRSM_Pos)
639 #define USB_DEVICE_INTFLAG_RAMACER_Pos 7
640 #define USB_DEVICE_INTFLAG_RAMACER (_U_(0x1) << USB_DEVICE_INTFLAG_RAMACER_Pos)
641 #define USB_DEVICE_INTFLAG_LPMNYET_Pos 8
642 #define USB_DEVICE_INTFLAG_LPMNYET (_U_(0x1) << USB_DEVICE_INTFLAG_LPMNYET_Pos)
643 #define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9
644 #define USB_DEVICE_INTFLAG_LPMSUSP (_U_(0x1) << USB_DEVICE_INTFLAG_LPMSUSP_Pos)
645 #define USB_DEVICE_INTFLAG_MASK _U_(0x03FF)
648 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
666 #define USB_HOST_INTFLAG_OFFSET 0x01C
667 #define USB_HOST_INTFLAG_RESETVALUE _U_(0x0000)
669 #define USB_HOST_INTFLAG_HSOF_Pos 2
670 #define USB_HOST_INTFLAG_HSOF (_U_(0x1) << USB_HOST_INTFLAG_HSOF_Pos)
671 #define USB_HOST_INTFLAG_RST_Pos 3
672 #define USB_HOST_INTFLAG_RST (_U_(0x1) << USB_HOST_INTFLAG_RST_Pos)
673 #define USB_HOST_INTFLAG_WAKEUP_Pos 4
674 #define USB_HOST_INTFLAG_WAKEUP (_U_(0x1) << USB_HOST_INTFLAG_WAKEUP_Pos)
675 #define USB_HOST_INTFLAG_DNRSM_Pos 5
676 #define USB_HOST_INTFLAG_DNRSM (_U_(0x1) << USB_HOST_INTFLAG_DNRSM_Pos)
677 #define USB_HOST_INTFLAG_UPRSM_Pos 6
678 #define USB_HOST_INTFLAG_UPRSM (_U_(0x1) << USB_HOST_INTFLAG_UPRSM_Pos)
679 #define USB_HOST_INTFLAG_RAMACER_Pos 7
680 #define USB_HOST_INTFLAG_RAMACER (_U_(0x1) << USB_HOST_INTFLAG_RAMACER_Pos)
681 #define USB_HOST_INTFLAG_DCONN_Pos 8
682 #define USB_HOST_INTFLAG_DCONN (_U_(0x1) << USB_HOST_INTFLAG_DCONN_Pos)
683 #define USB_HOST_INTFLAG_DDISC_Pos 9
684 #define USB_HOST_INTFLAG_DDISC (_U_(0x1) << USB_HOST_INTFLAG_DDISC_Pos)
685 #define USB_HOST_INTFLAG_MASK _U_(0x03FC)
688 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
709 #define USB_DEVICE_EPINTSMRY_OFFSET 0x020
710 #define USB_DEVICE_EPINTSMRY_RESETVALUE _U_(0x0000)
712 #define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0
713 #define USB_DEVICE_EPINTSMRY_EPINT0 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT0_Pos)
714 #define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1
715 #define USB_DEVICE_EPINTSMRY_EPINT1 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT1_Pos)
716 #define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2
717 #define USB_DEVICE_EPINTSMRY_EPINT2 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT2_Pos)
718 #define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3
719 #define USB_DEVICE_EPINTSMRY_EPINT3 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT3_Pos)
720 #define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4
721 #define USB_DEVICE_EPINTSMRY_EPINT4 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT4_Pos)
722 #define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5
723 #define USB_DEVICE_EPINTSMRY_EPINT5 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT5_Pos)
724 #define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6
725 #define USB_DEVICE_EPINTSMRY_EPINT6 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT6_Pos)
726 #define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7
727 #define USB_DEVICE_EPINTSMRY_EPINT7 (_U_(1) << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
728 #define USB_DEVICE_EPINTSMRY_EPINT_Pos 0
729 #define USB_DEVICE_EPINTSMRY_EPINT_Msk (_U_(0xFF) << USB_DEVICE_EPINTSMRY_EPINT_Pos)
730 #define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
731 #define USB_DEVICE_EPINTSMRY_MASK _U_(0x00FF)
734 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
755 #define USB_HOST_PINTSMRY_OFFSET 0x020
756 #define USB_HOST_PINTSMRY_RESETVALUE _U_(0x0000)
758 #define USB_HOST_PINTSMRY_EPINT0_Pos 0
759 #define USB_HOST_PINTSMRY_EPINT0 (_U_(1) << USB_HOST_PINTSMRY_EPINT0_Pos)
760 #define USB_HOST_PINTSMRY_EPINT1_Pos 1
761 #define USB_HOST_PINTSMRY_EPINT1 (_U_(1) << USB_HOST_PINTSMRY_EPINT1_Pos)
762 #define USB_HOST_PINTSMRY_EPINT2_Pos 2
763 #define USB_HOST_PINTSMRY_EPINT2 (_U_(1) << USB_HOST_PINTSMRY_EPINT2_Pos)
764 #define USB_HOST_PINTSMRY_EPINT3_Pos 3
765 #define USB_HOST_PINTSMRY_EPINT3 (_U_(1) << USB_HOST_PINTSMRY_EPINT3_Pos)
766 #define USB_HOST_PINTSMRY_EPINT4_Pos 4
767 #define USB_HOST_PINTSMRY_EPINT4 (_U_(1) << USB_HOST_PINTSMRY_EPINT4_Pos)
768 #define USB_HOST_PINTSMRY_EPINT5_Pos 5
769 #define USB_HOST_PINTSMRY_EPINT5 (_U_(1) << USB_HOST_PINTSMRY_EPINT5_Pos)
770 #define USB_HOST_PINTSMRY_EPINT6_Pos 6
771 #define USB_HOST_PINTSMRY_EPINT6 (_U_(1) << USB_HOST_PINTSMRY_EPINT6_Pos)
772 #define USB_HOST_PINTSMRY_EPINT7_Pos 7
773 #define USB_HOST_PINTSMRY_EPINT7 (_U_(1) << USB_HOST_PINTSMRY_EPINT7_Pos)
774 #define USB_HOST_PINTSMRY_EPINT_Pos 0
775 #define USB_HOST_PINTSMRY_EPINT_Msk (_U_(0xFF) << USB_HOST_PINTSMRY_EPINT_Pos)
776 #define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
777 #define USB_HOST_PINTSMRY_MASK _U_(0x00FF)
780 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
789 #define USB_DESCADD_OFFSET 0x024
790 #define USB_DESCADD_RESETVALUE _U_(0x00000000)
792 #define USB_DESCADD_DESCADD_Pos 0
793 #define USB_DESCADD_DESCADD_Msk (_U_(0xFFFFFFFF) << USB_DESCADD_DESCADD_Pos)
794 #define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
795 #define USB_DESCADD_MASK _U_(0xFFFFFFFF)
798 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
812 #define USB_PADCAL_OFFSET 0x028
813 #define USB_PADCAL_RESETVALUE _U_(0x0000)
815 #define USB_PADCAL_TRANSP_Pos 0
816 #define USB_PADCAL_TRANSP_Msk (_U_(0x1F) << USB_PADCAL_TRANSP_Pos)
817 #define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
818 #define USB_PADCAL_TRANSN_Pos 6
819 #define USB_PADCAL_TRANSN_Msk (_U_(0x1F) << USB_PADCAL_TRANSN_Pos)
820 #define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
821 #define USB_PADCAL_TRIM_Pos 12
822 #define USB_PADCAL_TRIM_Msk (_U_(0x7) << USB_PADCAL_TRIM_Pos)
823 #define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
824 #define USB_PADCAL_MASK _U_(0x77DF)
827 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
839 #define USB_DEVICE_EPCFG_OFFSET 0x100
840 #define USB_DEVICE_EPCFG_RESETVALUE _U_(0x00)
842 #define USB_DEVICE_EPCFG_EPTYPE0_Pos 0
843 #define USB_DEVICE_EPCFG_EPTYPE0_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE0_Pos)
844 #define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
845 #define USB_DEVICE_EPCFG_EPTYPE1_Pos 4
846 #define USB_DEVICE_EPCFG_EPTYPE1_Msk (_U_(0x7) << USB_DEVICE_EPCFG_EPTYPE1_Pos)
847 #define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
848 #define USB_DEVICE_EPCFG_NYETDIS_Pos 7
849 #define USB_DEVICE_EPCFG_NYETDIS (_U_(0x1) << USB_DEVICE_EPCFG_NYETDIS_Pos)
850 #define USB_DEVICE_EPCFG_MASK _U_(0xF7)
853 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
865 #define USB_HOST_PCFG_OFFSET 0x100
866 #define USB_HOST_PCFG_RESETVALUE _U_(0x00)
868 #define USB_HOST_PCFG_PTOKEN_Pos 0
869 #define USB_HOST_PCFG_PTOKEN_Msk (_U_(0x3) << USB_HOST_PCFG_PTOKEN_Pos)
870 #define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
871 #define USB_HOST_PCFG_BK_Pos 2
872 #define USB_HOST_PCFG_BK (_U_(0x1) << USB_HOST_PCFG_BK_Pos)
873 #define USB_HOST_PCFG_PTYPE_Pos 3
874 #define USB_HOST_PCFG_PTYPE_Msk (_U_(0x7) << USB_HOST_PCFG_PTYPE_Pos)
875 #define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
876 #define USB_HOST_PCFG_MASK _U_(0x3F)
879 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
888 #define USB_HOST_BINTERVAL_OFFSET 0x103
889 #define USB_HOST_BINTERVAL_RESETVALUE _U_(0x00)
891 #define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0
892 #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (_U_(0xFF) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
893 #define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
894 #define USB_HOST_BINTERVAL_MASK _U_(0xFF)
897 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
918 #define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104
919 #define USB_DEVICE_EPSTATUSCLR_RESETVALUE _U_(0x00)
921 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0
922 #define USB_DEVICE_EPSTATUSCLR_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos)
923 #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1
924 #define USB_DEVICE_EPSTATUSCLR_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos)
925 #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2
926 #define USB_DEVICE_EPSTATUSCLR_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_CURBK_Pos)
927 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4
928 #define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos)
929 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5
930 #define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
931 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4
932 #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
933 #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
934 #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6
935 #define USB_DEVICE_EPSTATUSCLR_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
936 #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7
937 #define USB_DEVICE_EPSTATUSCLR_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos)
938 #define USB_DEVICE_EPSTATUSCLR_MASK _U_(0xF7)
941 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
957 #define USB_HOST_PSTATUSCLR_OFFSET 0x104
958 #define USB_HOST_PSTATUSCLR_RESETVALUE _U_(0x00)
960 #define USB_HOST_PSTATUSCLR_DTGL_Pos 0
961 #define USB_HOST_PSTATUSCLR_DTGL (_U_(0x1) << USB_HOST_PSTATUSCLR_DTGL_Pos)
962 #define USB_HOST_PSTATUSCLR_CURBK_Pos 2
963 #define USB_HOST_PSTATUSCLR_CURBK (_U_(0x1) << USB_HOST_PSTATUSCLR_CURBK_Pos)
964 #define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4
965 #define USB_HOST_PSTATUSCLR_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSCLR_PFREEZE_Pos)
966 #define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6
967 #define USB_HOST_PSTATUSCLR_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK0RDY_Pos)
968 #define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7
969 #define USB_HOST_PSTATUSCLR_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSCLR_BK1RDY_Pos)
970 #define USB_HOST_PSTATUSCLR_MASK _U_(0xD5)
973 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
994 #define USB_DEVICE_EPSTATUSSET_OFFSET 0x105
995 #define USB_DEVICE_EPSTATUSSET_RESETVALUE _U_(0x00)
997 #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0
998 #define USB_DEVICE_EPSTATUSSET_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos)
999 #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1
1000 #define USB_DEVICE_EPSTATUSSET_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos)
1001 #define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2
1002 #define USB_DEVICE_EPSTATUSSET_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUSSET_CURBK_Pos)
1003 #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4
1004 #define USB_DEVICE_EPSTATUSSET_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos)
1005 #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5
1006 #define USB_DEVICE_EPSTATUSSET_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
1007 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4
1008 #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
1009 #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
1010 #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6
1011 #define USB_DEVICE_EPSTATUSSET_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
1012 #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7
1013 #define USB_DEVICE_EPSTATUSSET_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos)
1014 #define USB_DEVICE_EPSTATUSSET_MASK _U_(0xF7)
1017 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1033 #define USB_HOST_PSTATUSSET_OFFSET 0x105
1034 #define USB_HOST_PSTATUSSET_RESETVALUE _U_(0x00)
1036 #define USB_HOST_PSTATUSSET_DTGL_Pos 0
1037 #define USB_HOST_PSTATUSSET_DTGL (_U_(0x1) << USB_HOST_PSTATUSSET_DTGL_Pos)
1038 #define USB_HOST_PSTATUSSET_CURBK_Pos 2
1039 #define USB_HOST_PSTATUSSET_CURBK (_U_(0x1) << USB_HOST_PSTATUSSET_CURBK_Pos)
1040 #define USB_HOST_PSTATUSSET_PFREEZE_Pos 4
1041 #define USB_HOST_PSTATUSSET_PFREEZE (_U_(0x1) << USB_HOST_PSTATUSSET_PFREEZE_Pos)
1042 #define USB_HOST_PSTATUSSET_BK0RDY_Pos 6
1043 #define USB_HOST_PSTATUSSET_BK0RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK0RDY_Pos)
1044 #define USB_HOST_PSTATUSSET_BK1RDY_Pos 7
1045 #define USB_HOST_PSTATUSSET_BK1RDY (_U_(0x1) << USB_HOST_PSTATUSSET_BK1RDY_Pos)
1046 #define USB_HOST_PSTATUSSET_MASK _U_(0xD5)
1049 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1070 #define USB_DEVICE_EPSTATUS_OFFSET 0x106
1071 #define USB_DEVICE_EPSTATUS_RESETVALUE _U_(0x00)
1073 #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0
1074 #define USB_DEVICE_EPSTATUS_DTGLOUT (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLOUT_Pos)
1075 #define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1
1076 #define USB_DEVICE_EPSTATUS_DTGLIN (_U_(0x1) << USB_DEVICE_EPSTATUS_DTGLIN_Pos)
1077 #define USB_DEVICE_EPSTATUS_CURBK_Pos 2
1078 #define USB_DEVICE_EPSTATUS_CURBK (_U_(0x1) << USB_DEVICE_EPSTATUS_CURBK_Pos)
1079 #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4
1080 #define USB_DEVICE_EPSTATUS_STALLRQ0 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ0_Pos)
1081 #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5
1082 #define USB_DEVICE_EPSTATUS_STALLRQ1 (_U_(1) << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
1083 #define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4
1084 #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (_U_(0x3) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
1085 #define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
1086 #define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6
1087 #define USB_DEVICE_EPSTATUS_BK0RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
1088 #define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7
1089 #define USB_DEVICE_EPSTATUS_BK1RDY (_U_(0x1) << USB_DEVICE_EPSTATUS_BK1RDY_Pos)
1090 #define USB_DEVICE_EPSTATUS_MASK _U_(0xF7)
1093 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1109 #define USB_HOST_PSTATUS_OFFSET 0x106
1110 #define USB_HOST_PSTATUS_RESETVALUE _U_(0x00)
1112 #define USB_HOST_PSTATUS_DTGL_Pos 0
1113 #define USB_HOST_PSTATUS_DTGL (_U_(0x1) << USB_HOST_PSTATUS_DTGL_Pos)
1114 #define USB_HOST_PSTATUS_CURBK_Pos 2
1115 #define USB_HOST_PSTATUS_CURBK (_U_(0x1) << USB_HOST_PSTATUS_CURBK_Pos)
1116 #define USB_HOST_PSTATUS_PFREEZE_Pos 4
1117 #define USB_HOST_PSTATUS_PFREEZE (_U_(0x1) << USB_HOST_PSTATUS_PFREEZE_Pos)
1118 #define USB_HOST_PSTATUS_BK0RDY_Pos 6
1119 #define USB_HOST_PSTATUS_BK0RDY (_U_(0x1) << USB_HOST_PSTATUS_BK0RDY_Pos)
1120 #define USB_HOST_PSTATUS_BK1RDY_Pos 7
1121 #define USB_HOST_PSTATUS_BK1RDY (_U_(0x1) << USB_HOST_PSTATUS_BK1RDY_Pos)
1122 #define USB_HOST_PSTATUS_MASK _U_(0xD5)
1125 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1148 #define USB_DEVICE_EPINTFLAG_OFFSET 0x107
1149 #define USB_DEVICE_EPINTFLAG_RESETVALUE _U_(0x00)
1151 #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0
1152 #define USB_DEVICE_EPINTFLAG_TRCPT0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT0_Pos)
1153 #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1
1154 #define USB_DEVICE_EPINTFLAG_TRCPT1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
1155 #define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0
1156 #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
1157 #define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
1158 #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2
1159 #define USB_DEVICE_EPINTFLAG_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
1160 #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3
1161 #define USB_DEVICE_EPINTFLAG_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
1162 #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2
1163 #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
1164 #define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
1165 #define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4
1166 #define USB_DEVICE_EPINTFLAG_RXSTP (_U_(0x1) << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
1167 #define USB_DEVICE_EPINTFLAG_STALL0_Pos 5
1168 #define USB_DEVICE_EPINTFLAG_STALL0 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL0_Pos)
1169 #define USB_DEVICE_EPINTFLAG_STALL1_Pos 6
1170 #define USB_DEVICE_EPINTFLAG_STALL1 (_U_(1) << USB_DEVICE_EPINTFLAG_STALL1_Pos)
1171 #define USB_DEVICE_EPINTFLAG_STALL_Pos 5
1172 #define USB_DEVICE_EPINTFLAG_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTFLAG_STALL_Pos)
1173 #define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
1174 #define USB_DEVICE_EPINTFLAG_MASK _U_(0x7F)
1177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1196 #define USB_HOST_PINTFLAG_OFFSET 0x107
1197 #define USB_HOST_PINTFLAG_RESETVALUE _U_(0x00)
1199 #define USB_HOST_PINTFLAG_TRCPT0_Pos 0
1200 #define USB_HOST_PINTFLAG_TRCPT0 (_U_(1) << USB_HOST_PINTFLAG_TRCPT0_Pos)
1201 #define USB_HOST_PINTFLAG_TRCPT1_Pos 1
1202 #define USB_HOST_PINTFLAG_TRCPT1 (_U_(1) << USB_HOST_PINTFLAG_TRCPT1_Pos)
1203 #define USB_HOST_PINTFLAG_TRCPT_Pos 0
1204 #define USB_HOST_PINTFLAG_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTFLAG_TRCPT_Pos)
1205 #define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
1206 #define USB_HOST_PINTFLAG_TRFAIL_Pos 2
1207 #define USB_HOST_PINTFLAG_TRFAIL (_U_(0x1) << USB_HOST_PINTFLAG_TRFAIL_Pos)
1208 #define USB_HOST_PINTFLAG_PERR_Pos 3
1209 #define USB_HOST_PINTFLAG_PERR (_U_(0x1) << USB_HOST_PINTFLAG_PERR_Pos)
1210 #define USB_HOST_PINTFLAG_TXSTP_Pos 4
1211 #define USB_HOST_PINTFLAG_TXSTP (_U_(0x1) << USB_HOST_PINTFLAG_TXSTP_Pos)
1212 #define USB_HOST_PINTFLAG_STALL_Pos 5
1213 #define USB_HOST_PINTFLAG_STALL (_U_(0x1) << USB_HOST_PINTFLAG_STALL_Pos)
1214 #define USB_HOST_PINTFLAG_MASK _U_(0x3F)
1217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1240 #define USB_DEVICE_EPINTENCLR_OFFSET 0x108
1241 #define USB_DEVICE_EPINTENCLR_RESETVALUE _U_(0x00)
1243 #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0
1244 #define USB_DEVICE_EPINTENCLR_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT0_Pos)
1245 #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1
1246 #define USB_DEVICE_EPINTENCLR_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
1247 #define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0
1248 #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
1249 #define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
1250 #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2
1251 #define USB_DEVICE_EPINTENCLR_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
1252 #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3
1253 #define USB_DEVICE_EPINTENCLR_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
1254 #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2
1255 #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
1256 #define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
1257 #define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4
1258 #define USB_DEVICE_EPINTENCLR_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
1259 #define USB_DEVICE_EPINTENCLR_STALL0_Pos 5
1260 #define USB_DEVICE_EPINTENCLR_STALL0 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL0_Pos)
1261 #define USB_DEVICE_EPINTENCLR_STALL1_Pos 6
1262 #define USB_DEVICE_EPINTENCLR_STALL1 (_U_(1) << USB_DEVICE_EPINTENCLR_STALL1_Pos)
1263 #define USB_DEVICE_EPINTENCLR_STALL_Pos 5
1264 #define USB_DEVICE_EPINTENCLR_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENCLR_STALL_Pos)
1265 #define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
1266 #define USB_DEVICE_EPINTENCLR_MASK _U_(0x7F)
1269 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1288 #define USB_HOST_PINTENCLR_OFFSET 0x108
1289 #define USB_HOST_PINTENCLR_RESETVALUE _U_(0x00)
1291 #define USB_HOST_PINTENCLR_TRCPT0_Pos 0
1292 #define USB_HOST_PINTENCLR_TRCPT0 (_U_(1) << USB_HOST_PINTENCLR_TRCPT0_Pos)
1293 #define USB_HOST_PINTENCLR_TRCPT1_Pos 1
1294 #define USB_HOST_PINTENCLR_TRCPT1 (_U_(1) << USB_HOST_PINTENCLR_TRCPT1_Pos)
1295 #define USB_HOST_PINTENCLR_TRCPT_Pos 0
1296 #define USB_HOST_PINTENCLR_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENCLR_TRCPT_Pos)
1297 #define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
1298 #define USB_HOST_PINTENCLR_TRFAIL_Pos 2
1299 #define USB_HOST_PINTENCLR_TRFAIL (_U_(0x1) << USB_HOST_PINTENCLR_TRFAIL_Pos)
1300 #define USB_HOST_PINTENCLR_PERR_Pos 3
1301 #define USB_HOST_PINTENCLR_PERR (_U_(0x1) << USB_HOST_PINTENCLR_PERR_Pos)
1302 #define USB_HOST_PINTENCLR_TXSTP_Pos 4
1303 #define USB_HOST_PINTENCLR_TXSTP (_U_(0x1) << USB_HOST_PINTENCLR_TXSTP_Pos)
1304 #define USB_HOST_PINTENCLR_STALL_Pos 5
1305 #define USB_HOST_PINTENCLR_STALL (_U_(0x1) << USB_HOST_PINTENCLR_STALL_Pos)
1306 #define USB_HOST_PINTENCLR_MASK _U_(0x3F)
1309 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1332 #define USB_DEVICE_EPINTENSET_OFFSET 0x109
1333 #define USB_DEVICE_EPINTENSET_RESETVALUE _U_(0x00)
1335 #define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0
1336 #define USB_DEVICE_EPINTENSET_TRCPT0 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT0_Pos)
1337 #define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1
1338 #define USB_DEVICE_EPINTENSET_TRCPT1 (_U_(1) << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
1339 #define USB_DEVICE_EPINTENSET_TRCPT_Pos 0
1340 #define USB_DEVICE_EPINTENSET_TRCPT_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRCPT_Pos)
1341 #define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
1342 #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2
1343 #define USB_DEVICE_EPINTENSET_TRFAIL0 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
1344 #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3
1345 #define USB_DEVICE_EPINTENSET_TRFAIL1 (_U_(1) << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
1346 #define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2
1347 #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
1348 #define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
1349 #define USB_DEVICE_EPINTENSET_RXSTP_Pos 4
1350 #define USB_DEVICE_EPINTENSET_RXSTP (_U_(0x1) << USB_DEVICE_EPINTENSET_RXSTP_Pos)
1351 #define USB_DEVICE_EPINTENSET_STALL0_Pos 5
1352 #define USB_DEVICE_EPINTENSET_STALL0 (_U_(1) << USB_DEVICE_EPINTENSET_STALL0_Pos)
1353 #define USB_DEVICE_EPINTENSET_STALL1_Pos 6
1354 #define USB_DEVICE_EPINTENSET_STALL1 (_U_(1) << USB_DEVICE_EPINTENSET_STALL1_Pos)
1355 #define USB_DEVICE_EPINTENSET_STALL_Pos 5
1356 #define USB_DEVICE_EPINTENSET_STALL_Msk (_U_(0x3) << USB_DEVICE_EPINTENSET_STALL_Pos)
1357 #define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
1358 #define USB_DEVICE_EPINTENSET_MASK _U_(0x7F)
1361 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1380 #define USB_HOST_PINTENSET_OFFSET 0x109
1381 #define USB_HOST_PINTENSET_RESETVALUE _U_(0x00)
1383 #define USB_HOST_PINTENSET_TRCPT0_Pos 0
1384 #define USB_HOST_PINTENSET_TRCPT0 (_U_(1) << USB_HOST_PINTENSET_TRCPT0_Pos)
1385 #define USB_HOST_PINTENSET_TRCPT1_Pos 1
1386 #define USB_HOST_PINTENSET_TRCPT1 (_U_(1) << USB_HOST_PINTENSET_TRCPT1_Pos)
1387 #define USB_HOST_PINTENSET_TRCPT_Pos 0
1388 #define USB_HOST_PINTENSET_TRCPT_Msk (_U_(0x3) << USB_HOST_PINTENSET_TRCPT_Pos)
1389 #define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
1390 #define USB_HOST_PINTENSET_TRFAIL_Pos 2
1391 #define USB_HOST_PINTENSET_TRFAIL (_U_(0x1) << USB_HOST_PINTENSET_TRFAIL_Pos)
1392 #define USB_HOST_PINTENSET_PERR_Pos 3
1393 #define USB_HOST_PINTENSET_PERR (_U_(0x1) << USB_HOST_PINTENSET_PERR_Pos)
1394 #define USB_HOST_PINTENSET_TXSTP_Pos 4
1395 #define USB_HOST_PINTENSET_TXSTP (_U_(0x1) << USB_HOST_PINTENSET_TXSTP_Pos)
1396 #define USB_HOST_PINTENSET_STALL_Pos 5
1397 #define USB_HOST_PINTENSET_STALL (_U_(0x1) << USB_HOST_PINTENSET_STALL_Pos)
1398 #define USB_HOST_PINTENSET_MASK _U_(0x3F)
1401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1410 #define USB_DEVICE_ADDR_OFFSET 0x000
1412 #define USB_DEVICE_ADDR_ADDR_Pos 0
1413 #define USB_DEVICE_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_DEVICE_ADDR_ADDR_Pos)
1414 #define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
1415 #define USB_DEVICE_ADDR_MASK _U_(0xFFFFFFFF)
1418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1427 #define USB_HOST_ADDR_OFFSET 0x000
1429 #define USB_HOST_ADDR_ADDR_Pos 0
1430 #define USB_HOST_ADDR_ADDR_Msk (_U_(0xFFFFFFFF) << USB_HOST_ADDR_ADDR_Pos)
1431 #define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
1432 #define USB_HOST_ADDR_MASK _U_(0xFFFFFFFF)
1435 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1447 #define USB_DEVICE_PCKSIZE_OFFSET 0x004
1449 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0
1450 #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
1451 #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
1452 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14
1453 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
1454 #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
1455 #define USB_DEVICE_PCKSIZE_SIZE_Pos 28
1456 #define USB_DEVICE_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_DEVICE_PCKSIZE_SIZE_Pos)
1457 #define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
1458 #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31
1459 #define USB_DEVICE_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
1460 #define USB_DEVICE_PCKSIZE_MASK _U_(0xFFFFFFFF)
1463 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1475 #define USB_HOST_PCKSIZE_OFFSET 0x004
1477 #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0
1478 #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
1479 #define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
1480 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14
1481 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (_U_(0x3FFF) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
1482 #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
1483 #define USB_HOST_PCKSIZE_SIZE_Pos 28
1484 #define USB_HOST_PCKSIZE_SIZE_Msk (_U_(0x7) << USB_HOST_PCKSIZE_SIZE_Pos)
1485 #define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
1486 #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31
1487 #define USB_HOST_PCKSIZE_AUTO_ZLP (_U_(0x1) << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
1488 #define USB_HOST_PCKSIZE_MASK _U_(0xFFFFFFFF)
1491 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1502 #define USB_DEVICE_EXTREG_OFFSET 0x008
1504 #define USB_DEVICE_EXTREG_SUBPID_Pos 0
1505 #define USB_DEVICE_EXTREG_SUBPID_Msk (_U_(0xF) << USB_DEVICE_EXTREG_SUBPID_Pos)
1506 #define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
1507 #define USB_DEVICE_EXTREG_VARIABLE_Pos 4
1508 #define USB_DEVICE_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_DEVICE_EXTREG_VARIABLE_Pos)
1509 #define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
1510 #define USB_DEVICE_EXTREG_MASK _U_(0x7FFF)
1513 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1524 #define USB_HOST_EXTREG_OFFSET 0x008
1526 #define USB_HOST_EXTREG_SUBPID_Pos 0
1527 #define USB_HOST_EXTREG_SUBPID_Msk (_U_(0xF) << USB_HOST_EXTREG_SUBPID_Pos)
1528 #define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
1529 #define USB_HOST_EXTREG_VARIABLE_Pos 4
1530 #define USB_HOST_EXTREG_VARIABLE_Msk (_U_(0x7FF) << USB_HOST_EXTREG_VARIABLE_Pos)
1531 #define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
1532 #define USB_HOST_EXTREG_MASK _U_(0x7FFF)
1535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1546 #define USB_DEVICE_STATUS_BK_OFFSET 0x00A
1548 #define USB_DEVICE_STATUS_BK_CRCERR_Pos 0
1549 #define USB_DEVICE_STATUS_BK_CRCERR (_U_(0x1) << USB_DEVICE_STATUS_BK_CRCERR_Pos)
1550 #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1
1551 #define USB_DEVICE_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos)
1552 #define USB_DEVICE_STATUS_BK_MASK _U_(0x03)
1555 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1566 #define USB_HOST_STATUS_BK_OFFSET 0x00A
1568 #define USB_HOST_STATUS_BK_CRCERR_Pos 0
1569 #define USB_HOST_STATUS_BK_CRCERR (_U_(0x1) << USB_HOST_STATUS_BK_CRCERR_Pos)
1570 #define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1
1571 #define USB_HOST_STATUS_BK_ERRORFLOW (_U_(0x1) << USB_HOST_STATUS_BK_ERRORFLOW_Pos)
1572 #define USB_HOST_STATUS_BK_MASK _U_(0x03)
1575 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1587 #define USB_HOST_CTRL_PIPE_OFFSET 0x00C
1588 #define USB_HOST_CTRL_PIPE_RESETVALUE _U_(0x0000)
1590 #define USB_HOST_CTRL_PIPE_PDADDR_Pos 0
1591 #define USB_HOST_CTRL_PIPE_PDADDR_Msk (_U_(0x7F) << USB_HOST_CTRL_PIPE_PDADDR_Pos)
1592 #define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
1593 #define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8
1594 #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
1595 #define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
1596 #define USB_HOST_CTRL_PIPE_PERMAX_Pos 12
1597 #define USB_HOST_CTRL_PIPE_PERMAX_Msk (_U_(0xF) << USB_HOST_CTRL_PIPE_PERMAX_Pos)
1598 #define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
1599 #define USB_HOST_CTRL_PIPE_MASK _U_(0xFF7F)
1602 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1617 #define USB_HOST_STATUS_PIPE_OFFSET 0x00E
1619 #define USB_HOST_STATUS_PIPE_DTGLER_Pos 0
1620 #define USB_HOST_STATUS_PIPE_DTGLER (_U_(0x1) << USB_HOST_STATUS_PIPE_DTGLER_Pos)
1621 #define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1
1622 #define USB_HOST_STATUS_PIPE_DAPIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_DAPIDER_Pos)
1623 #define USB_HOST_STATUS_PIPE_PIDER_Pos 2
1624 #define USB_HOST_STATUS_PIPE_PIDER (_U_(0x1) << USB_HOST_STATUS_PIPE_PIDER_Pos)
1625 #define USB_HOST_STATUS_PIPE_TOUTER_Pos 3
1626 #define USB_HOST_STATUS_PIPE_TOUTER (_U_(0x1) << USB_HOST_STATUS_PIPE_TOUTER_Pos)
1627 #define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4
1628 #define USB_HOST_STATUS_PIPE_CRC16ER (_U_(0x1) << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
1629 #define USB_HOST_STATUS_PIPE_ERCNT_Pos 5
1630 #define USB_HOST_STATUS_PIPE_ERCNT_Msk (_U_(0x7) << USB_HOST_STATUS_PIPE_ERCNT_Pos)
1631 #define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
1632 #define USB_HOST_STATUS_PIPE_MASK _U_(0x00FF)
1635 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1646 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1659 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1674 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1690 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1721 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1753 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1760 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1766 #define SECTION_USB_DESCRIPTOR
1768 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR
Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear.
__IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR
Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag.
UsbDeviceEndpoint hardware registers.
__IO USB_HOST_INTENSET_Type INTENSET
Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set.
__I USB_DEVICE_FNUM_Type FNUM
Offset: 0x010 (R/ 16) DEVICE Device Frame Number.
__IO USB_HOST_HSOFC_Type HSOFC
Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control.
__O USB_HOST_PSTATUSCLR_Type PSTATUSCLR
Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear.
__IO USB_CTRLA_Type CTRLA
Offset: 0x000 (R/W 8) Control A.
__IO USB_DEVICE_INTFLAG_Type INTFLAG
Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag.
__IO USB_HOST_FNUM_Type FNUM
Offset: 0x010 (R/W 16) HOST Host Frame Number.
__I USB_HOST_PINTSMRY_Type PINTSMRY
Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary.
__IO USB_DEVICE_INTENSET_Type INTENSET
Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set.
__IO USB_DEVICE_INTENCLR_Type INTENCLR
Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear.
__IO USB_QOSCTRL_Type QOSCTRL
Offset: 0x003 (R/W 8) USB Quality Of Service.
__IO USB_HOST_EXTREG_Type EXTREG
Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended.
__O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET
Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set.
USB_DEVICE APB hardware registers.
__IO USB_HOST_PINTFLAG_Type PINTFLAG
Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag.
__I USB_HOST_PSTATUS_Type PSTATUS
Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status.
__I USB_DEVICE_EPINTSMRY_Type EPINTSMRY
Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary.
UsbDevice DEVICE
Offset: 0x000 USB is Device.
__IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG
Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag.
USB_HOST Descriptor SRAM registers.
__IO USB_DEVICE_CTRLB_Type CTRLB
Offset: 0x008 (R/W 16) DEVICE Control B.
__I USB_HOST_FLENHIGH_Type FLENHIGH
Offset: 0x012 (R/ 8) HOST Host Frame Length.
uint32_t MULTI_PACKET_SIZE
__IO USB_DESCADD_Type DESCADD
Offset: 0x024 (R/W 32) Descriptor Address.
UsbDeviceDescBank SRAM registers.
__IO USB_PADCAL_Type PADCAL
Offset: 0x028 (R/W 16) USB PAD Calibration.
USB_DEVICE Descriptor SRAM registers.
__IO USB_HOST_PCKSIZE_Type PCKSIZE
Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size.
__I USB_DEVICE_EPSTATUS_Type EPSTATUS
Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status.
__IO USB_HOST_INTFLAG_Type INTFLAG
Offset: 0x01C (R/W 16) HOST Host Interrupt Flag.
__I USB_DEVICE_STATUS_Type STATUS
Offset: 0x00C (R/ 8) DEVICE Status.
__IO USB_HOST_PINTENCLR_Type PINTENCLR
Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear.
uint32_t MULTI_PACKET_SIZE
__IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE
Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe.
__IO USB_HOST_PINTENSET_Type PINTENSET
Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set.
__IO USB_HOST_STATUS_Type STATUS
Offset: 0x00C (R/W 8) HOST Status.
__I USB_SYNCBUSY_Type SYNCBUSY
Offset: 0x002 (R/ 8) Synchronization Busy.
__IO USB_DEVICE_EPCFG_Type EPCFG
Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration.
__IO USB_HOST_ADDR_Type ADDR
Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer.
__IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE
Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe.
__IO USB_HOST_PCFG_Type PCFG
Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration.
__IO USB_DEVICE_DADD_Type DADD
Offset: 0x00A (R/W 8) DEVICE Device Address.
__I USB_FSMSTATUS_Type FSMSTATUS
Offset: 0x00D (R/ 8) Finite State Machine Status.
__IO USB_DEVICE_EXTREG_Type EXTREG
Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended.
__IO USB_DEVICE_PCKSIZE_Type PCKSIZE
Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size.
__IO USB_DESCADD_Type DESCADD
Offset: 0x024 (R/W 32) Descriptor Address.
__IO USB_DEVICE_EPINTENSET_Type EPINTENSET
Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag.
__IO USB_HOST_STATUS_BK_Type STATUS_BK
Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank.
__IO USB_QOSCTRL_Type QOSCTRL
Offset: 0x003 (R/W 8) USB Quality Of Service.
__IO USB_HOST_BINTERVAL_Type BINTERVAL
Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe.
USB_HOST hardware registers.
volatile const uint8_t RoReg8
UsbHostDescBank SRAM registers.
__I USB_FSMSTATUS_Type FSMSTATUS
Offset: 0x00D (R/ 8) Finite State Machine Status.
__I USB_SYNCBUSY_Type SYNCBUSY
Offset: 0x002 (R/ 8) Synchronization Busy.
__IO USB_DEVICE_STATUS_BK_Type STATUS_BK
Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank.
UsbHostPipe hardware registers.
__IO USB_HOST_INTENCLR_Type INTENCLR
Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear.
__IO USB_HOST_CTRLB_Type CTRLB
Offset: 0x008 (R/W 16) HOST Control B.
__IO USB_PADCAL_Type PADCAL
Offset: 0x028 (R/W 16) USB PAD Calibration.
__O USB_HOST_PSTATUSSET_Type PSTATUSSET
Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set.
__IO USB_DEVICE_ADDR_Type ADDR
Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer.
__IO USB_CTRLA_Type CTRLA
Offset: 0x000 (R/W 8) Control A.
UsbHost HOST
Offset: 0x000 USB is Host.