SAME54P20A Test Project
dsu.h
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1 
30 #ifndef _SAME54_DSU_INSTANCE_
31 #define _SAME54_DSU_INSTANCE_
32 
33 /* ========== Register definition for DSU peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_DSU_CTRL (0x41002000)
36 #define REG_DSU_STATUSA (0x41002001)
37 #define REG_DSU_STATUSB (0x41002002)
38 #define REG_DSU_ADDR (0x41002004)
39 #define REG_DSU_LENGTH (0x41002008)
40 #define REG_DSU_DATA (0x4100200C)
41 #define REG_DSU_DCC0 (0x41002010)
42 #define REG_DSU_DCC1 (0x41002014)
43 #define REG_DSU_DID (0x41002018)
44 #define REG_DSU_CFG (0x4100201C)
45 #define REG_DSU_ENTRY0 (0x41003000)
46 #define REG_DSU_ENTRY1 (0x41003004)
47 #define REG_DSU_END (0x41003008)
48 #define REG_DSU_MEMTYPE (0x41003FCC)
49 #define REG_DSU_PID4 (0x41003FD0)
50 #define REG_DSU_PID5 (0x41003FD4)
51 #define REG_DSU_PID6 (0x41003FD8)
52 #define REG_DSU_PID7 (0x41003FDC)
53 #define REG_DSU_PID0 (0x41003FE0)
54 #define REG_DSU_PID1 (0x41003FE4)
55 #define REG_DSU_PID2 (0x41003FE8)
56 #define REG_DSU_PID3 (0x41003FEC)
57 #define REG_DSU_CID0 (0x41003FF0)
58 #define REG_DSU_CID1 (0x41003FF4)
59 #define REG_DSU_CID2 (0x41003FF8)
60 #define REG_DSU_CID3 (0x41003FFC)
61 #else
62 #define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL)
63 #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL)
64 #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL)
65 #define REG_DSU_ADDR (*(RwReg *)0x41002004UL)
66 #define REG_DSU_LENGTH (*(RwReg *)0x41002008UL)
67 #define REG_DSU_DATA (*(RwReg *)0x4100200CUL)
68 #define REG_DSU_DCC0 (*(RwReg *)0x41002010UL)
69 #define REG_DSU_DCC1 (*(RwReg *)0x41002014UL)
70 #define REG_DSU_DID (*(RoReg *)0x41002018UL)
71 #define REG_DSU_CFG (*(RwReg *)0x4100201CUL)
72 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL)
73 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL)
74 #define REG_DSU_END (*(RoReg *)0x41003008UL)
75 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL)
76 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL)
77 #define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL)
78 #define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL)
79 #define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL)
80 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL)
81 #define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL)
82 #define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL)
83 #define REG_DSU_PID3 (*(RoReg *)0x41003FECUL)
84 #define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL)
85 #define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL)
86 #define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL)
87 #define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL)
88 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
89 
90 /* ========== Instance parameters for DSU peripheral ========== */
91 #define DSU_CLK_AHB_ID 4
92 #define DSU_DMAC_ID_DCC0 2 // DMAC ID for DCC0 register
93 #define DSU_DMAC_ID_DCC1 3 // DMAC ID for DCC1 register
94 
95 #endif /* _SAME54_DSU_INSTANCE_ */