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30 #ifndef _SAME54_DSU_COMPONENT_
31 #define _SAME54_DSU_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
59 #define DSU_CTRL_OFFSET 0x0000
60 #define DSU_CTRL_RESETVALUE _U_(0x00)
62 #define DSU_CTRL_SWRST_Pos 0
63 #define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos)
64 #define DSU_CTRL_CRC_Pos 2
65 #define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos)
66 #define DSU_CTRL_MBIST_Pos 3
67 #define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos)
68 #define DSU_CTRL_CE_Pos 4
69 #define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos)
70 #define DSU_CTRL_ARR_Pos 6
71 #define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos)
72 #define DSU_CTRL_SMSA_Pos 7
73 #define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos)
74 #define DSU_CTRL_MASK _U_(0xDD)
77 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
91 #define DSU_STATUSA_OFFSET 0x0001
92 #define DSU_STATUSA_RESETVALUE _U_(0x00)
94 #define DSU_STATUSA_DONE_Pos 0
95 #define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos)
96 #define DSU_STATUSA_CRSTEXT_Pos 1
97 #define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)
98 #define DSU_STATUSA_BERR_Pos 2
99 #define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos)
100 #define DSU_STATUSA_FAIL_Pos 3
101 #define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos)
102 #define DSU_STATUSA_PERR_Pos 4
103 #define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos)
104 #define DSU_STATUSA_MASK _U_(0x1F)
107 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
127 #define DSU_STATUSB_OFFSET 0x0002
128 #define DSU_STATUSB_RESETVALUE _U_(0x00)
130 #define DSU_STATUSB_PROT_Pos 0
131 #define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos)
132 #define DSU_STATUSB_DBGPRES_Pos 1
133 #define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)
134 #define DSU_STATUSB_DCCD0_Pos 2
135 #define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos)
136 #define DSU_STATUSB_DCCD1_Pos 3
137 #define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos)
138 #define DSU_STATUSB_DCCD_Pos 2
139 #define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos)
140 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
141 #define DSU_STATUSB_HPE_Pos 4
142 #define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos)
143 #define DSU_STATUSB_CELCK_Pos 5
144 #define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos)
145 #define DSU_STATUSB_MASK _U_(0x3F)
148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
158 #define DSU_ADDR_OFFSET 0x0004
159 #define DSU_ADDR_RESETVALUE _U_(0x00000000)
161 #define DSU_ADDR_AMOD_Pos 0
162 #define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos)
163 #define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
164 #define DSU_ADDR_ADDR_Pos 2
165 #define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
166 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
167 #define DSU_ADDR_MASK _U_(0xFFFFFFFF)
170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
180 #define DSU_LENGTH_OFFSET 0x0008
181 #define DSU_LENGTH_RESETVALUE _U_(0x00000000)
183 #define DSU_LENGTH_LENGTH_Pos 2
184 #define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
185 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
186 #define DSU_LENGTH_MASK _U_(0xFFFFFFFC)
189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
198 #define DSU_DATA_OFFSET 0x000C
199 #define DSU_DATA_RESETVALUE _U_(0x00000000)
201 #define DSU_DATA_DATA_Pos 0
202 #define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
203 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
204 #define DSU_DATA_MASK _U_(0xFFFFFFFF)
207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
216 #define DSU_DCC_OFFSET 0x0010
217 #define DSU_DCC_RESETVALUE _U_(0x00000000)
219 #define DSU_DCC_DATA_Pos 0
220 #define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
221 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
222 #define DSU_DCC_MASK _U_(0xFFFFFFFF)
225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
240 #define DSU_DID_OFFSET 0x0018
242 #define DSU_DID_DEVSEL_Pos 0
243 #define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos)
244 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
245 #define DSU_DID_REVISION_Pos 8
246 #define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos)
247 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
248 #define DSU_DID_DIE_Pos 12
249 #define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos)
250 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
251 #define DSU_DID_SERIES_Pos 16
252 #define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos)
253 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
254 #define DSU_DID_SERIES_0_Val _U_(0x0)
255 #define DSU_DID_SERIES_1_Val _U_(0x1)
256 #define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos)
257 #define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos)
258 #define DSU_DID_FAMILY_Pos 23
259 #define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos)
260 #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
261 #define DSU_DID_FAMILY_0_Val _U_(0x0)
262 #define DSU_DID_FAMILY_1_Val _U_(0x1)
263 #define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos)
264 #define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos)
265 #define DSU_DID_PROCESSOR_Pos 28
266 #define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos)
267 #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
268 #define DSU_DID_PROCESSOR_CM0P_Val _U_(0x1)
269 #define DSU_DID_PROCESSOR_CM23_Val _U_(0x2)
270 #define DSU_DID_PROCESSOR_CM3_Val _U_(0x3)
271 #define DSU_DID_PROCESSOR_CM4_Val _U_(0x5)
272 #define DSU_DID_PROCESSOR_CM4F_Val _U_(0x6)
273 #define DSU_DID_PROCESSOR_CM33_Val _U_(0x7)
274 #define DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos)
275 #define DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos)
276 #define DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos)
277 #define DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos)
278 #define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos)
279 #define DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos)
280 #define DSU_DID_MASK _U_(0xFFBFFFFF)
283 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
295 #define DSU_CFG_OFFSET 0x001C
296 #define DSU_CFG_RESETVALUE _U_(0x00000002)
298 #define DSU_CFG_LQOS_Pos 0
299 #define DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos)
300 #define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos))
301 #define DSU_CFG_DCCDMALEVEL_Pos 2
302 #define DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos)
303 #define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos))
304 #define DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0)
305 #define DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1)
306 #define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos)
307 #define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos)
308 #define DSU_CFG_ETBRAMEN_Pos 4
309 #define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)
310 #define DSU_CFG_MASK _U_(0x0000001F)
313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
325 #define DSU_ENTRY0_OFFSET 0x1000
326 #define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002)
328 #define DSU_ENTRY0_EPRES_Pos 0
329 #define DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)
330 #define DSU_ENTRY0_FMT_Pos 1
331 #define DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos)
332 #define DSU_ENTRY0_ADDOFF_Pos 12
333 #define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)
334 #define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
335 #define DSU_ENTRY0_MASK _U_(0xFFFFF003)
338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
344 #define DSU_ENTRY1_OFFSET 0x1004
345 #define DSU_ENTRY1_RESETVALUE _U_(0x00000000)
346 #define DSU_ENTRY1_MASK _U_(0xFFFFFFFF)
349 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
358 #define DSU_END_OFFSET 0x1008
359 #define DSU_END_RESETVALUE _U_(0x00000000)
361 #define DSU_END_END_Pos 0
362 #define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos)
363 #define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
364 #define DSU_END_MASK _U_(0xFFFFFFFF)
367 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
377 #define DSU_MEMTYPE_OFFSET 0x1FCC
378 #define DSU_MEMTYPE_RESETVALUE _U_(0x00000000)
380 #define DSU_MEMTYPE_SMEMP_Pos 0
381 #define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)
382 #define DSU_MEMTYPE_MASK _U_(0x00000001)
385 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
396 #define DSU_PID4_OFFSET 0x1FD0
397 #define DSU_PID4_RESETVALUE _U_(0x00000000)
399 #define DSU_PID4_JEPCC_Pos 0
400 #define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos)
401 #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
402 #define DSU_PID4_FKBC_Pos 4
403 #define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos)
404 #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
405 #define DSU_PID4_MASK _U_(0x000000FF)
408 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
414 #define DSU_PID5_OFFSET 0x1FD4
415 #define DSU_PID5_RESETVALUE _U_(0x00000000)
416 #define DSU_PID5_MASK _U_(0x00000000)
419 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
425 #define DSU_PID6_OFFSET 0x1FD8
426 #define DSU_PID6_RESETVALUE _U_(0x00000000)
427 #define DSU_PID6_MASK _U_(0x00000000)
430 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
436 #define DSU_PID7_OFFSET 0x1FDC
437 #define DSU_PID7_RESETVALUE _U_(0x00000000)
438 #define DSU_PID7_MASK _U_(0x00000000)
441 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
451 #define DSU_PID0_OFFSET 0x1FE0
452 #define DSU_PID0_RESETVALUE _U_(0x000000D0)
454 #define DSU_PID0_PARTNBL_Pos 0
455 #define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)
456 #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
457 #define DSU_PID0_MASK _U_(0x000000FF)
460 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
471 #define DSU_PID1_OFFSET 0x1FE4
472 #define DSU_PID1_RESETVALUE _U_(0x000000FC)
474 #define DSU_PID1_PARTNBH_Pos 0
475 #define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos)
476 #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
477 #define DSU_PID1_JEPIDCL_Pos 4
478 #define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)
479 #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
480 #define DSU_PID1_MASK _U_(0x000000FF)
483 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
495 #define DSU_PID2_OFFSET 0x1FE8
496 #define DSU_PID2_RESETVALUE _U_(0x00000009)
498 #define DSU_PID2_JEPIDCH_Pos 0
499 #define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)
500 #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
501 #define DSU_PID2_JEPU_Pos 3
502 #define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos)
503 #define DSU_PID2_REVISION_Pos 4
504 #define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos)
505 #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
506 #define DSU_PID2_MASK _U_(0x000000FF)
509 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
520 #define DSU_PID3_OFFSET 0x1FEC
521 #define DSU_PID3_RESETVALUE _U_(0x00000000)
523 #define DSU_PID3_CUSMOD_Pos 0
524 #define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos)
525 #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
526 #define DSU_PID3_REVAND_Pos 4
527 #define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos)
528 #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
529 #define DSU_PID3_MASK _U_(0x000000FF)
532 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
542 #define DSU_CID0_OFFSET 0x1FF0
543 #define DSU_CID0_RESETVALUE _U_(0x0000000D)
545 #define DSU_CID0_PREAMBLEB0_Pos 0
546 #define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
547 #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
548 #define DSU_CID0_MASK _U_(0x000000FF)
551 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
562 #define DSU_CID1_OFFSET 0x1FF4
563 #define DSU_CID1_RESETVALUE _U_(0x00000010)
565 #define DSU_CID1_PREAMBLE_Pos 0
566 #define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)
567 #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
568 #define DSU_CID1_CCLASS_Pos 4
569 #define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos)
570 #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
571 #define DSU_CID1_MASK _U_(0x000000FF)
574 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
584 #define DSU_CID2_OFFSET 0x1FF8
585 #define DSU_CID2_RESETVALUE _U_(0x00000005)
587 #define DSU_CID2_PREAMBLEB2_Pos 0
588 #define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
589 #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
590 #define DSU_CID2_MASK _U_(0x000000FF)
593 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
603 #define DSU_CID3_OFFSET 0x1FFC
604 #define DSU_CID3_RESETVALUE _U_(0x000000B1)
606 #define DSU_CID3_PREAMBLEB3_Pos 0
607 #define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
608 #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
609 #define DSU_CID3_MASK _U_(0x000000FF)
612 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__I DSU_CID2_Type CID2
Offset: 0x1FF8 (R/ 32) Component Identification 2.
__I DSU_PID2_Type PID2
Offset: 0x1FE8 (R/ 32) Peripheral Identification 2.
__I DSU_PID3_Type PID3
Offset: 0x1FEC (R/ 32) Peripheral Identification 3.
__I DSU_STATUSB_Type STATUSB
Offset: 0x0002 (R/ 8) Status B.
__IO DSU_LENGTH_Type LENGTH
Offset: 0x0008 (R/W 32) Length.
__IO DSU_ADDR_Type ADDR
Offset: 0x0004 (R/W 32) Address.
__I DSU_PID5_Type PID5
Offset: 0x1FD4 (R/ 32) Peripheral Identification 5.
__I DSU_PID7_Type PID7
Offset: 0x1FDC (R/ 32) Peripheral Identification 7.
__O DSU_CTRL_Type CTRL
Offset: 0x0000 ( /W 8) Control.
__I DSU_ENTRY1_Type ENTRY1
Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1.
__I DSU_PID0_Type PID0
Offset: 0x1FE0 (R/ 32) Peripheral Identification 0.
__I DSU_CID1_Type CID1
Offset: 0x1FF4 (R/ 32) Component Identification 1.
__IO DSU_DATA_Type DATA
Offset: 0x000C (R/W 32) Data.
__I DSU_PID4_Type PID4
Offset: 0x1FD0 (R/ 32) Peripheral Identification 4.
__I DSU_END_Type END
Offset: 0x1008 (R/ 32) CoreSight ROM Table End.
__I DSU_ENTRY0_Type ENTRY0
Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0.
__I DSU_MEMTYPE_Type MEMTYPE
Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type.
__I DSU_PID6_Type PID6
Offset: 0x1FD8 (R/ 32) Peripheral Identification 6.
volatile const uint8_t RoReg8
__I DSU_PID1_Type PID1
Offset: 0x1FE4 (R/ 32) Peripheral Identification 1.
__I DSU_CID3_Type CID3
Offset: 0x1FFC (R/ 32) Component Identification 3.
__IO DSU_STATUSA_Type STATUSA
Offset: 0x0001 (R/W 8) Status A.
__I DSU_CID0_Type CID0
Offset: 0x1FF0 (R/ 32) Component Identification 0.
__I DSU_DID_Type DID
Offset: 0x0018 (R/ 32) Device Identification.
__IO DSU_CFG_Type CFG
Offset: 0x001C (R/W 32) Configuration.