SAME54P20A Test Project
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Component description for PORT. More...
Go to the source code of this file.
Data Structures | |
union | PORT_DIR_Type |
union | PORT_DIRCLR_Type |
union | PORT_DIRSET_Type |
union | PORT_DIRTGL_Type |
union | PORT_OUT_Type |
union | PORT_OUTCLR_Type |
union | PORT_OUTSET_Type |
union | PORT_OUTTGL_Type |
union | PORT_IN_Type |
union | PORT_CTRL_Type |
union | PORT_WRCONFIG_Type |
union | PORT_EVCTRL_Type |
union | PORT_PMUX_Type |
union | PORT_PINCFG_Type |
struct | PortGroup |
PortGroup hardware registers. More... | |
struct | Port |
PORT hardware registers. More... | |
Macros | |
#define | PORT_U2210 |
#define | REV_PORT 0x220 |
#define | PORT_DIR_OFFSET 0x00 |
(PORT_DIR offset) Data Direction | |
#define | PORT_DIR_RESETVALUE _U_(0x00000000) |
(PORT_DIR reset_value) Data Direction | |
#define | PORT_DIR_DIR_Pos 0 |
(PORT_DIR) Port Data Direction | |
#define | PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos) |
#define | PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)) |
#define | PORT_DIR_MASK _U_(0xFFFFFFFF) |
(PORT_DIR) MASK Register | |
#define | PORT_DIRCLR_OFFSET 0x04 |
(PORT_DIRCLR offset) Data Direction Clear | |
#define | PORT_DIRCLR_RESETVALUE _U_(0x00000000) |
(PORT_DIRCLR reset_value) Data Direction Clear | |
#define | PORT_DIRCLR_DIRCLR_Pos 0 |
(PORT_DIRCLR) Port Data Direction Clear | |
#define | PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos) |
#define | PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)) |
#define | PORT_DIRCLR_MASK _U_(0xFFFFFFFF) |
(PORT_DIRCLR) MASK Register | |
#define | PORT_DIRSET_OFFSET 0x08 |
(PORT_DIRSET offset) Data Direction Set | |
#define | PORT_DIRSET_RESETVALUE _U_(0x00000000) |
(PORT_DIRSET reset_value) Data Direction Set | |
#define | PORT_DIRSET_DIRSET_Pos 0 |
(PORT_DIRSET) Port Data Direction Set | |
#define | PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos) |
#define | PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)) |
#define | PORT_DIRSET_MASK _U_(0xFFFFFFFF) |
(PORT_DIRSET) MASK Register | |
#define | PORT_DIRTGL_OFFSET 0x0C |
(PORT_DIRTGL offset) Data Direction Toggle | |
#define | PORT_DIRTGL_RESETVALUE _U_(0x00000000) |
(PORT_DIRTGL reset_value) Data Direction Toggle | |
#define | PORT_DIRTGL_DIRTGL_Pos 0 |
(PORT_DIRTGL) Port Data Direction Toggle | |
#define | PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos) |
#define | PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)) |
#define | PORT_DIRTGL_MASK _U_(0xFFFFFFFF) |
(PORT_DIRTGL) MASK Register | |
#define | PORT_OUT_OFFSET 0x10 |
(PORT_OUT offset) Data Output Value | |
#define | PORT_OUT_RESETVALUE _U_(0x00000000) |
(PORT_OUT reset_value) Data Output Value | |
#define | PORT_OUT_OUT_Pos 0 |
(PORT_OUT) PORT Data Output Value | |
#define | PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos) |
#define | PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)) |
#define | PORT_OUT_MASK _U_(0xFFFFFFFF) |
(PORT_OUT) MASK Register | |
#define | PORT_OUTCLR_OFFSET 0x14 |
(PORT_OUTCLR offset) Data Output Value Clear | |
#define | PORT_OUTCLR_RESETVALUE _U_(0x00000000) |
(PORT_OUTCLR reset_value) Data Output Value Clear | |
#define | PORT_OUTCLR_OUTCLR_Pos 0 |
(PORT_OUTCLR) PORT Data Output Value Clear | |
#define | PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos) |
#define | PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)) |
#define | PORT_OUTCLR_MASK _U_(0xFFFFFFFF) |
(PORT_OUTCLR) MASK Register | |
#define | PORT_OUTSET_OFFSET 0x18 |
(PORT_OUTSET offset) Data Output Value Set | |
#define | PORT_OUTSET_RESETVALUE _U_(0x00000000) |
(PORT_OUTSET reset_value) Data Output Value Set | |
#define | PORT_OUTSET_OUTSET_Pos 0 |
(PORT_OUTSET) PORT Data Output Value Set | |
#define | PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos) |
#define | PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)) |
#define | PORT_OUTSET_MASK _U_(0xFFFFFFFF) |
(PORT_OUTSET) MASK Register | |
#define | PORT_OUTTGL_OFFSET 0x1C |
(PORT_OUTTGL offset) Data Output Value Toggle | |
#define | PORT_OUTTGL_RESETVALUE _U_(0x00000000) |
(PORT_OUTTGL reset_value) Data Output Value Toggle | |
#define | PORT_OUTTGL_OUTTGL_Pos 0 |
(PORT_OUTTGL) PORT Data Output Value Toggle | |
#define | PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos) |
#define | PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)) |
#define | PORT_OUTTGL_MASK _U_(0xFFFFFFFF) |
(PORT_OUTTGL) MASK Register | |
#define | PORT_IN_OFFSET 0x20 |
(PORT_IN offset) Data Input Value | |
#define | PORT_IN_RESETVALUE _U_(0x00000000) |
(PORT_IN reset_value) Data Input Value | |
#define | PORT_IN_IN_Pos 0 |
(PORT_IN) PORT Data Input Value | |
#define | PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos) |
#define | PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)) |
#define | PORT_IN_MASK _U_(0xFFFFFFFF) |
(PORT_IN) MASK Register | |
#define | PORT_CTRL_OFFSET 0x24 |
(PORT_CTRL offset) Control | |
#define | PORT_CTRL_RESETVALUE _U_(0x00000000) |
(PORT_CTRL reset_value) Control | |
#define | PORT_CTRL_SAMPLING_Pos 0 |
(PORT_CTRL) Input Sampling Mode | |
#define | PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) |
#define | PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)) |
#define | PORT_CTRL_MASK _U_(0xFFFFFFFF) |
(PORT_CTRL) MASK Register | |
#define | PORT_WRCONFIG_OFFSET 0x28 |
(PORT_WRCONFIG offset) Write Configuration | |
#define | PORT_WRCONFIG_RESETVALUE _U_(0x00000000) |
(PORT_WRCONFIG reset_value) Write Configuration | |
#define | PORT_WRCONFIG_PINMASK_Pos 0 |
(PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration | |
#define | PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) |
#define | PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)) |
#define | PORT_WRCONFIG_PMUXEN_Pos 16 |
(PORT_WRCONFIG) Peripheral Multiplexer Enable | |
#define | PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos) |
#define | PORT_WRCONFIG_INEN_Pos 17 |
(PORT_WRCONFIG) Input Enable | |
#define | PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos) |
#define | PORT_WRCONFIG_PULLEN_Pos 18 |
(PORT_WRCONFIG) Pull Enable | |
#define | PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos) |
#define | PORT_WRCONFIG_DRVSTR_Pos 22 |
(PORT_WRCONFIG) Output Driver Strength Selection | |
#define | PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos) |
#define | PORT_WRCONFIG_PMUX_Pos 24 |
(PORT_WRCONFIG) Peripheral Multiplexing | |
#define | PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos) |
#define | PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)) |
#define | PORT_WRCONFIG_WRPMUX_Pos 28 |
(PORT_WRCONFIG) Write PMUX | |
#define | PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos) |
#define | PORT_WRCONFIG_WRPINCFG_Pos 30 |
(PORT_WRCONFIG) Write PINCFG | |
#define | PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) |
#define | PORT_WRCONFIG_HWSEL_Pos 31 |
(PORT_WRCONFIG) Half-Word Select | |
#define | PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos) |
#define | PORT_WRCONFIG_MASK _U_(0xDF47FFFF) |
(PORT_WRCONFIG) MASK Register | |
#define | PORT_EVCTRL_OFFSET 0x2C |
(PORT_EVCTRL offset) Event Input Control | |
#define | PORT_EVCTRL_RESETVALUE _U_(0x00000000) |
(PORT_EVCTRL reset_value) Event Input Control | |
#define | PORT_EVCTRL_PID0_Pos 0 |
(PORT_EVCTRL) PORT Event Pin Identifier 0 | |
#define | PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos) |
#define | PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos)) |
#define | PORT_EVCTRL_EVACT0_Pos 5 |
(PORT_EVCTRL) PORT Event Action 0 | |
#define | PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos) |
#define | PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos)) |
#define | PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) |
(PORT_EVCTRL) Event output to pin | |
#define | PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) |
(PORT_EVCTRL) Set output register of pin on event | |
#define | PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) |
(PORT_EVCTRL) Clear output register of pin on event | |
#define | PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) |
(PORT_EVCTRL) Toggle output register of pin on event | |
#define | PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) |
#define | PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) |
#define | PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) |
#define | PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) |
#define | PORT_EVCTRL_PORTEI0_Pos 7 |
(PORT_EVCTRL) PORT Event Input Enable 0 | |
#define | PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos) |
#define | PORT_EVCTRL_PID1_Pos 8 |
(PORT_EVCTRL) PORT Event Pin Identifier 1 | |
#define | PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos) |
#define | PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos)) |
#define | PORT_EVCTRL_EVACT1_Pos 13 |
(PORT_EVCTRL) PORT Event Action 1 | |
#define | PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos) |
#define | PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos)) |
#define | PORT_EVCTRL_PORTEI1_Pos 15 |
(PORT_EVCTRL) PORT Event Input Enable 1 | |
#define | PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos) |
#define | PORT_EVCTRL_PID2_Pos 16 |
(PORT_EVCTRL) PORT Event Pin Identifier 2 | |
#define | PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos) |
#define | PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos)) |
#define | PORT_EVCTRL_EVACT2_Pos 21 |
(PORT_EVCTRL) PORT Event Action 2 | |
#define | PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos) |
#define | PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos)) |
#define | PORT_EVCTRL_PORTEI2_Pos 23 |
(PORT_EVCTRL) PORT Event Input Enable 2 | |
#define | PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos) |
#define | PORT_EVCTRL_PID3_Pos 24 |
(PORT_EVCTRL) PORT Event Pin Identifier 3 | |
#define | PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos) |
#define | PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos)) |
#define | PORT_EVCTRL_EVACT3_Pos 29 |
(PORT_EVCTRL) PORT Event Action 3 | |
#define | PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos) |
#define | PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos)) |
#define | PORT_EVCTRL_PORTEI3_Pos 31 |
(PORT_EVCTRL) PORT Event Input Enable 3 | |
#define | PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos) |
#define | PORT_EVCTRL_MASK _U_(0xFFFFFFFF) |
(PORT_EVCTRL) MASK Register | |
#define | PORT_PMUX_OFFSET 0x30 |
(PORT_PMUX offset) Peripheral Multiplexing | |
#define | PORT_PMUX_RESETVALUE _U_(0x00) |
(PORT_PMUX reset_value) Peripheral Multiplexing | |
#define | PORT_PMUX_PMUXE_Pos 0 |
(PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin | |
#define | PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos) |
#define | PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)) |
#define | PORT_PMUX_PMUXO_Pos 4 |
(PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin | |
#define | PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos) |
#define | PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)) |
#define | PORT_PMUX_MASK _U_(0xFF) |
(PORT_PMUX) MASK Register | |
#define | PORT_PINCFG_OFFSET 0x40 |
(PORT_PINCFG offset) Pin Configuration | |
#define | PORT_PINCFG_RESETVALUE _U_(0x00) |
(PORT_PINCFG reset_value) Pin Configuration | |
#define | PORT_PINCFG_PMUXEN_Pos 0 |
(PORT_PINCFG) Peripheral Multiplexer Enable | |
#define | PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos) |
#define | PORT_PINCFG_INEN_Pos 1 |
(PORT_PINCFG) Input Enable | |
#define | PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos) |
#define | PORT_PINCFG_PULLEN_Pos 2 |
(PORT_PINCFG) Pull Enable | |
#define | PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos) |
#define | PORT_PINCFG_DRVSTR_Pos 6 |
(PORT_PINCFG) Output Driver Strength Selection | |
#define | PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos) |
#define | PORT_PINCFG_MASK _U_(0x47) |
(PORT_PINCFG) MASK Register | |
Component description for PORT.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file port.h.