Definition at line 747 of file sercom.h.
◆ __pad0__
uint8_t SERCOM_USART_INTENCLR_Type::__pad0__ |
bit: 6 Reserved
Definition at line 755 of file sercom.h.
◆ bit
struct { ... } SERCOM_USART_INTENCLR_Type::bit |
Structure used for bit access
◆ CTSIC
uint8_t SERCOM_USART_INTENCLR_Type::CTSIC |
bit: 4 Clear To Send Input Change Interrupt Disable
Definition at line 753 of file sercom.h.
◆ DRE
uint8_t SERCOM_USART_INTENCLR_Type::DRE |
bit: 0 Data Register Empty Interrupt Disable
Definition at line 749 of file sercom.h.
◆ ERROR
uint8_t SERCOM_USART_INTENCLR_Type::ERROR |
bit: 7 Combined Error Interrupt Disable
Definition at line 756 of file sercom.h.
◆ reg
uint8_t SERCOM_USART_INTENCLR_Type::reg |
Type used for register access
Definition at line 758 of file sercom.h.
◆ RXBRK
uint8_t SERCOM_USART_INTENCLR_Type::RXBRK |
bit: 5 Break Received Interrupt Disable
Definition at line 754 of file sercom.h.
◆ RXC
uint8_t SERCOM_USART_INTENCLR_Type::RXC |
bit: 2 Receive Complete Interrupt Disable
Definition at line 751 of file sercom.h.
◆ RXS
uint8_t SERCOM_USART_INTENCLR_Type::RXS |
bit: 3 Receive Start Interrupt Disable
Definition at line 752 of file sercom.h.
◆ TXC
uint8_t SERCOM_USART_INTENCLR_Type::TXC |
bit: 1 Transmit Complete Interrupt Disable
Definition at line 750 of file sercom.h.
The documentation for this union was generated from the following file:
- /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/sercom.h