SAME54P20A Test Project
picop.h
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1 
44 #ifndef _SAME54_PICOP_INSTANCE_
45 #define _SAME54_PICOP_INSTANCE_
46 
47 /* ========== Register definition for PICOP peripheral ========== */
48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
49 #define REG_PICOP_ID0 (0x4100E000U)
50 #define REG_PICOP_ID1 (0x4100E004U)
51 #define REG_PICOP_ID2 (0x4100E008U)
52 #define REG_PICOP_ID3 (0x4100E00CU)
53 #define REG_PICOP_ID4 (0x4100E010U)
54 #define REG_PICOP_ID5 (0x4100E014U)
55 #define REG_PICOP_ID6 (0x4100E018U)
56 #define REG_PICOP_ID7 (0x4100E01CU)
57 #define REG_PICOP_CONFIG (0x4100E020U)
58 #define REG_PICOP_CTRL (0x4100E024U)
59 #define REG_PICOP_CMD (0x4100E028U)
60 #define REG_PICOP_PC (0x4100E02CU)
61 #define REG_PICOP_HF (0x4100E030U)
62 #define REG_PICOP_HFCTRL (0x4100E034U)
63 #define REG_PICOP_HFSETCLR0 (0x4100E038U)
64 #define REG_PICOP_HFSETCLR1 (0x4100E03CU)
65 #define REG_PICOP_OCDCONFIG (0x4100E050U)
66 #define REG_PICOP_OCDCONTROL (0x4100E054U)
67 #define REG_PICOP_OCDSTATUS (0x4100E058U)
68 #define REG_PICOP_OCDPC (0x4100E05CU)
69 #define REG_PICOP_OCDFEAT (0x4100E060U)
70 #define REG_PICOP_OCDCCNT (0x4100E068U)
71 #define REG_PICOP_OCDBPGEN0 (0x4100E070U)
72 #define REG_PICOP_OCDBPGEN1 (0x4100E074U)
73 #define REG_PICOP_OCDBPGEN2 (0x4100E078U)
74 #define REG_PICOP_OCDBPGEN3 (0x4100E07CU)
75 #define REG_PICOP_R3R0 (0x4100E080U)
76 #define REG_PICOP_R7R4 (0x4100E084U)
77 #define REG_PICOP_R11R8 (0x4100E088U)
78 #define REG_PICOP_R15R12 (0x4100E08CU)
79 #define REG_PICOP_R19R16 (0x4100E090U)
80 #define REG_PICOP_R23R20 (0x4100E094U)
81 #define REG_PICOP_R27R24 (0x4100E098U)
82 #define REG_PICOP_R31R28 (0x4100E09CU)
83 #define REG_PICOP_S1S0 (0x4100E0A0U)
84 #define REG_PICOP_S3S2 (0x4100E0A4U)
85 #define REG_PICOP_S5S4 (0x4100E0A8U)
86 #define REG_PICOP_S11S10 (0x4100E0B4U)
87 #define REG_PICOP_LINK (0x4100E0B8U)
88 #define REG_PICOP_SP (0x4100E0BCU)
89 #define REG_PICOP_MMUFLASH (0x4100E100U)
90 #define REG_PICOP_MMU0 (0x4100E118U)
91 #define REG_PICOP_MMU1 (0x4100E11CU)
92 #define REG_PICOP_MMUCTRL (0x4100E120U)
93 #define REG_PICOP_ICACHE (0x4100E180U)
94 #define REG_PICOP_ICACHELRU (0x4100E184U)
95 #define REG_PICOP_QOSCTRL (0x4100E200U)
96 #else
97 #define REG_PICOP_ID0 (*(RwReg *)0x4100E000U)
98 #define REG_PICOP_ID1 (*(RwReg *)0x4100E004U)
99 #define REG_PICOP_ID2 (*(RwReg *)0x4100E008U)
100 #define REG_PICOP_ID3 (*(RwReg *)0x4100E00CU)
101 #define REG_PICOP_ID4 (*(RwReg *)0x4100E010U)
102 #define REG_PICOP_ID5 (*(RwReg *)0x4100E014U)
103 #define REG_PICOP_ID6 (*(RwReg *)0x4100E018U)
104 #define REG_PICOP_ID7 (*(RwReg *)0x4100E01CU)
105 #define REG_PICOP_CONFIG (*(RwReg *)0x4100E020U)
106 #define REG_PICOP_CTRL (*(RwReg *)0x4100E024U)
107 #define REG_PICOP_CMD (*(RwReg *)0x4100E028U)
108 #define REG_PICOP_PC (*(RwReg *)0x4100E02CU)
109 #define REG_PICOP_HF (*(RwReg *)0x4100E030U)
110 #define REG_PICOP_HFCTRL (*(RwReg *)0x4100E034U)
111 #define REG_PICOP_HFSETCLR0 (*(RwReg *)0x4100E038U)
112 #define REG_PICOP_HFSETCLR1 (*(RwReg *)0x4100E03CU)
113 #define REG_PICOP_OCDCONFIG (*(RwReg *)0x4100E050U)
114 #define REG_PICOP_OCDCONTROL (*(RwReg *)0x4100E054U)
115 #define REG_PICOP_OCDSTATUS (*(RwReg *)0x4100E058U)
116 #define REG_PICOP_OCDPC (*(RwReg *)0x4100E05CU)
117 #define REG_PICOP_OCDFEAT (*(RwReg *)0x4100E060U)
118 #define REG_PICOP_OCDCCNT (*(RwReg *)0x4100E068U)
119 #define REG_PICOP_OCDBPGEN0 (*(RwReg *)0x4100E070U)
120 #define REG_PICOP_OCDBPGEN1 (*(RwReg *)0x4100E074U)
121 #define REG_PICOP_OCDBPGEN2 (*(RwReg *)0x4100E078U)
122 #define REG_PICOP_OCDBPGEN3 (*(RwReg *)0x4100E07CU)
123 #define REG_PICOP_R3R0 (*(RwReg *)0x4100E080U)
124 #define REG_PICOP_R7R4 (*(RwReg *)0x4100E084U)
125 #define REG_PICOP_R11R8 (*(RwReg *)0x4100E088U)
126 #define REG_PICOP_R15R12 (*(RwReg *)0x4100E08CU)
127 #define REG_PICOP_R19R16 (*(RwReg *)0x4100E090U)
128 #define REG_PICOP_R23R20 (*(RwReg *)0x4100E094U)
129 #define REG_PICOP_R27R24 (*(RwReg *)0x4100E098U)
130 #define REG_PICOP_R31R28 (*(RwReg *)0x4100E09CU)
131 #define REG_PICOP_S1S0 (*(RwReg *)0x4100E0A0U)
132 #define REG_PICOP_S3S2 (*(RwReg *)0x4100E0A4U)
133 #define REG_PICOP_S5S4 (*(RwReg *)0x4100E0A8U)
134 #define REG_PICOP_S11S10 (*(RwReg *)0x4100E0B4U)
135 #define REG_PICOP_LINK (*(RwReg *)0x4100E0B8U)
136 #define REG_PICOP_SP (*(RwReg *)0x4100E0BCU)
137 #define REG_PICOP_MMUFLASH (*(RwReg *)0x4100E100U)
138 #define REG_PICOP_MMU0 (*(RwReg *)0x4100E118U)
139 #define REG_PICOP_MMU1 (*(RwReg *)0x4100E11CU)
140 #define REG_PICOP_MMUCTRL (*(RwReg *)0x4100E120U)
141 #define REG_PICOP_ICACHE (*(RwReg *)0x4100E180U)
142 #define REG_PICOP_ICACHELRU (*(RwReg *)0x4100E184U)
143 #define REG_PICOP_QOSCTRL (*(RwReg *)0x4100E200U)
144 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
145 
146 
147 #endif /* _SAME54_PICOP_INSTANCE_ */