SAME54P20A Test Project
pdec.h
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1 
30 #ifndef _SAME54_PDEC_COMPONENT_
31 #define _SAME54_PDEC_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define PDEC_U2263
40 #define REV_PDEC 0x100
41 
42 /* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t SWRST:1;
47  uint32_t ENABLE:1;
48  uint32_t MODE:2;
49  uint32_t :2;
50  uint32_t RUNSTDBY:1;
51  uint32_t :1;
52  uint32_t CONF:3;
53  uint32_t ALOCK:1;
54  uint32_t :2;
55  uint32_t SWAP:1;
56  uint32_t PEREN:1;
57  uint32_t PINEN0:1;
58  uint32_t PINEN1:1;
59  uint32_t PINEN2:1;
60  uint32_t :1;
61  uint32_t PINVEN0:1;
62  uint32_t PINVEN1:1;
63  uint32_t PINVEN2:1;
64  uint32_t :1;
65  uint32_t ANGULAR:3;
66  uint32_t :1;
67  uint32_t MAXCMP:4;
68  } bit;
69  struct {
70  uint32_t :16;
71  uint32_t PINEN:3;
72  uint32_t :1;
73  uint32_t PINVEN:3;
74  uint32_t :9;
75  } vec;
76  uint32_t reg;
78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
79 
80 #define PDEC_CTRLA_OFFSET 0x00
81 #define PDEC_CTRLA_RESETVALUE _U_(0x00000000)
83 #define PDEC_CTRLA_SWRST_Pos 0
84 #define PDEC_CTRLA_SWRST (_U_(0x1) << PDEC_CTRLA_SWRST_Pos)
85 #define PDEC_CTRLA_ENABLE_Pos 1
86 #define PDEC_CTRLA_ENABLE (_U_(0x1) << PDEC_CTRLA_ENABLE_Pos)
87 #define PDEC_CTRLA_MODE_Pos 2
88 #define PDEC_CTRLA_MODE_Msk (_U_(0x3) << PDEC_CTRLA_MODE_Pos)
89 #define PDEC_CTRLA_MODE(value) (PDEC_CTRLA_MODE_Msk & ((value) << PDEC_CTRLA_MODE_Pos))
90 #define PDEC_CTRLA_MODE_QDEC_Val _U_(0x0)
91 #define PDEC_CTRLA_MODE_HALL_Val _U_(0x1)
92 #define PDEC_CTRLA_MODE_COUNTER_Val _U_(0x2)
93 #define PDEC_CTRLA_MODE_QDEC (PDEC_CTRLA_MODE_QDEC_Val << PDEC_CTRLA_MODE_Pos)
94 #define PDEC_CTRLA_MODE_HALL (PDEC_CTRLA_MODE_HALL_Val << PDEC_CTRLA_MODE_Pos)
95 #define PDEC_CTRLA_MODE_COUNTER (PDEC_CTRLA_MODE_COUNTER_Val << PDEC_CTRLA_MODE_Pos)
96 #define PDEC_CTRLA_RUNSTDBY_Pos 6
97 #define PDEC_CTRLA_RUNSTDBY (_U_(0x1) << PDEC_CTRLA_RUNSTDBY_Pos)
98 #define PDEC_CTRLA_CONF_Pos 8
99 #define PDEC_CTRLA_CONF_Msk (_U_(0x7) << PDEC_CTRLA_CONF_Pos)
100 #define PDEC_CTRLA_CONF(value) (PDEC_CTRLA_CONF_Msk & ((value) << PDEC_CTRLA_CONF_Pos))
101 #define PDEC_CTRLA_CONF_X4_Val _U_(0x0)
102 #define PDEC_CTRLA_CONF_X4S_Val _U_(0x1)
103 #define PDEC_CTRLA_CONF_X2_Val _U_(0x2)
104 #define PDEC_CTRLA_CONF_X2S_Val _U_(0x3)
105 #define PDEC_CTRLA_CONF_AUTOC_Val _U_(0x4)
106 #define PDEC_CTRLA_CONF_X4 (PDEC_CTRLA_CONF_X4_Val << PDEC_CTRLA_CONF_Pos)
107 #define PDEC_CTRLA_CONF_X4S (PDEC_CTRLA_CONF_X4S_Val << PDEC_CTRLA_CONF_Pos)
108 #define PDEC_CTRLA_CONF_X2 (PDEC_CTRLA_CONF_X2_Val << PDEC_CTRLA_CONF_Pos)
109 #define PDEC_CTRLA_CONF_X2S (PDEC_CTRLA_CONF_X2S_Val << PDEC_CTRLA_CONF_Pos)
110 #define PDEC_CTRLA_CONF_AUTOC (PDEC_CTRLA_CONF_AUTOC_Val << PDEC_CTRLA_CONF_Pos)
111 #define PDEC_CTRLA_ALOCK_Pos 11
112 #define PDEC_CTRLA_ALOCK (_U_(0x1) << PDEC_CTRLA_ALOCK_Pos)
113 #define PDEC_CTRLA_SWAP_Pos 14
114 #define PDEC_CTRLA_SWAP (_U_(0x1) << PDEC_CTRLA_SWAP_Pos)
115 #define PDEC_CTRLA_PEREN_Pos 15
116 #define PDEC_CTRLA_PEREN (_U_(0x1) << PDEC_CTRLA_PEREN_Pos)
117 #define PDEC_CTRLA_PINEN0_Pos 16
118 #define PDEC_CTRLA_PINEN0 (_U_(1) << PDEC_CTRLA_PINEN0_Pos)
119 #define PDEC_CTRLA_PINEN1_Pos 17
120 #define PDEC_CTRLA_PINEN1 (_U_(1) << PDEC_CTRLA_PINEN1_Pos)
121 #define PDEC_CTRLA_PINEN2_Pos 18
122 #define PDEC_CTRLA_PINEN2 (_U_(1) << PDEC_CTRLA_PINEN2_Pos)
123 #define PDEC_CTRLA_PINEN_Pos 16
124 #define PDEC_CTRLA_PINEN_Msk (_U_(0x7) << PDEC_CTRLA_PINEN_Pos)
125 #define PDEC_CTRLA_PINEN(value) (PDEC_CTRLA_PINEN_Msk & ((value) << PDEC_CTRLA_PINEN_Pos))
126 #define PDEC_CTRLA_PINVEN0_Pos 20
127 #define PDEC_CTRLA_PINVEN0 (_U_(1) << PDEC_CTRLA_PINVEN0_Pos)
128 #define PDEC_CTRLA_PINVEN1_Pos 21
129 #define PDEC_CTRLA_PINVEN1 (_U_(1) << PDEC_CTRLA_PINVEN1_Pos)
130 #define PDEC_CTRLA_PINVEN2_Pos 22
131 #define PDEC_CTRLA_PINVEN2 (_U_(1) << PDEC_CTRLA_PINVEN2_Pos)
132 #define PDEC_CTRLA_PINVEN_Pos 20
133 #define PDEC_CTRLA_PINVEN_Msk (_U_(0x7) << PDEC_CTRLA_PINVEN_Pos)
134 #define PDEC_CTRLA_PINVEN(value) (PDEC_CTRLA_PINVEN_Msk & ((value) << PDEC_CTRLA_PINVEN_Pos))
135 #define PDEC_CTRLA_ANGULAR_Pos 24
136 #define PDEC_CTRLA_ANGULAR_Msk (_U_(0x7) << PDEC_CTRLA_ANGULAR_Pos)
137 #define PDEC_CTRLA_ANGULAR(value) (PDEC_CTRLA_ANGULAR_Msk & ((value) << PDEC_CTRLA_ANGULAR_Pos))
138 #define PDEC_CTRLA_MAXCMP_Pos 28
139 #define PDEC_CTRLA_MAXCMP_Msk (_U_(0xF) << PDEC_CTRLA_MAXCMP_Pos)
140 #define PDEC_CTRLA_MAXCMP(value) (PDEC_CTRLA_MAXCMP_Msk & ((value) << PDEC_CTRLA_MAXCMP_Pos))
141 #define PDEC_CTRLA_MASK _U_(0xF777CF4F)
143 /* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */
144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
145 typedef union {
146  struct {
147  uint8_t :1;
148  uint8_t LUPD:1;
149  uint8_t :3;
150  uint8_t CMD:3;
151  } bit;
152  uint8_t reg;
154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
155 
156 #define PDEC_CTRLBCLR_OFFSET 0x04
157 #define PDEC_CTRLBCLR_RESETVALUE _U_(0x00)
159 #define PDEC_CTRLBCLR_LUPD_Pos 1
160 #define PDEC_CTRLBCLR_LUPD (_U_(0x1) << PDEC_CTRLBCLR_LUPD_Pos)
161 #define PDEC_CTRLBCLR_CMD_Pos 5
162 #define PDEC_CTRLBCLR_CMD_Msk (_U_(0x7) << PDEC_CTRLBCLR_CMD_Pos)
163 #define PDEC_CTRLBCLR_CMD(value) (PDEC_CTRLBCLR_CMD_Msk & ((value) << PDEC_CTRLBCLR_CMD_Pos))
164 #define PDEC_CTRLBCLR_CMD_NONE_Val _U_(0x0)
165 #define PDEC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1)
166 #define PDEC_CTRLBCLR_CMD_UPDATE_Val _U_(0x2)
167 #define PDEC_CTRLBCLR_CMD_READSYNC_Val _U_(0x3)
168 #define PDEC_CTRLBCLR_CMD_START_Val _U_(0x4)
169 #define PDEC_CTRLBCLR_CMD_STOP_Val _U_(0x5)
170 #define PDEC_CTRLBCLR_CMD_NONE (PDEC_CTRLBCLR_CMD_NONE_Val << PDEC_CTRLBCLR_CMD_Pos)
171 #define PDEC_CTRLBCLR_CMD_RETRIGGER (PDEC_CTRLBCLR_CMD_RETRIGGER_Val << PDEC_CTRLBCLR_CMD_Pos)
172 #define PDEC_CTRLBCLR_CMD_UPDATE (PDEC_CTRLBCLR_CMD_UPDATE_Val << PDEC_CTRLBCLR_CMD_Pos)
173 #define PDEC_CTRLBCLR_CMD_READSYNC (PDEC_CTRLBCLR_CMD_READSYNC_Val << PDEC_CTRLBCLR_CMD_Pos)
174 #define PDEC_CTRLBCLR_CMD_START (PDEC_CTRLBCLR_CMD_START_Val << PDEC_CTRLBCLR_CMD_Pos)
175 #define PDEC_CTRLBCLR_CMD_STOP (PDEC_CTRLBCLR_CMD_STOP_Val << PDEC_CTRLBCLR_CMD_Pos)
176 #define PDEC_CTRLBCLR_MASK _U_(0xE2)
178 /* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */
179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
180 typedef union {
181  struct {
182  uint8_t :1;
183  uint8_t LUPD:1;
184  uint8_t :3;
185  uint8_t CMD:3;
186  } bit;
187  uint8_t reg;
189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
190 
191 #define PDEC_CTRLBSET_OFFSET 0x05
192 #define PDEC_CTRLBSET_RESETVALUE _U_(0x00)
194 #define PDEC_CTRLBSET_LUPD_Pos 1
195 #define PDEC_CTRLBSET_LUPD (_U_(0x1) << PDEC_CTRLBSET_LUPD_Pos)
196 #define PDEC_CTRLBSET_CMD_Pos 5
197 #define PDEC_CTRLBSET_CMD_Msk (_U_(0x7) << PDEC_CTRLBSET_CMD_Pos)
198 #define PDEC_CTRLBSET_CMD(value) (PDEC_CTRLBSET_CMD_Msk & ((value) << PDEC_CTRLBSET_CMD_Pos))
199 #define PDEC_CTRLBSET_CMD_NONE_Val _U_(0x0)
200 #define PDEC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1)
201 #define PDEC_CTRLBSET_CMD_UPDATE_Val _U_(0x2)
202 #define PDEC_CTRLBSET_CMD_READSYNC_Val _U_(0x3)
203 #define PDEC_CTRLBSET_CMD_START_Val _U_(0x4)
204 #define PDEC_CTRLBSET_CMD_STOP_Val _U_(0x5)
205 #define PDEC_CTRLBSET_CMD_NONE (PDEC_CTRLBSET_CMD_NONE_Val << PDEC_CTRLBSET_CMD_Pos)
206 #define PDEC_CTRLBSET_CMD_RETRIGGER (PDEC_CTRLBSET_CMD_RETRIGGER_Val << PDEC_CTRLBSET_CMD_Pos)
207 #define PDEC_CTRLBSET_CMD_UPDATE (PDEC_CTRLBSET_CMD_UPDATE_Val << PDEC_CTRLBSET_CMD_Pos)
208 #define PDEC_CTRLBSET_CMD_READSYNC (PDEC_CTRLBSET_CMD_READSYNC_Val << PDEC_CTRLBSET_CMD_Pos)
209 #define PDEC_CTRLBSET_CMD_START (PDEC_CTRLBSET_CMD_START_Val << PDEC_CTRLBSET_CMD_Pos)
210 #define PDEC_CTRLBSET_CMD_STOP (PDEC_CTRLBSET_CMD_STOP_Val << PDEC_CTRLBSET_CMD_Pos)
211 #define PDEC_CTRLBSET_MASK _U_(0xE2)
213 /* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */
214 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
215 typedef union {
216  struct {
217  uint16_t EVACT:2;
218  uint16_t EVINV:3;
219  uint16_t EVEI:3;
220  uint16_t OVFEO:1;
221  uint16_t ERREO:1;
222  uint16_t DIREO:1;
223  uint16_t VLCEO:1;
224  uint16_t MCEO0:1;
225  uint16_t MCEO1:1;
226  uint16_t :2;
227  } bit;
228  struct {
229  uint16_t :12;
230  uint16_t MCEO:2;
231  uint16_t :2;
232  } vec;
233  uint16_t reg;
235 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
236 
237 #define PDEC_EVCTRL_OFFSET 0x06
238 #define PDEC_EVCTRL_RESETVALUE _U_(0x0000)
240 #define PDEC_EVCTRL_EVACT_Pos 0
241 #define PDEC_EVCTRL_EVACT_Msk (_U_(0x3) << PDEC_EVCTRL_EVACT_Pos)
242 #define PDEC_EVCTRL_EVACT(value) (PDEC_EVCTRL_EVACT_Msk & ((value) << PDEC_EVCTRL_EVACT_Pos))
243 #define PDEC_EVCTRL_EVACT_OFF_Val _U_(0x0)
244 #define PDEC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1)
245 #define PDEC_EVCTRL_EVACT_COUNT_Val _U_(0x2)
246 #define PDEC_EVCTRL_EVACT_OFF (PDEC_EVCTRL_EVACT_OFF_Val << PDEC_EVCTRL_EVACT_Pos)
247 #define PDEC_EVCTRL_EVACT_RETRIGGER (PDEC_EVCTRL_EVACT_RETRIGGER_Val << PDEC_EVCTRL_EVACT_Pos)
248 #define PDEC_EVCTRL_EVACT_COUNT (PDEC_EVCTRL_EVACT_COUNT_Val << PDEC_EVCTRL_EVACT_Pos)
249 #define PDEC_EVCTRL_EVINV_Pos 2
250 #define PDEC_EVCTRL_EVINV_Msk (_U_(0x7) << PDEC_EVCTRL_EVINV_Pos)
251 #define PDEC_EVCTRL_EVINV(value) (PDEC_EVCTRL_EVINV_Msk & ((value) << PDEC_EVCTRL_EVINV_Pos))
252 #define PDEC_EVCTRL_EVEI_Pos 5
253 #define PDEC_EVCTRL_EVEI_Msk (_U_(0x7) << PDEC_EVCTRL_EVEI_Pos)
254 #define PDEC_EVCTRL_EVEI(value) (PDEC_EVCTRL_EVEI_Msk & ((value) << PDEC_EVCTRL_EVEI_Pos))
255 #define PDEC_EVCTRL_OVFEO_Pos 8
256 #define PDEC_EVCTRL_OVFEO (_U_(0x1) << PDEC_EVCTRL_OVFEO_Pos)
257 #define PDEC_EVCTRL_ERREO_Pos 9
258 #define PDEC_EVCTRL_ERREO (_U_(0x1) << PDEC_EVCTRL_ERREO_Pos)
259 #define PDEC_EVCTRL_DIREO_Pos 10
260 #define PDEC_EVCTRL_DIREO (_U_(0x1) << PDEC_EVCTRL_DIREO_Pos)
261 #define PDEC_EVCTRL_VLCEO_Pos 11
262 #define PDEC_EVCTRL_VLCEO (_U_(0x1) << PDEC_EVCTRL_VLCEO_Pos)
263 #define PDEC_EVCTRL_MCEO0_Pos 12
264 #define PDEC_EVCTRL_MCEO0 (_U_(1) << PDEC_EVCTRL_MCEO0_Pos)
265 #define PDEC_EVCTRL_MCEO1_Pos 13
266 #define PDEC_EVCTRL_MCEO1 (_U_(1) << PDEC_EVCTRL_MCEO1_Pos)
267 #define PDEC_EVCTRL_MCEO_Pos 12
268 #define PDEC_EVCTRL_MCEO_Msk (_U_(0x3) << PDEC_EVCTRL_MCEO_Pos)
269 #define PDEC_EVCTRL_MCEO(value) (PDEC_EVCTRL_MCEO_Msk & ((value) << PDEC_EVCTRL_MCEO_Pos))
270 #define PDEC_EVCTRL_MASK _U_(0x3FFF)
272 /* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
274 typedef union {
275  struct {
276  uint8_t OVF:1;
277  uint8_t ERR:1;
278  uint8_t DIR:1;
279  uint8_t VLC:1;
280  uint8_t MC0:1;
281  uint8_t MC1:1;
282  uint8_t :2;
283  } bit;
284  struct {
285  uint8_t :4;
286  uint8_t MC:2;
287  uint8_t :2;
288  } vec;
289  uint8_t reg;
291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
292 
293 #define PDEC_INTENCLR_OFFSET 0x08
294 #define PDEC_INTENCLR_RESETVALUE _U_(0x00)
296 #define PDEC_INTENCLR_OVF_Pos 0
297 #define PDEC_INTENCLR_OVF (_U_(0x1) << PDEC_INTENCLR_OVF_Pos)
298 #define PDEC_INTENCLR_ERR_Pos 1
299 #define PDEC_INTENCLR_ERR (_U_(0x1) << PDEC_INTENCLR_ERR_Pos)
300 #define PDEC_INTENCLR_DIR_Pos 2
301 #define PDEC_INTENCLR_DIR (_U_(0x1) << PDEC_INTENCLR_DIR_Pos)
302 #define PDEC_INTENCLR_VLC_Pos 3
303 #define PDEC_INTENCLR_VLC (_U_(0x1) << PDEC_INTENCLR_VLC_Pos)
304 #define PDEC_INTENCLR_MC0_Pos 4
305 #define PDEC_INTENCLR_MC0 (_U_(1) << PDEC_INTENCLR_MC0_Pos)
306 #define PDEC_INTENCLR_MC1_Pos 5
307 #define PDEC_INTENCLR_MC1 (_U_(1) << PDEC_INTENCLR_MC1_Pos)
308 #define PDEC_INTENCLR_MC_Pos 4
309 #define PDEC_INTENCLR_MC_Msk (_U_(0x3) << PDEC_INTENCLR_MC_Pos)
310 #define PDEC_INTENCLR_MC(value) (PDEC_INTENCLR_MC_Msk & ((value) << PDEC_INTENCLR_MC_Pos))
311 #define PDEC_INTENCLR_MASK _U_(0x3F)
313 /* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
314 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
315 typedef union {
316  struct {
317  uint8_t OVF:1;
318  uint8_t ERR:1;
319  uint8_t DIR:1;
320  uint8_t VLC:1;
321  uint8_t MC0:1;
322  uint8_t MC1:1;
323  uint8_t :2;
324  } bit;
325  struct {
326  uint8_t :4;
327  uint8_t MC:2;
328  uint8_t :2;
329  } vec;
330  uint8_t reg;
332 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
333 
334 #define PDEC_INTENSET_OFFSET 0x09
335 #define PDEC_INTENSET_RESETVALUE _U_(0x00)
337 #define PDEC_INTENSET_OVF_Pos 0
338 #define PDEC_INTENSET_OVF (_U_(0x1) << PDEC_INTENSET_OVF_Pos)
339 #define PDEC_INTENSET_ERR_Pos 1
340 #define PDEC_INTENSET_ERR (_U_(0x1) << PDEC_INTENSET_ERR_Pos)
341 #define PDEC_INTENSET_DIR_Pos 2
342 #define PDEC_INTENSET_DIR (_U_(0x1) << PDEC_INTENSET_DIR_Pos)
343 #define PDEC_INTENSET_VLC_Pos 3
344 #define PDEC_INTENSET_VLC (_U_(0x1) << PDEC_INTENSET_VLC_Pos)
345 #define PDEC_INTENSET_MC0_Pos 4
346 #define PDEC_INTENSET_MC0 (_U_(1) << PDEC_INTENSET_MC0_Pos)
347 #define PDEC_INTENSET_MC1_Pos 5
348 #define PDEC_INTENSET_MC1 (_U_(1) << PDEC_INTENSET_MC1_Pos)
349 #define PDEC_INTENSET_MC_Pos 4
350 #define PDEC_INTENSET_MC_Msk (_U_(0x3) << PDEC_INTENSET_MC_Pos)
351 #define PDEC_INTENSET_MC(value) (PDEC_INTENSET_MC_Msk & ((value) << PDEC_INTENSET_MC_Pos))
352 #define PDEC_INTENSET_MASK _U_(0x3F)
354 /* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
355 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
356 typedef union { // __I to avoid read-modify-write on write-to-clear register
357  struct {
358  __I uint8_t OVF:1;
359  __I uint8_t ERR:1;
360  __I uint8_t DIR:1;
361  __I uint8_t VLC:1;
362  __I uint8_t MC0:1;
363  __I uint8_t MC1:1;
364  __I uint8_t :2;
365  } bit;
366  struct {
367  __I uint8_t :4;
368  __I uint8_t MC:2;
369  __I uint8_t :2;
370  } vec;
371  uint8_t reg;
373 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
374 
375 #define PDEC_INTFLAG_OFFSET 0x0A
376 #define PDEC_INTFLAG_RESETVALUE _U_(0x00)
378 #define PDEC_INTFLAG_OVF_Pos 0
379 #define PDEC_INTFLAG_OVF (_U_(0x1) << PDEC_INTFLAG_OVF_Pos)
380 #define PDEC_INTFLAG_ERR_Pos 1
381 #define PDEC_INTFLAG_ERR (_U_(0x1) << PDEC_INTFLAG_ERR_Pos)
382 #define PDEC_INTFLAG_DIR_Pos 2
383 #define PDEC_INTFLAG_DIR (_U_(0x1) << PDEC_INTFLAG_DIR_Pos)
384 #define PDEC_INTFLAG_VLC_Pos 3
385 #define PDEC_INTFLAG_VLC (_U_(0x1) << PDEC_INTFLAG_VLC_Pos)
386 #define PDEC_INTFLAG_MC0_Pos 4
387 #define PDEC_INTFLAG_MC0 (_U_(1) << PDEC_INTFLAG_MC0_Pos)
388 #define PDEC_INTFLAG_MC1_Pos 5
389 #define PDEC_INTFLAG_MC1 (_U_(1) << PDEC_INTFLAG_MC1_Pos)
390 #define PDEC_INTFLAG_MC_Pos 4
391 #define PDEC_INTFLAG_MC_Msk (_U_(0x3) << PDEC_INTFLAG_MC_Pos)
392 #define PDEC_INTFLAG_MC(value) (PDEC_INTFLAG_MC_Msk & ((value) << PDEC_INTFLAG_MC_Pos))
393 #define PDEC_INTFLAG_MASK _U_(0x3F)
395 /* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */
396 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
397 typedef union {
398  struct {
399  uint16_t QERR:1;
400  uint16_t IDXERR:1;
401  uint16_t MPERR:1;
402  uint16_t :1;
403  uint16_t WINERR:1;
404  uint16_t HERR:1;
405  uint16_t STOP:1;
406  uint16_t DIR:1;
407  uint16_t PRESCBUFV:1;
408  uint16_t FILTERBUFV:1;
409  uint16_t :2;
410  uint16_t CCBUFV0:1;
411  uint16_t CCBUFV1:1;
412  uint16_t :2;
413  } bit;
414  struct {
415  uint16_t :12;
416  uint16_t CCBUFV:2;
417  uint16_t :2;
418  } vec;
419  uint16_t reg;
421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
422 
423 #define PDEC_STATUS_OFFSET 0x0C
424 #define PDEC_STATUS_RESETVALUE _U_(0x0040)
426 #define PDEC_STATUS_QERR_Pos 0
427 #define PDEC_STATUS_QERR (_U_(0x1) << PDEC_STATUS_QERR_Pos)
428 #define PDEC_STATUS_IDXERR_Pos 1
429 #define PDEC_STATUS_IDXERR (_U_(0x1) << PDEC_STATUS_IDXERR_Pos)
430 #define PDEC_STATUS_MPERR_Pos 2
431 #define PDEC_STATUS_MPERR (_U_(0x1) << PDEC_STATUS_MPERR_Pos)
432 #define PDEC_STATUS_WINERR_Pos 4
433 #define PDEC_STATUS_WINERR (_U_(0x1) << PDEC_STATUS_WINERR_Pos)
434 #define PDEC_STATUS_HERR_Pos 5
435 #define PDEC_STATUS_HERR (_U_(0x1) << PDEC_STATUS_HERR_Pos)
436 #define PDEC_STATUS_STOP_Pos 6
437 #define PDEC_STATUS_STOP (_U_(0x1) << PDEC_STATUS_STOP_Pos)
438 #define PDEC_STATUS_DIR_Pos 7
439 #define PDEC_STATUS_DIR (_U_(0x1) << PDEC_STATUS_DIR_Pos)
440 #define PDEC_STATUS_PRESCBUFV_Pos 8
441 #define PDEC_STATUS_PRESCBUFV (_U_(0x1) << PDEC_STATUS_PRESCBUFV_Pos)
442 #define PDEC_STATUS_FILTERBUFV_Pos 9
443 #define PDEC_STATUS_FILTERBUFV (_U_(0x1) << PDEC_STATUS_FILTERBUFV_Pos)
444 #define PDEC_STATUS_CCBUFV0_Pos 12
445 #define PDEC_STATUS_CCBUFV0 (_U_(1) << PDEC_STATUS_CCBUFV0_Pos)
446 #define PDEC_STATUS_CCBUFV1_Pos 13
447 #define PDEC_STATUS_CCBUFV1 (_U_(1) << PDEC_STATUS_CCBUFV1_Pos)
448 #define PDEC_STATUS_CCBUFV_Pos 12
449 #define PDEC_STATUS_CCBUFV_Msk (_U_(0x3) << PDEC_STATUS_CCBUFV_Pos)
450 #define PDEC_STATUS_CCBUFV(value) (PDEC_STATUS_CCBUFV_Msk & ((value) << PDEC_STATUS_CCBUFV_Pos))
451 #define PDEC_STATUS_MASK _U_(0x33F7)
453 /* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */
454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
455 typedef union {
456  struct {
457  uint8_t DBGRUN:1;
458  uint8_t :7;
459  } bit;
460  uint8_t reg;
462 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
463 
464 #define PDEC_DBGCTRL_OFFSET 0x0F
465 #define PDEC_DBGCTRL_RESETVALUE _U_(0x00)
467 #define PDEC_DBGCTRL_DBGRUN_Pos 0
468 #define PDEC_DBGCTRL_DBGRUN (_U_(0x1) << PDEC_DBGCTRL_DBGRUN_Pos)
469 #define PDEC_DBGCTRL_MASK _U_(0x01)
471 /* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) (R/ 32) Synchronization Status -------- */
472 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
473 typedef union {
474  struct {
475  uint32_t SWRST:1;
476  uint32_t ENABLE:1;
477  uint32_t CTRLB:1;
478  uint32_t STATUS:1;
479  uint32_t PRESC:1;
480  uint32_t FILTER:1;
481  uint32_t COUNT:1;
482  uint32_t CC0:1;
483  uint32_t CC1:1;
484  uint32_t :23;
485  } bit;
486  struct {
487  uint32_t :7;
488  uint32_t CC:2;
489  uint32_t :23;
490  } vec;
491  uint32_t reg;
493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
494 
495 #define PDEC_SYNCBUSY_OFFSET 0x10
496 #define PDEC_SYNCBUSY_RESETVALUE _U_(0x00000000)
498 #define PDEC_SYNCBUSY_SWRST_Pos 0
499 #define PDEC_SYNCBUSY_SWRST (_U_(0x1) << PDEC_SYNCBUSY_SWRST_Pos)
500 #define PDEC_SYNCBUSY_ENABLE_Pos 1
501 #define PDEC_SYNCBUSY_ENABLE (_U_(0x1) << PDEC_SYNCBUSY_ENABLE_Pos)
502 #define PDEC_SYNCBUSY_CTRLB_Pos 2
503 #define PDEC_SYNCBUSY_CTRLB (_U_(0x1) << PDEC_SYNCBUSY_CTRLB_Pos)
504 #define PDEC_SYNCBUSY_STATUS_Pos 3
505 #define PDEC_SYNCBUSY_STATUS (_U_(0x1) << PDEC_SYNCBUSY_STATUS_Pos)
506 #define PDEC_SYNCBUSY_PRESC_Pos 4
507 #define PDEC_SYNCBUSY_PRESC (_U_(0x1) << PDEC_SYNCBUSY_PRESC_Pos)
508 #define PDEC_SYNCBUSY_FILTER_Pos 5
509 #define PDEC_SYNCBUSY_FILTER (_U_(0x1) << PDEC_SYNCBUSY_FILTER_Pos)
510 #define PDEC_SYNCBUSY_COUNT_Pos 6
511 #define PDEC_SYNCBUSY_COUNT (_U_(0x1) << PDEC_SYNCBUSY_COUNT_Pos)
512 #define PDEC_SYNCBUSY_CC0_Pos 7
513 #define PDEC_SYNCBUSY_CC0 (_U_(1) << PDEC_SYNCBUSY_CC0_Pos)
514 #define PDEC_SYNCBUSY_CC1_Pos 8
515 #define PDEC_SYNCBUSY_CC1 (_U_(1) << PDEC_SYNCBUSY_CC1_Pos)
516 #define PDEC_SYNCBUSY_CC_Pos 7
517 #define PDEC_SYNCBUSY_CC_Msk (_U_(0x3) << PDEC_SYNCBUSY_CC_Pos)
518 #define PDEC_SYNCBUSY_CC(value) (PDEC_SYNCBUSY_CC_Msk & ((value) << PDEC_SYNCBUSY_CC_Pos))
519 #define PDEC_SYNCBUSY_MASK _U_(0x000001FF)
521 /* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */
522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
523 typedef union {
524  struct {
525  uint8_t PRESC:4;
526  uint8_t :4;
527  } bit;
528  uint8_t reg;
530 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
531 
532 #define PDEC_PRESC_OFFSET 0x14
533 #define PDEC_PRESC_RESETVALUE _U_(0x00)
535 #define PDEC_PRESC_PRESC_Pos 0
536 #define PDEC_PRESC_PRESC_Msk (_U_(0xF) << PDEC_PRESC_PRESC_Pos)
537 #define PDEC_PRESC_PRESC(value) (PDEC_PRESC_PRESC_Msk & ((value) << PDEC_PRESC_PRESC_Pos))
538 #define PDEC_PRESC_PRESC_DIV1_Val _U_(0x0)
539 #define PDEC_PRESC_PRESC_DIV2_Val _U_(0x1)
540 #define PDEC_PRESC_PRESC_DIV4_Val _U_(0x2)
541 #define PDEC_PRESC_PRESC_DIV8_Val _U_(0x3)
542 #define PDEC_PRESC_PRESC_DIV16_Val _U_(0x4)
543 #define PDEC_PRESC_PRESC_DIV32_Val _U_(0x5)
544 #define PDEC_PRESC_PRESC_DIV64_Val _U_(0x6)
545 #define PDEC_PRESC_PRESC_DIV128_Val _U_(0x7)
546 #define PDEC_PRESC_PRESC_DIV256_Val _U_(0x8)
547 #define PDEC_PRESC_PRESC_DIV512_Val _U_(0x9)
548 #define PDEC_PRESC_PRESC_DIV1024_Val _U_(0xA)
549 #define PDEC_PRESC_PRESC_DIV1 (PDEC_PRESC_PRESC_DIV1_Val << PDEC_PRESC_PRESC_Pos)
550 #define PDEC_PRESC_PRESC_DIV2 (PDEC_PRESC_PRESC_DIV2_Val << PDEC_PRESC_PRESC_Pos)
551 #define PDEC_PRESC_PRESC_DIV4 (PDEC_PRESC_PRESC_DIV4_Val << PDEC_PRESC_PRESC_Pos)
552 #define PDEC_PRESC_PRESC_DIV8 (PDEC_PRESC_PRESC_DIV8_Val << PDEC_PRESC_PRESC_Pos)
553 #define PDEC_PRESC_PRESC_DIV16 (PDEC_PRESC_PRESC_DIV16_Val << PDEC_PRESC_PRESC_Pos)
554 #define PDEC_PRESC_PRESC_DIV32 (PDEC_PRESC_PRESC_DIV32_Val << PDEC_PRESC_PRESC_Pos)
555 #define PDEC_PRESC_PRESC_DIV64 (PDEC_PRESC_PRESC_DIV64_Val << PDEC_PRESC_PRESC_Pos)
556 #define PDEC_PRESC_PRESC_DIV128 (PDEC_PRESC_PRESC_DIV128_Val << PDEC_PRESC_PRESC_Pos)
557 #define PDEC_PRESC_PRESC_DIV256 (PDEC_PRESC_PRESC_DIV256_Val << PDEC_PRESC_PRESC_Pos)
558 #define PDEC_PRESC_PRESC_DIV512 (PDEC_PRESC_PRESC_DIV512_Val << PDEC_PRESC_PRESC_Pos)
559 #define PDEC_PRESC_PRESC_DIV1024 (PDEC_PRESC_PRESC_DIV1024_Val << PDEC_PRESC_PRESC_Pos)
560 #define PDEC_PRESC_MASK _U_(0x0F)
562 /* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */
563 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
564 typedef union {
565  struct {
566  uint8_t FILTER:8;
567  } bit;
568  uint8_t reg;
570 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
571 
572 #define PDEC_FILTER_OFFSET 0x15
573 #define PDEC_FILTER_RESETVALUE _U_(0x00)
575 #define PDEC_FILTER_FILTER_Pos 0
576 #define PDEC_FILTER_FILTER_Msk (_U_(0xFF) << PDEC_FILTER_FILTER_Pos)
577 #define PDEC_FILTER_FILTER(value) (PDEC_FILTER_FILTER_Msk & ((value) << PDEC_FILTER_FILTER_Pos))
578 #define PDEC_FILTER_MASK _U_(0xFF)
580 /* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */
581 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
582 typedef union {
583  struct {
584  uint8_t PRESCBUF:4;
585  uint8_t :4;
586  } bit;
587  uint8_t reg;
589 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
590 
591 #define PDEC_PRESCBUF_OFFSET 0x18
592 #define PDEC_PRESCBUF_RESETVALUE _U_(0x00)
594 #define PDEC_PRESCBUF_PRESCBUF_Pos 0
595 #define PDEC_PRESCBUF_PRESCBUF_Msk (_U_(0xF) << PDEC_PRESCBUF_PRESCBUF_Pos)
596 #define PDEC_PRESCBUF_PRESCBUF(value) (PDEC_PRESCBUF_PRESCBUF_Msk & ((value) << PDEC_PRESCBUF_PRESCBUF_Pos))
597 #define PDEC_PRESCBUF_PRESCBUF_DIV1_Val _U_(0x0)
598 #define PDEC_PRESCBUF_PRESCBUF_DIV2_Val _U_(0x1)
599 #define PDEC_PRESCBUF_PRESCBUF_DIV4_Val _U_(0x2)
600 #define PDEC_PRESCBUF_PRESCBUF_DIV8_Val _U_(0x3)
601 #define PDEC_PRESCBUF_PRESCBUF_DIV16_Val _U_(0x4)
602 #define PDEC_PRESCBUF_PRESCBUF_DIV32_Val _U_(0x5)
603 #define PDEC_PRESCBUF_PRESCBUF_DIV64_Val _U_(0x6)
604 #define PDEC_PRESCBUF_PRESCBUF_DIV128_Val _U_(0x7)
605 #define PDEC_PRESCBUF_PRESCBUF_DIV256_Val _U_(0x8)
606 #define PDEC_PRESCBUF_PRESCBUF_DIV512_Val _U_(0x9)
607 #define PDEC_PRESCBUF_PRESCBUF_DIV1024_Val _U_(0xA)
608 #define PDEC_PRESCBUF_PRESCBUF_DIV1 (PDEC_PRESCBUF_PRESCBUF_DIV1_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
609 #define PDEC_PRESCBUF_PRESCBUF_DIV2 (PDEC_PRESCBUF_PRESCBUF_DIV2_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
610 #define PDEC_PRESCBUF_PRESCBUF_DIV4 (PDEC_PRESCBUF_PRESCBUF_DIV4_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
611 #define PDEC_PRESCBUF_PRESCBUF_DIV8 (PDEC_PRESCBUF_PRESCBUF_DIV8_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
612 #define PDEC_PRESCBUF_PRESCBUF_DIV16 (PDEC_PRESCBUF_PRESCBUF_DIV16_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
613 #define PDEC_PRESCBUF_PRESCBUF_DIV32 (PDEC_PRESCBUF_PRESCBUF_DIV32_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
614 #define PDEC_PRESCBUF_PRESCBUF_DIV64 (PDEC_PRESCBUF_PRESCBUF_DIV64_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
615 #define PDEC_PRESCBUF_PRESCBUF_DIV128 (PDEC_PRESCBUF_PRESCBUF_DIV128_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
616 #define PDEC_PRESCBUF_PRESCBUF_DIV256 (PDEC_PRESCBUF_PRESCBUF_DIV256_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
617 #define PDEC_PRESCBUF_PRESCBUF_DIV512 (PDEC_PRESCBUF_PRESCBUF_DIV512_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
618 #define PDEC_PRESCBUF_PRESCBUF_DIV1024 (PDEC_PRESCBUF_PRESCBUF_DIV1024_Val << PDEC_PRESCBUF_PRESCBUF_Pos)
619 #define PDEC_PRESCBUF_MASK _U_(0x0F)
621 /* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */
622 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
623 typedef union {
624  struct {
625  uint8_t FILTERBUF:8;
626  } bit;
627  uint8_t reg;
629 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
630 
631 #define PDEC_FILTERBUF_OFFSET 0x19
632 #define PDEC_FILTERBUF_RESETVALUE _U_(0x00)
634 #define PDEC_FILTERBUF_FILTERBUF_Pos 0
635 #define PDEC_FILTERBUF_FILTERBUF_Msk (_U_(0xFF) << PDEC_FILTERBUF_FILTERBUF_Pos)
636 #define PDEC_FILTERBUF_FILTERBUF(value) (PDEC_FILTERBUF_FILTERBUF_Msk & ((value) << PDEC_FILTERBUF_FILTERBUF_Pos))
637 #define PDEC_FILTERBUF_MASK _U_(0xFF)
639 /* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */
640 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
641 typedef union {
642  struct {
643  uint32_t COUNT:16;
644  uint32_t :16;
645  } bit;
646  uint32_t reg;
648 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
649 
650 #define PDEC_COUNT_OFFSET 0x1C
651 #define PDEC_COUNT_RESETVALUE _U_(0x00000000)
653 #define PDEC_COUNT_COUNT_Pos 0
654 #define PDEC_COUNT_COUNT_Msk (_U_(0xFFFF) << PDEC_COUNT_COUNT_Pos)
655 #define PDEC_COUNT_COUNT(value) (PDEC_COUNT_COUNT_Msk & ((value) << PDEC_COUNT_COUNT_Pos))
656 #define PDEC_COUNT_MASK _U_(0x0000FFFF)
658 /* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */
659 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
660 typedef union {
661  struct {
662  uint32_t CC:16;
663  uint32_t :16;
664  } bit;
665  uint32_t reg;
666 } PDEC_CC_Type;
667 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
668 
669 #define PDEC_CC_OFFSET 0x20
670 #define PDEC_CC_RESETVALUE _U_(0x00000000)
672 #define PDEC_CC_CC_Pos 0
673 #define PDEC_CC_CC_Msk (_U_(0xFFFF) << PDEC_CC_CC_Pos)
674 #define PDEC_CC_CC(value) (PDEC_CC_CC_Msk & ((value) << PDEC_CC_CC_Pos))
675 #define PDEC_CC_MASK _U_(0x0000FFFF)
677 /* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */
678 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
679 typedef union {
680  struct {
681  uint32_t CCBUF:16;
682  uint32_t :16;
683  } bit;
684  uint32_t reg;
686 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
687 
688 #define PDEC_CCBUF_OFFSET 0x30
689 #define PDEC_CCBUF_RESETVALUE _U_(0x00000000)
691 #define PDEC_CCBUF_CCBUF_Pos 0
692 #define PDEC_CCBUF_CCBUF_Msk (_U_(0xFFFF) << PDEC_CCBUF_CCBUF_Pos)
693 #define PDEC_CCBUF_CCBUF(value) (PDEC_CCBUF_CCBUF_Msk & ((value) << PDEC_CCBUF_CCBUF_Pos))
694 #define PDEC_CCBUF_MASK _U_(0x0000FFFF)
697 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
698 typedef struct {
706  RoReg8 Reserved1[0x1];
708  RoReg8 Reserved2[0x1];
713  RoReg8 Reserved3[0x2];
716  RoReg8 Reserved4[0x2];
718  __IO PDEC_CC_Type CC[2];
719  RoReg8 Reserved5[0x8];
720  __IO PDEC_CCBUF_Type CCBUF[2];
721 } Pdec;
722 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
723 
726 #endif /* _SAME54_PDEC_COMPONENT_ */
PDEC_EVCTRL_Type::MCEO
uint16_t MCEO
Definition: pdec.h:230
PDEC_INTENSET_Type::ERR
uint8_t ERR
Definition: pdec.h:318
PDEC_INTFLAG_Type
Definition: pdec.h:356
PDEC_FILTER_Type::reg
uint8_t reg
Definition: pdec.h:568
PDEC_PRESC_Type::PRESC
uint8_t PRESC
Definition: pdec.h:525
PDEC_INTENCLR_Type::MC1
uint8_t MC1
Definition: pdec.h:281
PDEC_DBGCTRL_Type::reg
uint8_t reg
Definition: pdec.h:460
PDEC_CTRLBSET_Type
Definition: pdec.h:180
PDEC_CTRLA_Type::ALOCK
uint32_t ALOCK
Definition: pdec.h:53
PDEC_INTENSET_Type::DIR
uint8_t DIR
Definition: pdec.h:319
PDEC_STATUS_Type::reg
uint16_t reg
Definition: pdec.h:419
PDEC_STATUS_Type::IDXERR
uint16_t IDXERR
Definition: pdec.h:400
PDEC_STATUS_Type::DIR
uint16_t DIR
Definition: pdec.h:406
PDEC_STATUS_Type::CCBUFV1
uint16_t CCBUFV1
Definition: pdec.h:411
PDEC_STATUS_Type::FILTERBUFV
uint16_t FILTERBUFV
Definition: pdec.h:408
PDEC_INTENCLR_Type::reg
uint8_t reg
Definition: pdec.h:289
PDEC_PRESCBUF_Type::PRESCBUF
uint8_t PRESCBUF
Definition: pdec.h:584
PDEC_SYNCBUSY_Type::CC1
uint32_t CC1
Definition: pdec.h:483
Pdec::INTENCLR
__IO PDEC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear.
Definition: pdec.h:703
Pdec::FILTERBUF
__IO PDEC_FILTERBUF_Type FILTERBUF
Offset: 0x19 (R/W 8) Filter Buffer Value.
Definition: pdec.h:715
PDEC_SYNCBUSY_Type::CC
uint32_t CC
Definition: pdec.h:488
Pdec
PDEC hardware registers.
Definition: pdec.h:698
PDEC_EVCTRL_Type::ERREO
uint16_t ERREO
Definition: pdec.h:221
PDEC_CTRLA_Type::PINEN2
uint32_t PINEN2
Definition: pdec.h:59
PDEC_INTENCLR_Type::MC
uint8_t MC
Definition: pdec.h:286
PDEC_DBGCTRL_Type
Definition: pdec.h:455
Pdec::FILTER
__IO PDEC_FILTER_Type FILTER
Offset: 0x15 (R/W 8) Filter Value.
Definition: pdec.h:712
PDEC_FILTERBUF_Type::reg
uint8_t reg
Definition: pdec.h:627
PDEC_CTRLA_Type::MAXCMP
uint32_t MAXCMP
Definition: pdec.h:67
PDEC_STATUS_Type::CCBUFV
uint16_t CCBUFV
Definition: pdec.h:416
PDEC_STATUS_Type::CCBUFV0
uint16_t CCBUFV0
Definition: pdec.h:410
PDEC_CTRLA_Type::PINVEN0
uint32_t PINVEN0
Definition: pdec.h:61
Pdec::PRESC
__IO PDEC_PRESC_Type PRESC
Offset: 0x14 (R/W 8) Prescaler Value.
Definition: pdec.h:711
PDEC_STATUS_Type::MPERR
uint16_t MPERR
Definition: pdec.h:401
PDEC_CTRLA_Type::PINVEN1
uint32_t PINVEN1
Definition: pdec.h:62
PDEC_INTFLAG_Type::MC
__I uint8_t MC
Definition: pdec.h:368
PDEC_CTRLA_Type
Definition: pdec.h:44
Pdec::EVCTRL
__IO PDEC_EVCTRL_Type EVCTRL
Offset: 0x06 (R/W 16) Event Control.
Definition: pdec.h:702
PDEC_INTFLAG_Type::reg
uint8_t reg
Definition: pdec.h:371
PDEC_INTENCLR_Type::VLC
uint8_t VLC
Definition: pdec.h:279
PDEC_INTFLAG_Type::ERR
__I uint8_t ERR
Definition: pdec.h:359
PDEC_CTRLA_Type::PINVEN2
uint32_t PINVEN2
Definition: pdec.h:63
PDEC_CTRLBCLR_Type::LUPD
uint8_t LUPD
Definition: pdec.h:148
PDEC_CTRLBSET_Type::reg
uint8_t reg
Definition: pdec.h:187
PDEC_FILTER_Type::FILTER
uint8_t FILTER
Definition: pdec.h:566
PDEC_PRESCBUF_Type
Definition: pdec.h:582
PDEC_INTENSET_Type::MC
uint8_t MC
Definition: pdec.h:327
PDEC_SYNCBUSY_Type::COUNT
uint32_t COUNT
Definition: pdec.h:481
PDEC_STATUS_Type
Definition: pdec.h:397
PDEC_EVCTRL_Type::reg
uint16_t reg
Definition: pdec.h:233
PDEC_INTENCLR_Type::ERR
uint8_t ERR
Definition: pdec.h:277
PDEC_SYNCBUSY_Type::PRESC
uint32_t PRESC
Definition: pdec.h:479
PDEC_FILTER_Type
Definition: pdec.h:564
PDEC_CTRLA_Type::SWAP
uint32_t SWAP
Definition: pdec.h:55
Pdec::INTENSET
__IO PDEC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set.
Definition: pdec.h:704
PDEC_FILTERBUF_Type
Definition: pdec.h:623
PDEC_PRESC_Type
Definition: pdec.h:523
PDEC_STATUS_Type::STOP
uint16_t STOP
Definition: pdec.h:405
Pdec::CTRLBCLR
__IO PDEC_CTRLBCLR_Type CTRLBCLR
Offset: 0x04 (R/W 8) Control B Clear.
Definition: pdec.h:700
PDEC_DBGCTRL_Type::DBGRUN
uint8_t DBGRUN
Definition: pdec.h:457
PDEC_SYNCBUSY_Type::FILTER
uint32_t FILTER
Definition: pdec.h:480
PDEC_PRESC_Type::reg
uint8_t reg
Definition: pdec.h:528
PDEC_INTENSET_Type::OVF
uint8_t OVF
Definition: pdec.h:317
PDEC_CTRLA_Type::SWRST
uint32_t SWRST
Definition: pdec.h:46
PDEC_PRESCBUF_Type::reg
uint8_t reg
Definition: pdec.h:587
Pdec::COUNT
__IO PDEC_COUNT_Type COUNT
Offset: 0x1C (R/W 32) Counter Value.
Definition: pdec.h:717
Pdec::SYNCBUSY
__I PDEC_SYNCBUSY_Type SYNCBUSY
Offset: 0x10 (R/ 32) Synchronization Status.
Definition: pdec.h:710
PDEC_COUNT_Type
Definition: pdec.h:641
PDEC_INTENCLR_Type
Definition: pdec.h:274
PDEC_CTRLA_Type::PINEN0
uint32_t PINEN0
Definition: pdec.h:57
PDEC_SYNCBUSY_Type::SWRST
uint32_t SWRST
Definition: pdec.h:475
PDEC_CTRLA_Type::PINEN
uint32_t PINEN
Definition: pdec.h:71
PDEC_STATUS_Type::WINERR
uint16_t WINERR
Definition: pdec.h:403
PDEC_INTENCLR_Type::OVF
uint8_t OVF
Definition: pdec.h:276
PDEC_CTRLBSET_Type::CMD
uint8_t CMD
Definition: pdec.h:185
PDEC_CTRLA_Type::PINVEN
uint32_t PINVEN
Definition: pdec.h:73
PDEC_EVCTRL_Type
Definition: pdec.h:215
Pdec::CTRLBSET
__IO PDEC_CTRLBSET_Type CTRLBSET
Offset: 0x05 (R/W 8) Control B Set.
Definition: pdec.h:701
Pdec::PRESCBUF
__IO PDEC_PRESCBUF_Type PRESCBUF
Offset: 0x18 (R/W 8) Prescaler Buffer Value.
Definition: pdec.h:714
PDEC_INTENSET_Type::VLC
uint8_t VLC
Definition: pdec.h:320
PDEC_CTRLA_Type::PEREN
uint32_t PEREN
Definition: pdec.h:56
PDEC_INTFLAG_Type::DIR
__I uint8_t DIR
Definition: pdec.h:360
PDEC_CTRLBCLR_Type::reg
uint8_t reg
Definition: pdec.h:152
PDEC_CTRLBSET_Type::LUPD
uint8_t LUPD
Definition: pdec.h:183
PDEC_SYNCBUSY_Type::STATUS
uint32_t STATUS
Definition: pdec.h:478
PDEC_STATUS_Type::QERR
uint16_t QERR
Definition: pdec.h:399
PDEC_SYNCBUSY_Type
Definition: pdec.h:473
PDEC_SYNCBUSY_Type::CC0
uint32_t CC0
Definition: pdec.h:482
PDEC_SYNCBUSY_Type::ENABLE
uint32_t ENABLE
Definition: pdec.h:476
PDEC_INTENCLR_Type::MC0
uint8_t MC0
Definition: pdec.h:280
PDEC_CTRLA_Type::MODE
uint32_t MODE
Definition: pdec.h:48
PDEC_INTENSET_Type::MC1
uint8_t MC1
Definition: pdec.h:322
PDEC_EVCTRL_Type::EVEI
uint16_t EVEI
Definition: pdec.h:219
PDEC_EVCTRL_Type::OVFEO
uint16_t OVFEO
Definition: pdec.h:220
PDEC_INTENCLR_Type::DIR
uint8_t DIR
Definition: pdec.h:278
PDEC_CTRLBCLR_Type::CMD
uint8_t CMD
Definition: pdec.h:150
Pdec::STATUS
__IO PDEC_STATUS_Type STATUS
Offset: 0x0C (R/W 16) Status.
Definition: pdec.h:707
PDEC_FILTERBUF_Type::FILTERBUF
uint8_t FILTERBUF
Definition: pdec.h:625
PDEC_SYNCBUSY_Type::reg
uint32_t reg
Definition: pdec.h:491
PDEC_CCBUF_Type::CCBUF
uint32_t CCBUF
Definition: pdec.h:681
PDEC_COUNT_Type::COUNT
uint32_t COUNT
Definition: pdec.h:643
PDEC_CTRLA_Type::RUNSTDBY
uint32_t RUNSTDBY
Definition: pdec.h:50
PDEC_CTRLA_Type::ANGULAR
uint32_t ANGULAR
Definition: pdec.h:65
PDEC_EVCTRL_Type::EVINV
uint16_t EVINV
Definition: pdec.h:218
PDEC_EVCTRL_Type::MCEO1
uint16_t MCEO1
Definition: pdec.h:225
PDEC_INTFLAG_Type::VLC
__I uint8_t VLC
Definition: pdec.h:361
PDEC_CTRLA_Type::reg
uint32_t reg
Definition: pdec.h:76
PDEC_EVCTRL_Type::DIREO
uint16_t DIREO
Definition: pdec.h:222
PDEC_INTFLAG_Type::uint8_t
__I uint8_t
Definition: pdec.h:364
PDEC_INTFLAG_Type::MC0
__I uint8_t MC0
Definition: pdec.h:362
PDEC_SYNCBUSY_Type::CTRLB
uint32_t CTRLB
Definition: pdec.h:477
PDEC_CCBUF_Type
Definition: pdec.h:679
PDEC_CTRLA_Type::CONF
uint32_t CONF
Definition: pdec.h:52
PDEC_EVCTRL_Type::MCEO0
uint16_t MCEO0
Definition: pdec.h:224
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
PDEC_INTENSET_Type
Definition: pdec.h:315
PDEC_CTRLBCLR_Type
Definition: pdec.h:145
PDEC_INTENSET_Type::MC0
uint8_t MC0
Definition: pdec.h:321
PDEC_EVCTRL_Type::VLCEO
uint16_t VLCEO
Definition: pdec.h:223
PDEC_CTRLA_Type::ENABLE
uint32_t ENABLE
Definition: pdec.h:47
Pdec::CTRLA
__IO PDEC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
Definition: pdec.h:699
PDEC_INTENSET_Type::reg
uint8_t reg
Definition: pdec.h:330
PDEC_CC_Type::reg
uint32_t reg
Definition: pdec.h:665
Pdec::DBGCTRL
__IO PDEC_DBGCTRL_Type DBGCTRL
Offset: 0x0F (R/W 8) Debug Control.
Definition: pdec.h:709
PDEC_STATUS_Type::PRESCBUFV
uint16_t PRESCBUFV
Definition: pdec.h:407
Pdec::INTFLAG
__IO PDEC_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear.
Definition: pdec.h:705
PDEC_CCBUF_Type::reg
uint32_t reg
Definition: pdec.h:684
PDEC_CC_Type
Definition: pdec.h:660
PDEC_INTFLAG_Type::OVF
__I uint8_t OVF
Definition: pdec.h:358
PDEC_STATUS_Type::HERR
uint16_t HERR
Definition: pdec.h:404
PDEC_CTRLA_Type::PINEN1
uint32_t PINEN1
Definition: pdec.h:58
PDEC_INTFLAG_Type::MC1
__I uint8_t MC1
Definition: pdec.h:363
PDEC_CC_Type::CC
uint32_t CC
Definition: pdec.h:662
PDEC_EVCTRL_Type::EVACT
uint16_t EVACT
Definition: pdec.h:217
PDEC_COUNT_Type::reg
uint32_t reg
Definition: pdec.h:646