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30 #ifndef _SAME54_MCLK_COMPONENT_
31 #define _SAME54_MCLK_COMPONENT_
40 #define REV_MCLK 0x100
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
53 #define MCLK_INTENCLR_OFFSET 0x01
54 #define MCLK_INTENCLR_RESETVALUE _U_(0x00)
56 #define MCLK_INTENCLR_CKRDY_Pos 0
57 #define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
58 #define MCLK_INTENCLR_MASK _U_(0x01)
61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
71 #define MCLK_INTENSET_OFFSET 0x02
72 #define MCLK_INTENSET_RESETVALUE _U_(0x00)
74 #define MCLK_INTENSET_CKRDY_Pos 0
75 #define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
76 #define MCLK_INTENSET_MASK _U_(0x01)
79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
89 #define MCLK_INTFLAG_OFFSET 0x03
90 #define MCLK_INTFLAG_RESETVALUE _U_(0x01)
92 #define MCLK_INTFLAG_CKRDY_Pos 0
93 #define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
94 #define MCLK_INTFLAG_MASK _U_(0x01)
97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
106 #define MCLK_HSDIV_OFFSET 0x04
107 #define MCLK_HSDIV_RESETVALUE _U_(0x01)
109 #define MCLK_HSDIV_DIV_Pos 0
110 #define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
111 #define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
112 #define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1)
113 #define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)
114 #define MCLK_HSDIV_MASK _U_(0xFF)
117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
126 #define MCLK_CPUDIV_OFFSET 0x05
127 #define MCLK_CPUDIV_RESETVALUE _U_(0x01)
129 #define MCLK_CPUDIV_DIV_Pos 0
130 #define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
131 #define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
132 #define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1)
133 #define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2)
134 #define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4)
135 #define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8)
136 #define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10)
137 #define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20)
138 #define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40)
139 #define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80)
140 #define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)
141 #define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)
142 #define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)
143 #define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)
144 #define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)
145 #define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)
146 #define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)
147 #define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)
148 #define MCLK_CPUDIV_MASK _U_(0xFF)
151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
184 #define MCLK_AHBMASK_OFFSET 0x10
185 #define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF)
187 #define MCLK_AHBMASK_HPB0_Pos 0
188 #define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
189 #define MCLK_AHBMASK_HPB1_Pos 1
190 #define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
191 #define MCLK_AHBMASK_HPB2_Pos 2
192 #define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
193 #define MCLK_AHBMASK_HPB3_Pos 3
194 #define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
195 #define MCLK_AHBMASK_DSU_Pos 4
196 #define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
197 #define MCLK_AHBMASK_HMATRIX_Pos 5
198 #define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
199 #define MCLK_AHBMASK_NVMCTRL_Pos 6
200 #define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
201 #define MCLK_AHBMASK_HSRAM_Pos 7
202 #define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
203 #define MCLK_AHBMASK_CMCC_Pos 8
204 #define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
205 #define MCLK_AHBMASK_DMAC_Pos 9
206 #define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
207 #define MCLK_AHBMASK_USB_Pos 10
208 #define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
209 #define MCLK_AHBMASK_BKUPRAM_Pos 11
210 #define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
211 #define MCLK_AHBMASK_PAC_Pos 12
212 #define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
213 #define MCLK_AHBMASK_QSPI_Pos 13
214 #define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
215 #define MCLK_AHBMASK_GMAC_Pos 14
216 #define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
217 #define MCLK_AHBMASK_SDHC0_Pos 15
218 #define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
219 #define MCLK_AHBMASK_SDHC1_Pos 16
220 #define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
221 #define MCLK_AHBMASK_CAN0_Pos 17
222 #define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
223 #define MCLK_AHBMASK_CAN1_Pos 18
224 #define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
225 #define MCLK_AHBMASK_ICM_Pos 19
226 #define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
227 #define MCLK_AHBMASK_PUKCC_Pos 20
228 #define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
229 #define MCLK_AHBMASK_QSPI_2X_Pos 21
230 #define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
231 #define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22
232 #define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
233 #define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23
234 #define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
235 #define MCLK_AHBMASK_MASK _U_(0x00FFFFFF)
238 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
263 #define MCLK_APBAMASK_OFFSET 0x14
264 #define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF)
266 #define MCLK_APBAMASK_PAC_Pos 0
267 #define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
268 #define MCLK_APBAMASK_PM_Pos 1
269 #define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
270 #define MCLK_APBAMASK_MCLK_Pos 2
271 #define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
272 #define MCLK_APBAMASK_RSTC_Pos 3
273 #define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
274 #define MCLK_APBAMASK_OSCCTRL_Pos 4
275 #define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
276 #define MCLK_APBAMASK_OSC32KCTRL_Pos 5
277 #define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
278 #define MCLK_APBAMASK_SUPC_Pos 6
279 #define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
280 #define MCLK_APBAMASK_GCLK_Pos 7
281 #define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
282 #define MCLK_APBAMASK_WDT_Pos 8
283 #define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
284 #define MCLK_APBAMASK_RTC_Pos 9
285 #define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
286 #define MCLK_APBAMASK_EIC_Pos 10
287 #define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
288 #define MCLK_APBAMASK_FREQM_Pos 11
289 #define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
290 #define MCLK_APBAMASK_SERCOM0_Pos 12
291 #define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
292 #define MCLK_APBAMASK_SERCOM1_Pos 13
293 #define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
294 #define MCLK_APBAMASK_TC0_Pos 14
295 #define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
296 #define MCLK_APBAMASK_TC1_Pos 15
297 #define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
298 #define MCLK_APBAMASK_MASK _U_(0x0000FFFF)
301 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
327 #define MCLK_APBBMASK_OFFSET 0x18
328 #define MCLK_APBBMASK_RESETVALUE _U_(0x00018056)
330 #define MCLK_APBBMASK_USB_Pos 0
331 #define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
332 #define MCLK_APBBMASK_DSU_Pos 1
333 #define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
334 #define MCLK_APBBMASK_NVMCTRL_Pos 2
335 #define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
336 #define MCLK_APBBMASK_PORT_Pos 4
337 #define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
338 #define MCLK_APBBMASK_HMATRIX_Pos 6
339 #define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
340 #define MCLK_APBBMASK_EVSYS_Pos 7
341 #define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
342 #define MCLK_APBBMASK_SERCOM2_Pos 9
343 #define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
344 #define MCLK_APBBMASK_SERCOM3_Pos 10
345 #define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
346 #define MCLK_APBBMASK_TCC0_Pos 11
347 #define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
348 #define MCLK_APBBMASK_TCC1_Pos 12
349 #define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
350 #define MCLK_APBBMASK_TC2_Pos 13
351 #define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
352 #define MCLK_APBBMASK_TC3_Pos 14
353 #define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
354 #define MCLK_APBBMASK_RAMECC_Pos 16
355 #define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
356 #define MCLK_APBBMASK_MASK _U_(0x00017ED7)
359 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
382 #define MCLK_APBCMASK_OFFSET 0x1C
383 #define MCLK_APBCMASK_RESETVALUE _U_(0x00002000)
385 #define MCLK_APBCMASK_GMAC_Pos 2
386 #define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
387 #define MCLK_APBCMASK_TCC2_Pos 3
388 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
389 #define MCLK_APBCMASK_TCC3_Pos 4
390 #define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
391 #define MCLK_APBCMASK_TC4_Pos 5
392 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
393 #define MCLK_APBCMASK_TC5_Pos 6
394 #define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
395 #define MCLK_APBCMASK_PDEC_Pos 7
396 #define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
397 #define MCLK_APBCMASK_AC_Pos 8
398 #define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
399 #define MCLK_APBCMASK_AES_Pos 9
400 #define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
401 #define MCLK_APBCMASK_TRNG_Pos 10
402 #define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
403 #define MCLK_APBCMASK_ICM_Pos 11
404 #define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
405 #define MCLK_APBCMASK_QSPI_Pos 13
406 #define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
407 #define MCLK_APBCMASK_CCL_Pos 14
408 #define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
409 #define MCLK_APBCMASK_MASK _U_(0x00006FFC)
412 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
433 #define MCLK_APBDMASK_OFFSET 0x20
434 #define MCLK_APBDMASK_RESETVALUE _U_(0x00000000)
436 #define MCLK_APBDMASK_SERCOM4_Pos 0
437 #define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
438 #define MCLK_APBDMASK_SERCOM5_Pos 1
439 #define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
440 #define MCLK_APBDMASK_SERCOM6_Pos 2
441 #define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
442 #define MCLK_APBDMASK_SERCOM7_Pos 3
443 #define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
444 #define MCLK_APBDMASK_TCC4_Pos 4
445 #define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
446 #define MCLK_APBDMASK_TC6_Pos 5
447 #define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
448 #define MCLK_APBDMASK_TC7_Pos 6
449 #define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
450 #define MCLK_APBDMASK_ADC0_Pos 7
451 #define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
452 #define MCLK_APBDMASK_ADC1_Pos 8
453 #define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
454 #define MCLK_APBDMASK_DAC_Pos 9
455 #define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
456 #define MCLK_APBDMASK_I2S_Pos 10
457 #define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
458 #define MCLK_APBDMASK_PCC_Pos 11
459 #define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
460 #define MCLK_APBDMASK_MASK _U_(0x00000FFF)
463 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO MCLK_APBCMASK_Type APBCMASK
Offset: 0x1C (R/W 32) APBC Mask.
__I MCLK_HSDIV_Type HSDIV
Offset: 0x04 (R/ 8) HS Clock Division.
__IO MCLK_INTENSET_Type INTENSET
Offset: 0x02 (R/W 8) Interrupt Enable Set.
__IO MCLK_APBBMASK_Type APBBMASK
Offset: 0x18 (R/W 32) APBB Mask.
__IO MCLK_INTENCLR_Type INTENCLR
Offset: 0x01 (R/W 8) Interrupt Enable Clear.
__IO MCLK_APBDMASK_Type APBDMASK
Offset: 0x20 (R/W 32) APBD Mask.
__IO MCLK_AHBMASK_Type AHBMASK
Offset: 0x10 (R/W 32) AHB Mask.
__IO MCLK_INTFLAG_Type INTFLAG
Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear.
__IO MCLK_CPUDIV_Type CPUDIV
Offset: 0x05 (R/W 8) CPU Clock Division.
__IO MCLK_APBAMASK_Type APBAMASK
Offset: 0x14 (R/W 32) APBA Mask.
volatile const uint8_t RoReg8
uint32_t NVMCTRL_SMEEPROM_