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30 #ifndef _SAME54_PAC_COMPONENT_
31 #define _SAME54_PAC_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
54 #define PAC_WRCTRL_OFFSET 0x00
55 #define PAC_WRCTRL_RESETVALUE _U_(0x00000000)
57 #define PAC_WRCTRL_PERID_Pos 0
58 #define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
59 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
60 #define PAC_WRCTRL_KEY_Pos 16
61 #define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
62 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
63 #define PAC_WRCTRL_KEY_OFF_Val _U_(0x0)
64 #define PAC_WRCTRL_KEY_CLR_Val _U_(0x1)
65 #define PAC_WRCTRL_KEY_SET_Val _U_(0x2)
66 #define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3)
67 #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)
68 #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)
69 #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)
70 #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)
71 #define PAC_WRCTRL_MASK _U_(0x00FFFFFF)
74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
84 #define PAC_EVCTRL_OFFSET 0x04
85 #define PAC_EVCTRL_RESETVALUE _U_(0x00)
87 #define PAC_EVCTRL_ERREO_Pos 0
88 #define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
89 #define PAC_EVCTRL_MASK _U_(0x01)
92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
102 #define PAC_INTENCLR_OFFSET 0x08
103 #define PAC_INTENCLR_RESETVALUE _U_(0x00)
105 #define PAC_INTENCLR_ERR_Pos 0
106 #define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
107 #define PAC_INTENCLR_MASK _U_(0x01)
110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
120 #define PAC_INTENSET_OFFSET 0x09
121 #define PAC_INTENSET_RESETVALUE _U_(0x00)
123 #define PAC_INTENSET_ERR_Pos 0
124 #define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos)
125 #define PAC_INTENSET_MASK _U_(0x01)
128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
153 #define PAC_INTFLAGAHB_OFFSET 0x10
154 #define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000)
156 #define PAC_INTFLAGAHB_FLASH_Pos 0
157 #define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
158 #define PAC_INTFLAGAHB_FLASH_ALT_Pos 1
159 #define PAC_INTFLAGAHB_FLASH_ALT (_U_(0x1) << PAC_INTFLAGAHB_FLASH_ALT_Pos)
160 #define PAC_INTFLAGAHB_SEEPROM_Pos 2
161 #define PAC_INTFLAGAHB_SEEPROM (_U_(0x1) << PAC_INTFLAGAHB_SEEPROM_Pos)
162 #define PAC_INTFLAGAHB_RAMCM4S_Pos 3
163 #define PAC_INTFLAGAHB_RAMCM4S (_U_(0x1) << PAC_INTFLAGAHB_RAMCM4S_Pos)
164 #define PAC_INTFLAGAHB_RAMPPPDSU_Pos 4
165 #define PAC_INTFLAGAHB_RAMPPPDSU (_U_(0x1) << PAC_INTFLAGAHB_RAMPPPDSU_Pos)
166 #define PAC_INTFLAGAHB_RAMDMAWR_Pos 5
167 #define PAC_INTFLAGAHB_RAMDMAWR (_U_(0x1) << PAC_INTFLAGAHB_RAMDMAWR_Pos)
168 #define PAC_INTFLAGAHB_RAMDMACICM_Pos 6
169 #define PAC_INTFLAGAHB_RAMDMACICM (_U_(0x1) << PAC_INTFLAGAHB_RAMDMACICM_Pos)
170 #define PAC_INTFLAGAHB_HPB0_Pos 7
171 #define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
172 #define PAC_INTFLAGAHB_HPB1_Pos 8
173 #define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
174 #define PAC_INTFLAGAHB_HPB2_Pos 9
175 #define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
176 #define PAC_INTFLAGAHB_HPB3_Pos 10
177 #define PAC_INTFLAGAHB_HPB3 (_U_(0x1) << PAC_INTFLAGAHB_HPB3_Pos)
178 #define PAC_INTFLAGAHB_PUKCC_Pos 11
179 #define PAC_INTFLAGAHB_PUKCC (_U_(0x1) << PAC_INTFLAGAHB_PUKCC_Pos)
180 #define PAC_INTFLAGAHB_SDHC0_Pos 12
181 #define PAC_INTFLAGAHB_SDHC0 (_U_(0x1) << PAC_INTFLAGAHB_SDHC0_Pos)
182 #define PAC_INTFLAGAHB_SDHC1_Pos 13
183 #define PAC_INTFLAGAHB_SDHC1 (_U_(0x1) << PAC_INTFLAGAHB_SDHC1_Pos)
184 #define PAC_INTFLAGAHB_QSPI_Pos 14
185 #define PAC_INTFLAGAHB_QSPI (_U_(0x1) << PAC_INTFLAGAHB_QSPI_Pos)
186 #define PAC_INTFLAGAHB_BKUPRAM_Pos 15
187 #define PAC_INTFLAGAHB_BKUPRAM (_U_(0x1) << PAC_INTFLAGAHB_BKUPRAM_Pos)
188 #define PAC_INTFLAGAHB_MASK _U_(0x0000FFFF)
191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
216 #define PAC_INTFLAGA_OFFSET 0x14
217 #define PAC_INTFLAGA_RESETVALUE _U_(0x00000000)
219 #define PAC_INTFLAGA_PAC_Pos 0
220 #define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
221 #define PAC_INTFLAGA_PM_Pos 1
222 #define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
223 #define PAC_INTFLAGA_MCLK_Pos 2
224 #define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
225 #define PAC_INTFLAGA_RSTC_Pos 3
226 #define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
227 #define PAC_INTFLAGA_OSCCTRL_Pos 4
228 #define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
229 #define PAC_INTFLAGA_OSC32KCTRL_Pos 5
230 #define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
231 #define PAC_INTFLAGA_SUPC_Pos 6
232 #define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
233 #define PAC_INTFLAGA_GCLK_Pos 7
234 #define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
235 #define PAC_INTFLAGA_WDT_Pos 8
236 #define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
237 #define PAC_INTFLAGA_RTC_Pos 9
238 #define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
239 #define PAC_INTFLAGA_EIC_Pos 10
240 #define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
241 #define PAC_INTFLAGA_FREQM_Pos 11
242 #define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
243 #define PAC_INTFLAGA_SERCOM0_Pos 12
244 #define PAC_INTFLAGA_SERCOM0 (_U_(0x1) << PAC_INTFLAGA_SERCOM0_Pos)
245 #define PAC_INTFLAGA_SERCOM1_Pos 13
246 #define PAC_INTFLAGA_SERCOM1 (_U_(0x1) << PAC_INTFLAGA_SERCOM1_Pos)
247 #define PAC_INTFLAGA_TC0_Pos 14
248 #define PAC_INTFLAGA_TC0 (_U_(0x1) << PAC_INTFLAGA_TC0_Pos)
249 #define PAC_INTFLAGA_TC1_Pos 15
250 #define PAC_INTFLAGA_TC1 (_U_(0x1) << PAC_INTFLAGA_TC1_Pos)
251 #define PAC_INTFLAGA_MASK _U_(0x0000FFFF)
254 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
280 #define PAC_INTFLAGB_OFFSET 0x18
281 #define PAC_INTFLAGB_RESETVALUE _U_(0x00000000)
283 #define PAC_INTFLAGB_USB_Pos 0
284 #define PAC_INTFLAGB_USB (_U_(0x1) << PAC_INTFLAGB_USB_Pos)
285 #define PAC_INTFLAGB_DSU_Pos 1
286 #define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
287 #define PAC_INTFLAGB_NVMCTRL_Pos 2
288 #define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
289 #define PAC_INTFLAGB_CMCC_Pos 3
290 #define PAC_INTFLAGB_CMCC (_U_(0x1) << PAC_INTFLAGB_CMCC_Pos)
291 #define PAC_INTFLAGB_PORT_Pos 4
292 #define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
293 #define PAC_INTFLAGB_DMAC_Pos 5
294 #define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
295 #define PAC_INTFLAGB_HMATRIX_Pos 6
296 #define PAC_INTFLAGB_HMATRIX (_U_(0x1) << PAC_INTFLAGB_HMATRIX_Pos)
297 #define PAC_INTFLAGB_EVSYS_Pos 7
298 #define PAC_INTFLAGB_EVSYS (_U_(0x1) << PAC_INTFLAGB_EVSYS_Pos)
299 #define PAC_INTFLAGB_SERCOM2_Pos 9
300 #define PAC_INTFLAGB_SERCOM2 (_U_(0x1) << PAC_INTFLAGB_SERCOM2_Pos)
301 #define PAC_INTFLAGB_SERCOM3_Pos 10
302 #define PAC_INTFLAGB_SERCOM3 (_U_(0x1) << PAC_INTFLAGB_SERCOM3_Pos)
303 #define PAC_INTFLAGB_TCC0_Pos 11
304 #define PAC_INTFLAGB_TCC0 (_U_(0x1) << PAC_INTFLAGB_TCC0_Pos)
305 #define PAC_INTFLAGB_TCC1_Pos 12
306 #define PAC_INTFLAGB_TCC1 (_U_(0x1) << PAC_INTFLAGB_TCC1_Pos)
307 #define PAC_INTFLAGB_TC2_Pos 13
308 #define PAC_INTFLAGB_TC2 (_U_(0x1) << PAC_INTFLAGB_TC2_Pos)
309 #define PAC_INTFLAGB_TC3_Pos 14
310 #define PAC_INTFLAGB_TC3 (_U_(0x1) << PAC_INTFLAGB_TC3_Pos)
311 #define PAC_INTFLAGB_RAMECC_Pos 16
312 #define PAC_INTFLAGB_RAMECC (_U_(0x1) << PAC_INTFLAGB_RAMECC_Pos)
313 #define PAC_INTFLAGB_MASK _U_(0x00017EFF)
316 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
340 #define PAC_INTFLAGC_OFFSET 0x1C
341 #define PAC_INTFLAGC_RESETVALUE _U_(0x00000000)
343 #define PAC_INTFLAGC_CAN0_Pos 0
344 #define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos)
345 #define PAC_INTFLAGC_CAN1_Pos 1
346 #define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos)
347 #define PAC_INTFLAGC_GMAC_Pos 2
348 #define PAC_INTFLAGC_GMAC (_U_(0x1) << PAC_INTFLAGC_GMAC_Pos)
349 #define PAC_INTFLAGC_TCC2_Pos 3
350 #define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
351 #define PAC_INTFLAGC_TCC3_Pos 4
352 #define PAC_INTFLAGC_TCC3 (_U_(0x1) << PAC_INTFLAGC_TCC3_Pos)
353 #define PAC_INTFLAGC_TC4_Pos 5
354 #define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
355 #define PAC_INTFLAGC_TC5_Pos 6
356 #define PAC_INTFLAGC_TC5 (_U_(0x1) << PAC_INTFLAGC_TC5_Pos)
357 #define PAC_INTFLAGC_PDEC_Pos 7
358 #define PAC_INTFLAGC_PDEC (_U_(0x1) << PAC_INTFLAGC_PDEC_Pos)
359 #define PAC_INTFLAGC_AC_Pos 8
360 #define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
361 #define PAC_INTFLAGC_AES_Pos 9
362 #define PAC_INTFLAGC_AES (_U_(0x1) << PAC_INTFLAGC_AES_Pos)
363 #define PAC_INTFLAGC_TRNG_Pos 10
364 #define PAC_INTFLAGC_TRNG (_U_(0x1) << PAC_INTFLAGC_TRNG_Pos)
365 #define PAC_INTFLAGC_ICM_Pos 11
366 #define PAC_INTFLAGC_ICM (_U_(0x1) << PAC_INTFLAGC_ICM_Pos)
367 #define PAC_INTFLAGC_PUKCC_Pos 12
368 #define PAC_INTFLAGC_PUKCC (_U_(0x1) << PAC_INTFLAGC_PUKCC_Pos)
369 #define PAC_INTFLAGC_QSPI_Pos 13
370 #define PAC_INTFLAGC_QSPI (_U_(0x1) << PAC_INTFLAGC_QSPI_Pos)
371 #define PAC_INTFLAGC_CCL_Pos 14
372 #define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
373 #define PAC_INTFLAGC_MASK _U_(0x00007FFF)
376 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
397 #define PAC_INTFLAGD_OFFSET 0x20
398 #define PAC_INTFLAGD_RESETVALUE _U_(0x00000000)
400 #define PAC_INTFLAGD_SERCOM4_Pos 0
401 #define PAC_INTFLAGD_SERCOM4 (_U_(0x1) << PAC_INTFLAGD_SERCOM4_Pos)
402 #define PAC_INTFLAGD_SERCOM5_Pos 1
403 #define PAC_INTFLAGD_SERCOM5 (_U_(0x1) << PAC_INTFLAGD_SERCOM5_Pos)
404 #define PAC_INTFLAGD_SERCOM6_Pos 2
405 #define PAC_INTFLAGD_SERCOM6 (_U_(0x1) << PAC_INTFLAGD_SERCOM6_Pos)
406 #define PAC_INTFLAGD_SERCOM7_Pos 3
407 #define PAC_INTFLAGD_SERCOM7 (_U_(0x1) << PAC_INTFLAGD_SERCOM7_Pos)
408 #define PAC_INTFLAGD_TCC4_Pos 4
409 #define PAC_INTFLAGD_TCC4 (_U_(0x1) << PAC_INTFLAGD_TCC4_Pos)
410 #define PAC_INTFLAGD_TC6_Pos 5
411 #define PAC_INTFLAGD_TC6 (_U_(0x1) << PAC_INTFLAGD_TC6_Pos)
412 #define PAC_INTFLAGD_TC7_Pos 6
413 #define PAC_INTFLAGD_TC7 (_U_(0x1) << PAC_INTFLAGD_TC7_Pos)
414 #define PAC_INTFLAGD_ADC0_Pos 7
415 #define PAC_INTFLAGD_ADC0 (_U_(0x1) << PAC_INTFLAGD_ADC0_Pos)
416 #define PAC_INTFLAGD_ADC1_Pos 8
417 #define PAC_INTFLAGD_ADC1 (_U_(0x1) << PAC_INTFLAGD_ADC1_Pos)
418 #define PAC_INTFLAGD_DAC_Pos 9
419 #define PAC_INTFLAGD_DAC (_U_(0x1) << PAC_INTFLAGD_DAC_Pos)
420 #define PAC_INTFLAGD_I2S_Pos 10
421 #define PAC_INTFLAGD_I2S (_U_(0x1) << PAC_INTFLAGD_I2S_Pos)
422 #define PAC_INTFLAGD_PCC_Pos 11
423 #define PAC_INTFLAGD_PCC (_U_(0x1) << PAC_INTFLAGD_PCC_Pos)
424 #define PAC_INTFLAGD_MASK _U_(0x00000FFF)
427 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
452 #define PAC_STATUSA_OFFSET 0x34
453 #define PAC_STATUSA_RESETVALUE _U_(0x00010000)
455 #define PAC_STATUSA_PAC_Pos 0
456 #define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos)
457 #define PAC_STATUSA_PM_Pos 1
458 #define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos)
459 #define PAC_STATUSA_MCLK_Pos 2
460 #define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
461 #define PAC_STATUSA_RSTC_Pos 3
462 #define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
463 #define PAC_STATUSA_OSCCTRL_Pos 4
464 #define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
465 #define PAC_STATUSA_OSC32KCTRL_Pos 5
466 #define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
467 #define PAC_STATUSA_SUPC_Pos 6
468 #define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
469 #define PAC_STATUSA_GCLK_Pos 7
470 #define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
471 #define PAC_STATUSA_WDT_Pos 8
472 #define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos)
473 #define PAC_STATUSA_RTC_Pos 9
474 #define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos)
475 #define PAC_STATUSA_EIC_Pos 10
476 #define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos)
477 #define PAC_STATUSA_FREQM_Pos 11
478 #define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
479 #define PAC_STATUSA_SERCOM0_Pos 12
480 #define PAC_STATUSA_SERCOM0 (_U_(0x1) << PAC_STATUSA_SERCOM0_Pos)
481 #define PAC_STATUSA_SERCOM1_Pos 13
482 #define PAC_STATUSA_SERCOM1 (_U_(0x1) << PAC_STATUSA_SERCOM1_Pos)
483 #define PAC_STATUSA_TC0_Pos 14
484 #define PAC_STATUSA_TC0 (_U_(0x1) << PAC_STATUSA_TC0_Pos)
485 #define PAC_STATUSA_TC1_Pos 15
486 #define PAC_STATUSA_TC1 (_U_(0x1) << PAC_STATUSA_TC1_Pos)
487 #define PAC_STATUSA_MASK _U_(0x0000FFFF)
490 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
516 #define PAC_STATUSB_OFFSET 0x38
517 #define PAC_STATUSB_RESETVALUE _U_(0x00000002)
519 #define PAC_STATUSB_USB_Pos 0
520 #define PAC_STATUSB_USB (_U_(0x1) << PAC_STATUSB_USB_Pos)
521 #define PAC_STATUSB_DSU_Pos 1
522 #define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos)
523 #define PAC_STATUSB_NVMCTRL_Pos 2
524 #define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
525 #define PAC_STATUSB_CMCC_Pos 3
526 #define PAC_STATUSB_CMCC (_U_(0x1) << PAC_STATUSB_CMCC_Pos)
527 #define PAC_STATUSB_PORT_Pos 4
528 #define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos)
529 #define PAC_STATUSB_DMAC_Pos 5
530 #define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
531 #define PAC_STATUSB_HMATRIX_Pos 6
532 #define PAC_STATUSB_HMATRIX (_U_(0x1) << PAC_STATUSB_HMATRIX_Pos)
533 #define PAC_STATUSB_EVSYS_Pos 7
534 #define PAC_STATUSB_EVSYS (_U_(0x1) << PAC_STATUSB_EVSYS_Pos)
535 #define PAC_STATUSB_SERCOM2_Pos 9
536 #define PAC_STATUSB_SERCOM2 (_U_(0x1) << PAC_STATUSB_SERCOM2_Pos)
537 #define PAC_STATUSB_SERCOM3_Pos 10
538 #define PAC_STATUSB_SERCOM3 (_U_(0x1) << PAC_STATUSB_SERCOM3_Pos)
539 #define PAC_STATUSB_TCC0_Pos 11
540 #define PAC_STATUSB_TCC0 (_U_(0x1) << PAC_STATUSB_TCC0_Pos)
541 #define PAC_STATUSB_TCC1_Pos 12
542 #define PAC_STATUSB_TCC1 (_U_(0x1) << PAC_STATUSB_TCC1_Pos)
543 #define PAC_STATUSB_TC2_Pos 13
544 #define PAC_STATUSB_TC2 (_U_(0x1) << PAC_STATUSB_TC2_Pos)
545 #define PAC_STATUSB_TC3_Pos 14
546 #define PAC_STATUSB_TC3 (_U_(0x1) << PAC_STATUSB_TC3_Pos)
547 #define PAC_STATUSB_RAMECC_Pos 16
548 #define PAC_STATUSB_RAMECC (_U_(0x1) << PAC_STATUSB_RAMECC_Pos)
549 #define PAC_STATUSB_MASK _U_(0x00017EFF)
552 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
576 #define PAC_STATUSC_OFFSET 0x3C
577 #define PAC_STATUSC_RESETVALUE _U_(0x00000000)
579 #define PAC_STATUSC_CAN0_Pos 0
580 #define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos)
581 #define PAC_STATUSC_CAN1_Pos 1
582 #define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos)
583 #define PAC_STATUSC_GMAC_Pos 2
584 #define PAC_STATUSC_GMAC (_U_(0x1) << PAC_STATUSC_GMAC_Pos)
585 #define PAC_STATUSC_TCC2_Pos 3
586 #define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
587 #define PAC_STATUSC_TCC3_Pos 4
588 #define PAC_STATUSC_TCC3 (_U_(0x1) << PAC_STATUSC_TCC3_Pos)
589 #define PAC_STATUSC_TC4_Pos 5
590 #define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos)
591 #define PAC_STATUSC_TC5_Pos 6
592 #define PAC_STATUSC_TC5 (_U_(0x1) << PAC_STATUSC_TC5_Pos)
593 #define PAC_STATUSC_PDEC_Pos 7
594 #define PAC_STATUSC_PDEC (_U_(0x1) << PAC_STATUSC_PDEC_Pos)
595 #define PAC_STATUSC_AC_Pos 8
596 #define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos)
597 #define PAC_STATUSC_AES_Pos 9
598 #define PAC_STATUSC_AES (_U_(0x1) << PAC_STATUSC_AES_Pos)
599 #define PAC_STATUSC_TRNG_Pos 10
600 #define PAC_STATUSC_TRNG (_U_(0x1) << PAC_STATUSC_TRNG_Pos)
601 #define PAC_STATUSC_ICM_Pos 11
602 #define PAC_STATUSC_ICM (_U_(0x1) << PAC_STATUSC_ICM_Pos)
603 #define PAC_STATUSC_PUKCC_Pos 12
604 #define PAC_STATUSC_PUKCC (_U_(0x1) << PAC_STATUSC_PUKCC_Pos)
605 #define PAC_STATUSC_QSPI_Pos 13
606 #define PAC_STATUSC_QSPI (_U_(0x1) << PAC_STATUSC_QSPI_Pos)
607 #define PAC_STATUSC_CCL_Pos 14
608 #define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
609 #define PAC_STATUSC_MASK _U_(0x00007FFF)
612 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
633 #define PAC_STATUSD_OFFSET 0x40
634 #define PAC_STATUSD_RESETVALUE _U_(0x00000000)
636 #define PAC_STATUSD_SERCOM4_Pos 0
637 #define PAC_STATUSD_SERCOM4 (_U_(0x1) << PAC_STATUSD_SERCOM4_Pos)
638 #define PAC_STATUSD_SERCOM5_Pos 1
639 #define PAC_STATUSD_SERCOM5 (_U_(0x1) << PAC_STATUSD_SERCOM5_Pos)
640 #define PAC_STATUSD_SERCOM6_Pos 2
641 #define PAC_STATUSD_SERCOM6 (_U_(0x1) << PAC_STATUSD_SERCOM6_Pos)
642 #define PAC_STATUSD_SERCOM7_Pos 3
643 #define PAC_STATUSD_SERCOM7 (_U_(0x1) << PAC_STATUSD_SERCOM7_Pos)
644 #define PAC_STATUSD_TCC4_Pos 4
645 #define PAC_STATUSD_TCC4 (_U_(0x1) << PAC_STATUSD_TCC4_Pos)
646 #define PAC_STATUSD_TC6_Pos 5
647 #define PAC_STATUSD_TC6 (_U_(0x1) << PAC_STATUSD_TC6_Pos)
648 #define PAC_STATUSD_TC7_Pos 6
649 #define PAC_STATUSD_TC7 (_U_(0x1) << PAC_STATUSD_TC7_Pos)
650 #define PAC_STATUSD_ADC0_Pos 7
651 #define PAC_STATUSD_ADC0 (_U_(0x1) << PAC_STATUSD_ADC0_Pos)
652 #define PAC_STATUSD_ADC1_Pos 8
653 #define PAC_STATUSD_ADC1 (_U_(0x1) << PAC_STATUSD_ADC1_Pos)
654 #define PAC_STATUSD_DAC_Pos 9
655 #define PAC_STATUSD_DAC (_U_(0x1) << PAC_STATUSD_DAC_Pos)
656 #define PAC_STATUSD_I2S_Pos 10
657 #define PAC_STATUSD_I2S (_U_(0x1) << PAC_STATUSD_I2S_Pos)
658 #define PAC_STATUSD_PCC_Pos 11
659 #define PAC_STATUSD_PCC (_U_(0x1) << PAC_STATUSD_PCC_Pos)
660 #define PAC_STATUSD_MASK _U_(0x00000FFF)
663 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO PAC_EVCTRL_Type EVCTRL
Offset: 0x04 (R/W 8) Event control.
__I PAC_STATUSA_Type STATUSA
Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A.
__IO PAC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt enable clear.
__IO PAC_INTFLAGC_Type INTFLAGC
Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C.
__IO PAC_INTFLAGA_Type INTFLAGA
Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A.
__I PAC_STATUSB_Type STATUSB
Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B.
__IO PAC_INTFLAGB_Type INTFLAGB
Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B.
__I PAC_STATUSC_Type STATUSC
Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C.
__IO PAC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt enable set.
__IO PAC_INTFLAGD_Type INTFLAGD
Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D.
__I PAC_STATUSD_Type STATUSD
Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D.
volatile const uint8_t RoReg8
__IO PAC_INTFLAGAHB_Type INTFLAGAHB
Offset: 0x10 (R/W 32) Bridge interrupt flag status.
__IO PAC_WRCTRL_Type WRCTRL
Offset: 0x00 (R/W 32) Write control.