Definition at line 864 of file sercom.h.
◆ __pad0__
uint8_t SERCOM_USART_INTENSET_Type::__pad0__ |
bit: 6 Reserved
Definition at line 872 of file sercom.h.
◆ bit
struct { ... } SERCOM_USART_INTENSET_Type::bit |
Structure used for bit access
◆ CTSIC
uint8_t SERCOM_USART_INTENSET_Type::CTSIC |
bit: 4 Clear To Send Input Change Interrupt Enable
Definition at line 870 of file sercom.h.
◆ DRE
uint8_t SERCOM_USART_INTENSET_Type::DRE |
bit: 0 Data Register Empty Interrupt Enable
Definition at line 866 of file sercom.h.
◆ ERROR
uint8_t SERCOM_USART_INTENSET_Type::ERROR |
bit: 7 Combined Error Interrupt Enable
Definition at line 873 of file sercom.h.
◆ reg
uint8_t SERCOM_USART_INTENSET_Type::reg |
Type used for register access
Definition at line 875 of file sercom.h.
◆ RXBRK
uint8_t SERCOM_USART_INTENSET_Type::RXBRK |
bit: 5 Break Received Interrupt Enable
Definition at line 871 of file sercom.h.
◆ RXC
uint8_t SERCOM_USART_INTENSET_Type::RXC |
bit: 2 Receive Complete Interrupt Enable
Definition at line 868 of file sercom.h.
◆ RXS
uint8_t SERCOM_USART_INTENSET_Type::RXS |
bit: 3 Receive Start Interrupt Enable
Definition at line 869 of file sercom.h.
◆ TXC
uint8_t SERCOM_USART_INTENSET_Type::TXC |
bit: 1 Transmit Complete Interrupt Enable
Definition at line 867 of file sercom.h.
The documentation for this union was generated from the following file:
- /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/sercom.h