SAME54P20A Test Project
wdt.h
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1 
30 #ifndef _SAME54_WDT_COMPONENT_
31 #define _SAME54_WDT_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define WDT_U2251
40 #define REV_WDT 0x110
41 
42 /* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t :1;
47  uint8_t ENABLE:1;
48  uint8_t WEN:1;
49  uint8_t :4;
50  uint8_t ALWAYSON:1;
51  } bit;
52  uint8_t reg;
54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
55 
56 #define WDT_CTRLA_OFFSET 0x0
57 #define WDT_CTRLA_RESETVALUE _U_(0x00)
59 #define WDT_CTRLA_ENABLE_Pos 1
60 #define WDT_CTRLA_ENABLE (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
61 #define WDT_CTRLA_WEN_Pos 2
62 #define WDT_CTRLA_WEN (_U_(0x1) << WDT_CTRLA_WEN_Pos)
63 #define WDT_CTRLA_ALWAYSON_Pos 7
64 #define WDT_CTRLA_ALWAYSON (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
65 #define WDT_CTRLA_MASK _U_(0x86)
67 /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
69 typedef union {
70  struct {
71  uint8_t PER:4;
72  uint8_t WINDOW:4;
73  } bit;
74  uint8_t reg;
76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
77 
78 #define WDT_CONFIG_OFFSET 0x1
79 #define WDT_CONFIG_RESETVALUE _U_(0xBB)
81 #define WDT_CONFIG_PER_Pos 0
82 #define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
83 #define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
84 #define WDT_CONFIG_PER_CYC8_Val _U_(0x0)
85 #define WDT_CONFIG_PER_CYC16_Val _U_(0x1)
86 #define WDT_CONFIG_PER_CYC32_Val _U_(0x2)
87 #define WDT_CONFIG_PER_CYC64_Val _U_(0x3)
88 #define WDT_CONFIG_PER_CYC128_Val _U_(0x4)
89 #define WDT_CONFIG_PER_CYC256_Val _U_(0x5)
90 #define WDT_CONFIG_PER_CYC512_Val _U_(0x6)
91 #define WDT_CONFIG_PER_CYC1024_Val _U_(0x7)
92 #define WDT_CONFIG_PER_CYC2048_Val _U_(0x8)
93 #define WDT_CONFIG_PER_CYC4096_Val _U_(0x9)
94 #define WDT_CONFIG_PER_CYC8192_Val _U_(0xA)
95 #define WDT_CONFIG_PER_CYC16384_Val _U_(0xB)
96 #define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)
97 #define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)
98 #define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)
99 #define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)
100 #define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)
101 #define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)
102 #define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)
103 #define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)
104 #define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)
105 #define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)
106 #define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)
107 #define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)
108 #define WDT_CONFIG_WINDOW_Pos 4
109 #define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
110 #define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
111 #define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0)
112 #define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1)
113 #define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2)
114 #define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3)
115 #define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4)
116 #define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5)
117 #define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6)
118 #define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7)
119 #define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8)
120 #define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9)
121 #define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA)
122 #define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB)
123 #define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos)
124 #define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos)
125 #define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos)
126 #define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos)
127 #define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos)
128 #define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos)
129 #define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos)
130 #define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
131 #define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
132 #define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
133 #define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
134 #define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
135 #define WDT_CONFIG_MASK _U_(0xFF)
137 /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
139 typedef union {
140  struct {
141  uint8_t EWOFFSET:4;
142  uint8_t :4;
143  } bit;
144  uint8_t reg;
146 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
147 
148 #define WDT_EWCTRL_OFFSET 0x2
149 #define WDT_EWCTRL_RESETVALUE _U_(0x0B)
151 #define WDT_EWCTRL_EWOFFSET_Pos 0
152 #define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
153 #define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
154 #define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0)
155 #define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1)
156 #define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2)
157 #define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3)
158 #define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4)
159 #define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5)
160 #define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6)
161 #define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7)
162 #define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8)
163 #define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9)
164 #define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA)
165 #define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB)
166 #define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos)
167 #define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
168 #define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
169 #define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
170 #define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
171 #define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
172 #define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
173 #define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
174 #define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
175 #define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
176 #define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
177 #define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
178 #define WDT_EWCTRL_MASK _U_(0x0F)
180 /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
181 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
182 typedef union {
183  struct {
184  uint8_t EW:1;
185  uint8_t :7;
186  } bit;
187  uint8_t reg;
189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
190 
191 #define WDT_INTENCLR_OFFSET 0x4
192 #define WDT_INTENCLR_RESETVALUE _U_(0x00)
194 #define WDT_INTENCLR_EW_Pos 0
195 #define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
196 #define WDT_INTENCLR_MASK _U_(0x01)
198 /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
200 typedef union {
201  struct {
202  uint8_t EW:1;
203  uint8_t :7;
204  } bit;
205  uint8_t reg;
207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
208 
209 #define WDT_INTENSET_OFFSET 0x5
210 #define WDT_INTENSET_RESETVALUE _U_(0x00)
212 #define WDT_INTENSET_EW_Pos 0
213 #define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
214 #define WDT_INTENSET_MASK _U_(0x01)
216 /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
218 typedef union { // __I to avoid read-modify-write on write-to-clear register
219  struct {
220  __I uint8_t EW:1;
221  __I uint8_t :7;
222  } bit;
223  uint8_t reg;
225 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
226 
227 #define WDT_INTFLAG_OFFSET 0x6
228 #define WDT_INTFLAG_RESETVALUE _U_(0x00)
230 #define WDT_INTFLAG_EW_Pos 0
231 #define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
232 #define WDT_INTFLAG_MASK _U_(0x01)
234 /* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */
235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
236 typedef union {
237  struct {
238  uint32_t :1;
239  uint32_t ENABLE:1;
240  uint32_t WEN:1;
241  uint32_t ALWAYSON:1;
242  uint32_t CLEAR:1;
243  uint32_t :27;
244  } bit;
245  uint32_t reg;
247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
248 
249 #define WDT_SYNCBUSY_OFFSET 0x8
250 #define WDT_SYNCBUSY_RESETVALUE _U_(0x00000000)
252 #define WDT_SYNCBUSY_ENABLE_Pos 1
253 #define WDT_SYNCBUSY_ENABLE (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
254 #define WDT_SYNCBUSY_WEN_Pos 2
255 #define WDT_SYNCBUSY_WEN (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
256 #define WDT_SYNCBUSY_ALWAYSON_Pos 3
257 #define WDT_SYNCBUSY_ALWAYSON (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
258 #define WDT_SYNCBUSY_CLEAR_Pos 4
259 #define WDT_SYNCBUSY_CLEAR (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
260 #define WDT_SYNCBUSY_MASK _U_(0x0000001E)
262 /* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */
263 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
264 typedef union {
265  struct {
266  uint8_t CLEAR:8;
267  } bit;
268  uint8_t reg;
270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
271 
272 #define WDT_CLEAR_OFFSET 0xC
273 #define WDT_CLEAR_RESETVALUE _U_(0x00)
275 #define WDT_CLEAR_CLEAR_Pos 0
276 #define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
277 #define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
278 #define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5)
279 #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
280 #define WDT_CLEAR_MASK _U_(0xFF)
283 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
284 typedef struct {
288  RoReg8 Reserved1[0x1];
292  RoReg8 Reserved2[0x1];
295 } Wdt;
296 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
297 
300 #endif /* _SAME54_WDT_COMPONENT_ */
Wdt
WDT hardware registers.
Definition: wdt.h:284
Wdt::CLEAR
__O WDT_CLEAR_Type CLEAR
Offset: 0xC ( /W 8) Clear.
Definition: wdt.h:294
Wdt::SYNCBUSY
__I WDT_SYNCBUSY_Type SYNCBUSY
Offset: 0x8 (R/ 32) Synchronization Busy.
Definition: wdt.h:293
WDT_CONFIG_Type::PER
uint8_t PER
Definition: wdt.h:71
WDT_INTENSET_Type::reg
uint8_t reg
Definition: wdt.h:205
WDT_INTENCLR_Type::reg
uint8_t reg
Definition: wdt.h:187
WDT_EWCTRL_Type
Definition: wdt.h:139
WDT_INTENCLR_Type
Definition: wdt.h:182
WDT_INTFLAG_Type::uint8_t
__I uint8_t
Definition: wdt.h:221
Wdt::INTFLAG
__IO WDT_INTFLAG_Type INTFLAG
Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear.
Definition: wdt.h:291
WDT_CLEAR_Type
Definition: wdt.h:264
Wdt::INTENCLR
__IO WDT_INTENCLR_Type INTENCLR
Offset: 0x4 (R/W 8) Interrupt Enable Clear.
Definition: wdt.h:289
WDT_CTRLA_Type::ALWAYSON
uint8_t ALWAYSON
Definition: wdt.h:50
WDT_CONFIG_Type::reg
uint8_t reg
Definition: wdt.h:74
WDT_CTRLA_Type
Definition: wdt.h:44
WDT_INTFLAG_Type
Definition: wdt.h:218
WDT_SYNCBUSY_Type::WEN
uint32_t WEN
Definition: wdt.h:240
WDT_INTENCLR_Type::EW
uint8_t EW
Definition: wdt.h:184
WDT_CLEAR_Type::CLEAR
uint8_t CLEAR
Definition: wdt.h:266
Wdt::CONFIG
__IO WDT_CONFIG_Type CONFIG
Offset: 0x1 (R/W 8) Configuration.
Definition: wdt.h:286
Wdt::INTENSET
__IO WDT_INTENSET_Type INTENSET
Offset: 0x5 (R/W 8) Interrupt Enable Set.
Definition: wdt.h:290
WDT_INTENSET_Type::EW
uint8_t EW
Definition: wdt.h:202
WDT_INTFLAG_Type::EW
__I uint8_t EW
Definition: wdt.h:220
WDT_CTRLA_Type::WEN
uint8_t WEN
Definition: wdt.h:48
Wdt::EWCTRL
__IO WDT_EWCTRL_Type EWCTRL
Offset: 0x2 (R/W 8) Early Warning Interrupt Control.
Definition: wdt.h:287
WDT_INTENSET_Type
Definition: wdt.h:200
WDT_SYNCBUSY_Type::reg
uint32_t reg
Definition: wdt.h:245
WDT_SYNCBUSY_Type
Definition: wdt.h:236
WDT_EWCTRL_Type::reg
uint8_t reg
Definition: wdt.h:144
WDT_SYNCBUSY_Type::ALWAYSON
uint32_t ALWAYSON
Definition: wdt.h:241
WDT_EWCTRL_Type::EWOFFSET
uint8_t EWOFFSET
Definition: wdt.h:141
WDT_SYNCBUSY_Type::ENABLE
uint32_t ENABLE
Definition: wdt.h:239
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
Wdt::CTRLA
__IO WDT_CTRLA_Type CTRLA
Offset: 0x0 (R/W 8) Control.
Definition: wdt.h:285
WDT_CONFIG_Type
Definition: wdt.h:69
WDT_INTFLAG_Type::reg
uint8_t reg
Definition: wdt.h:223
WDT_SYNCBUSY_Type::CLEAR
uint32_t CLEAR
Definition: wdt.h:242
WDT_CLEAR_Type::reg
uint8_t reg
Definition: wdt.h:268
WDT_CONFIG_Type::WINDOW
uint8_t WINDOW
Definition: wdt.h:72
WDT_CTRLA_Type::reg
uint8_t reg
Definition: wdt.h:52
WDT_CTRLA_Type::ENABLE
uint8_t ENABLE
Definition: wdt.h:47