SAME54P20A Test Project
gclk.h
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1 
30 #ifndef _SAME54_GCLK_INSTANCE_
31 #define _SAME54_GCLK_INSTANCE_
32 
33 /* ========== Register definition for GCLK peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_GCLK_CTRLA (0x40001C00)
36 #define REG_GCLK_SYNCBUSY (0x40001C04)
37 #define REG_GCLK_GENCTRL0 (0x40001C20)
38 #define REG_GCLK_GENCTRL1 (0x40001C24)
39 #define REG_GCLK_GENCTRL2 (0x40001C28)
40 #define REG_GCLK_GENCTRL3 (0x40001C2C)
41 #define REG_GCLK_GENCTRL4 (0x40001C30)
42 #define REG_GCLK_GENCTRL5 (0x40001C34)
43 #define REG_GCLK_GENCTRL6 (0x40001C38)
44 #define REG_GCLK_GENCTRL7 (0x40001C3C)
45 #define REG_GCLK_GENCTRL8 (0x40001C40)
46 #define REG_GCLK_GENCTRL9 (0x40001C44)
47 #define REG_GCLK_GENCTRL10 (0x40001C48)
48 #define REG_GCLK_GENCTRL11 (0x40001C4C)
49 #define REG_GCLK_PCHCTRL0 (0x40001C80)
50 #define REG_GCLK_PCHCTRL1 (0x40001C84)
51 #define REG_GCLK_PCHCTRL2 (0x40001C88)
52 #define REG_GCLK_PCHCTRL3 (0x40001C8C)
53 #define REG_GCLK_PCHCTRL4 (0x40001C90)
54 #define REG_GCLK_PCHCTRL5 (0x40001C94)
55 #define REG_GCLK_PCHCTRL6 (0x40001C98)
56 #define REG_GCLK_PCHCTRL7 (0x40001C9C)
57 #define REG_GCLK_PCHCTRL8 (0x40001CA0)
58 #define REG_GCLK_PCHCTRL9 (0x40001CA4)
59 #define REG_GCLK_PCHCTRL10 (0x40001CA8)
60 #define REG_GCLK_PCHCTRL11 (0x40001CAC)
61 #define REG_GCLK_PCHCTRL12 (0x40001CB0)
62 #define REG_GCLK_PCHCTRL13 (0x40001CB4)
63 #define REG_GCLK_PCHCTRL14 (0x40001CB8)
64 #define REG_GCLK_PCHCTRL15 (0x40001CBC)
65 #define REG_GCLK_PCHCTRL16 (0x40001CC0)
66 #define REG_GCLK_PCHCTRL17 (0x40001CC4)
67 #define REG_GCLK_PCHCTRL18 (0x40001CC8)
68 #define REG_GCLK_PCHCTRL19 (0x40001CCC)
69 #define REG_GCLK_PCHCTRL20 (0x40001CD0)
70 #define REG_GCLK_PCHCTRL21 (0x40001CD4)
71 #define REG_GCLK_PCHCTRL22 (0x40001CD8)
72 #define REG_GCLK_PCHCTRL23 (0x40001CDC)
73 #define REG_GCLK_PCHCTRL24 (0x40001CE0)
74 #define REG_GCLK_PCHCTRL25 (0x40001CE4)
75 #define REG_GCLK_PCHCTRL26 (0x40001CE8)
76 #define REG_GCLK_PCHCTRL27 (0x40001CEC)
77 #define REG_GCLK_PCHCTRL28 (0x40001CF0)
78 #define REG_GCLK_PCHCTRL29 (0x40001CF4)
79 #define REG_GCLK_PCHCTRL30 (0x40001CF8)
80 #define REG_GCLK_PCHCTRL31 (0x40001CFC)
81 #define REG_GCLK_PCHCTRL32 (0x40001D00)
82 #define REG_GCLK_PCHCTRL33 (0x40001D04)
83 #define REG_GCLK_PCHCTRL34 (0x40001D08)
84 #define REG_GCLK_PCHCTRL35 (0x40001D0C)
85 #define REG_GCLK_PCHCTRL36 (0x40001D10)
86 #define REG_GCLK_PCHCTRL37 (0x40001D14)
87 #define REG_GCLK_PCHCTRL38 (0x40001D18)
88 #define REG_GCLK_PCHCTRL39 (0x40001D1C)
89 #define REG_GCLK_PCHCTRL40 (0x40001D20)
90 #define REG_GCLK_PCHCTRL41 (0x40001D24)
91 #define REG_GCLK_PCHCTRL42 (0x40001D28)
92 #define REG_GCLK_PCHCTRL43 (0x40001D2C)
93 #define REG_GCLK_PCHCTRL44 (0x40001D30)
94 #define REG_GCLK_PCHCTRL45 (0x40001D34)
95 #define REG_GCLK_PCHCTRL46 (0x40001D38)
96 #define REG_GCLK_PCHCTRL47 (0x40001D3C)
97 #else
98 #define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL)
99 #define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL)
100 #define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL)
101 #define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL)
102 #define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL)
103 #define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL)
104 #define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL)
105 #define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001C34UL)
106 #define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001C38UL)
107 #define REG_GCLK_GENCTRL7 (*(RwReg *)0x40001C3CUL)
108 #define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001C40UL)
109 #define REG_GCLK_GENCTRL9 (*(RwReg *)0x40001C44UL)
110 #define REG_GCLK_GENCTRL10 (*(RwReg *)0x40001C48UL)
111 #define REG_GCLK_GENCTRL11 (*(RwReg *)0x40001C4CUL)
112 #define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL)
113 #define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL)
114 #define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL)
115 #define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL)
116 #define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL)
117 #define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL)
118 #define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL)
119 #define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL)
120 #define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL)
121 #define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL)
122 #define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL)
123 #define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL)
124 #define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL)
125 #define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL)
126 #define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL)
127 #define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL)
128 #define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL)
129 #define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL)
130 #define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL)
131 #define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL)
132 #define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL)
133 #define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL)
134 #define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL)
135 #define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL)
136 #define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL)
137 #define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL)
138 #define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL)
139 #define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL)
140 #define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL)
141 #define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL)
142 #define REG_GCLK_PCHCTRL30 (*(RwReg *)0x40001CF8UL)
143 #define REG_GCLK_PCHCTRL31 (*(RwReg *)0x40001CFCUL)
144 #define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001D00UL)
145 #define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001D04UL)
146 #define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001D08UL)
147 #define REG_GCLK_PCHCTRL35 (*(RwReg *)0x40001D0CUL)
148 #define REG_GCLK_PCHCTRL36 (*(RwReg *)0x40001D10UL)
149 #define REG_GCLK_PCHCTRL37 (*(RwReg *)0x40001D14UL)
150 #define REG_GCLK_PCHCTRL38 (*(RwReg *)0x40001D18UL)
151 #define REG_GCLK_PCHCTRL39 (*(RwReg *)0x40001D1CUL)
152 #define REG_GCLK_PCHCTRL40 (*(RwReg *)0x40001D20UL)
153 #define REG_GCLK_PCHCTRL41 (*(RwReg *)0x40001D24UL)
154 #define REG_GCLK_PCHCTRL42 (*(RwReg *)0x40001D28UL)
155 #define REG_GCLK_PCHCTRL43 (*(RwReg *)0x40001D2CUL)
156 #define REG_GCLK_PCHCTRL44 (*(RwReg *)0x40001D30UL)
157 #define REG_GCLK_PCHCTRL45 (*(RwReg *)0x40001D34UL)
158 #define REG_GCLK_PCHCTRL46 (*(RwReg *)0x40001D38UL)
159 #define REG_GCLK_PCHCTRL47 (*(RwReg *)0x40001D3CUL)
160 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
161 
162 /* ========== Instance parameters for GCLK peripheral ========== */
163 #define GCLK_GENCTRL0_RESETVALUE 106 // Default specific reset value for generator 0
164 #define GCLK_GENDIV_BITS 16
165 #define GCLK_GEN_BITS 4
166 #define GCLK_GEN_NUM 12 // Number of Generic Clock Generators
167 #define GCLK_GEN_NUM_MSB 11 // Number of Generic Clock Generators - 1
168 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
169 #define GCLK_IO_NUM 8 // Number of Generic Clock I/Os
170 #define GCLK_NUM 48 // Number of Generic Clock Users
171 #define GCLK_SOURCE_BITS 4
172 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
173 #define GCLK_SOURCE_XOSC0 0 // Crystal Oscillator 0
174 #define GCLK_SOURCE_XOSC 0 // Alias to GCLK_SOURCE_XOSC0
175 #define GCLK_SOURCE_XOSC1 1 // Crystal Oscillator 1
176 #define GCLK_SOURCE_GCLKIN 2 // Input Pin of Corresponding GCLK Generator
177 #define GCLK_SOURCE_GCLKGEN1 3 // GCLK Generator 1 output
178 #define GCLK_SOURCE_OSCULP32K 4 // Ultra-low-power 32kHz Oscillator
179 #define GCLK_SOURCE_XOSC32K 5 // 32kHz Crystal Oscillator
180 #define GCLK_SOURCE_DFLL 6 // Digital FLL
181 #define GCLK_SOURCE_DFLL48M 6 // Alias to GCLK_SOURCE_DFLL
182 #define GCLK_SOURCE_OSC16M 6 // Alias to GCLK_SOURCE_DFLL
183 #define GCLK_SOURCE_OSC48M 6 // Alias to GCLK_SOURCE_DFLL
184 #define GCLK_SOURCE_DPLL0 7 // Digital PLL 0
185 #define GCLK_SOURCE_FDPLL 7 // Alias to GCLK_SOURCE_DPLL0
186 #define GCLK_SOURCE_FDPLL0 7 // Alias to GCLK_SOURCE_DPLL0
187 #define GCLK_SOURCE_DPLL1 8 // Digital PLL 1
188 #define GCLK_SOURCE_FDPLL1 8 // Alias to GCLK_SOURCE_DPLL1
189 #define GCLK_GEN_DIV_BITS { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }
190 
191 #endif /* _SAME54_GCLK_INSTANCE_ */