SAME54P20A Test Project
mclk.h
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1 
30 #ifndef _SAME54_MCLK_COMPONENT_
31 #define _SAME54_MCLK_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define MCLK_U2408
40 #define REV_MCLK 0x100
41 
42 /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t CKRDY:1;
47  uint8_t :7;
48  } bit;
49  uint8_t reg;
51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
52 
53 #define MCLK_INTENCLR_OFFSET 0x01
54 #define MCLK_INTENCLR_RESETVALUE _U_(0x00)
56 #define MCLK_INTENCLR_CKRDY_Pos 0
57 #define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
58 #define MCLK_INTENCLR_MASK _U_(0x01)
60 /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
62 typedef union {
63  struct {
64  uint8_t CKRDY:1;
65  uint8_t :7;
66  } bit;
67  uint8_t reg;
69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
70 
71 #define MCLK_INTENSET_OFFSET 0x02
72 #define MCLK_INTENSET_RESETVALUE _U_(0x00)
74 #define MCLK_INTENSET_CKRDY_Pos 0
75 #define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
76 #define MCLK_INTENSET_MASK _U_(0x01)
78 /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
80 typedef union { // __I to avoid read-modify-write on write-to-clear register
81  struct {
82  __I uint8_t CKRDY:1;
83  __I uint8_t :7;
84  } bit;
85  uint8_t reg;
87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
88 
89 #define MCLK_INTFLAG_OFFSET 0x03
90 #define MCLK_INTFLAG_RESETVALUE _U_(0x01)
92 #define MCLK_INTFLAG_CKRDY_Pos 0
93 #define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
94 #define MCLK_INTFLAG_MASK _U_(0x01)
96 /* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/ 8) HS Clock Division -------- */
97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
98 typedef union {
99  struct {
100  uint8_t DIV:8;
101  } bit;
102  uint8_t reg;
104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
105 
106 #define MCLK_HSDIV_OFFSET 0x04
107 #define MCLK_HSDIV_RESETVALUE _U_(0x01)
109 #define MCLK_HSDIV_DIV_Pos 0
110 #define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos)
111 #define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos))
112 #define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1)
113 #define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos)
114 #define MCLK_HSDIV_MASK _U_(0xFF)
116 /* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */
117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
118 typedef union {
119  struct {
120  uint8_t DIV:8;
121  } bit;
122  uint8_t reg;
124 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
125 
126 #define MCLK_CPUDIV_OFFSET 0x05
127 #define MCLK_CPUDIV_RESETVALUE _U_(0x01)
129 #define MCLK_CPUDIV_DIV_Pos 0
130 #define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos)
131 #define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos))
132 #define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1)
133 #define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2)
134 #define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4)
135 #define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8)
136 #define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10)
137 #define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20)
138 #define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40)
139 #define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80)
140 #define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos)
141 #define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos)
142 #define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos)
143 #define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos)
144 #define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos)
145 #define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos)
146 #define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos)
147 #define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos)
148 #define MCLK_CPUDIV_MASK _U_(0xFF)
150 /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
152 typedef union {
153  struct {
154  uint32_t HPB0_:1;
155  uint32_t HPB1_:1;
156  uint32_t HPB2_:1;
157  uint32_t HPB3_:1;
158  uint32_t DSU_:1;
159  uint32_t HMATRIX_:1;
160  uint32_t NVMCTRL_:1;
161  uint32_t HSRAM_:1;
162  uint32_t CMCC_:1;
163  uint32_t DMAC_:1;
164  uint32_t USB_:1;
165  uint32_t BKUPRAM_:1;
166  uint32_t PAC_:1;
167  uint32_t QSPI_:1;
168  uint32_t GMAC_:1;
169  uint32_t SDHC0_:1;
170  uint32_t SDHC1_:1;
171  uint32_t CAN0_:1;
172  uint32_t CAN1_:1;
173  uint32_t ICM_:1;
174  uint32_t PUKCC_:1;
175  uint32_t QSPI_2X_:1;
176  uint32_t NVMCTRL_SMEEPROM_:1;
177  uint32_t NVMCTRL_CACHE_:1;
178  uint32_t :8;
179  } bit;
180  uint32_t reg;
182 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
183 
184 #define MCLK_AHBMASK_OFFSET 0x10
185 #define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF)
187 #define MCLK_AHBMASK_HPB0_Pos 0
188 #define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
189 #define MCLK_AHBMASK_HPB1_Pos 1
190 #define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
191 #define MCLK_AHBMASK_HPB2_Pos 2
192 #define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
193 #define MCLK_AHBMASK_HPB3_Pos 3
194 #define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos)
195 #define MCLK_AHBMASK_DSU_Pos 4
196 #define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
197 #define MCLK_AHBMASK_HMATRIX_Pos 5
198 #define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos)
199 #define MCLK_AHBMASK_NVMCTRL_Pos 6
200 #define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
201 #define MCLK_AHBMASK_HSRAM_Pos 7
202 #define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
203 #define MCLK_AHBMASK_CMCC_Pos 8
204 #define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos)
205 #define MCLK_AHBMASK_DMAC_Pos 9
206 #define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
207 #define MCLK_AHBMASK_USB_Pos 10
208 #define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos)
209 #define MCLK_AHBMASK_BKUPRAM_Pos 11
210 #define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos)
211 #define MCLK_AHBMASK_PAC_Pos 12
212 #define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
213 #define MCLK_AHBMASK_QSPI_Pos 13
214 #define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos)
215 #define MCLK_AHBMASK_GMAC_Pos 14
216 #define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos)
217 #define MCLK_AHBMASK_SDHC0_Pos 15
218 #define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos)
219 #define MCLK_AHBMASK_SDHC1_Pos 16
220 #define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos)
221 #define MCLK_AHBMASK_CAN0_Pos 17
222 #define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
223 #define MCLK_AHBMASK_CAN1_Pos 18
224 #define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
225 #define MCLK_AHBMASK_ICM_Pos 19
226 #define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos)
227 #define MCLK_AHBMASK_PUKCC_Pos 20
228 #define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos)
229 #define MCLK_AHBMASK_QSPI_2X_Pos 21
230 #define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos)
231 #define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22
232 #define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos)
233 #define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23
234 #define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos)
235 #define MCLK_AHBMASK_MASK _U_(0x00FFFFFF)
237 /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
238 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
239 typedef union {
240  struct {
241  uint32_t PAC_:1;
242  uint32_t PM_:1;
243  uint32_t MCLK_:1;
244  uint32_t RSTC_:1;
245  uint32_t OSCCTRL_:1;
246  uint32_t OSC32KCTRL_:1;
247  uint32_t SUPC_:1;
248  uint32_t GCLK_:1;
249  uint32_t WDT_:1;
250  uint32_t RTC_:1;
251  uint32_t EIC_:1;
252  uint32_t FREQM_:1;
253  uint32_t SERCOM0_:1;
254  uint32_t SERCOM1_:1;
255  uint32_t TC0_:1;
256  uint32_t TC1_:1;
257  uint32_t :16;
258  } bit;
259  uint32_t reg;
261 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
262 
263 #define MCLK_APBAMASK_OFFSET 0x14
264 #define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF)
266 #define MCLK_APBAMASK_PAC_Pos 0
267 #define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
268 #define MCLK_APBAMASK_PM_Pos 1
269 #define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
270 #define MCLK_APBAMASK_MCLK_Pos 2
271 #define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
272 #define MCLK_APBAMASK_RSTC_Pos 3
273 #define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
274 #define MCLK_APBAMASK_OSCCTRL_Pos 4
275 #define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
276 #define MCLK_APBAMASK_OSC32KCTRL_Pos 5
277 #define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
278 #define MCLK_APBAMASK_SUPC_Pos 6
279 #define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
280 #define MCLK_APBAMASK_GCLK_Pos 7
281 #define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
282 #define MCLK_APBAMASK_WDT_Pos 8
283 #define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
284 #define MCLK_APBAMASK_RTC_Pos 9
285 #define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
286 #define MCLK_APBAMASK_EIC_Pos 10
287 #define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
288 #define MCLK_APBAMASK_FREQM_Pos 11
289 #define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
290 #define MCLK_APBAMASK_SERCOM0_Pos 12
291 #define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos)
292 #define MCLK_APBAMASK_SERCOM1_Pos 13
293 #define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos)
294 #define MCLK_APBAMASK_TC0_Pos 14
295 #define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos)
296 #define MCLK_APBAMASK_TC1_Pos 15
297 #define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos)
298 #define MCLK_APBAMASK_MASK _U_(0x0000FFFF)
300 /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
301 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
302 typedef union {
303  struct {
304  uint32_t USB_:1;
305  uint32_t DSU_:1;
306  uint32_t NVMCTRL_:1;
307  uint32_t :1;
308  uint32_t PORT_:1;
309  uint32_t :1;
310  uint32_t HMATRIX_:1;
311  uint32_t EVSYS_:1;
312  uint32_t :1;
313  uint32_t SERCOM2_:1;
314  uint32_t SERCOM3_:1;
315  uint32_t TCC0_:1;
316  uint32_t TCC1_:1;
317  uint32_t TC2_:1;
318  uint32_t TC3_:1;
319  uint32_t :1;
320  uint32_t RAMECC_:1;
321  uint32_t :15;
322  } bit;
323  uint32_t reg;
325 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
326 
327 #define MCLK_APBBMASK_OFFSET 0x18
328 #define MCLK_APBBMASK_RESETVALUE _U_(0x00018056)
330 #define MCLK_APBBMASK_USB_Pos 0
331 #define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos)
332 #define MCLK_APBBMASK_DSU_Pos 1
333 #define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
334 #define MCLK_APBBMASK_NVMCTRL_Pos 2
335 #define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
336 #define MCLK_APBBMASK_PORT_Pos 4
337 #define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
338 #define MCLK_APBBMASK_HMATRIX_Pos 6
339 #define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos)
340 #define MCLK_APBBMASK_EVSYS_Pos 7
341 #define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos)
342 #define MCLK_APBBMASK_SERCOM2_Pos 9
343 #define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos)
344 #define MCLK_APBBMASK_SERCOM3_Pos 10
345 #define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos)
346 #define MCLK_APBBMASK_TCC0_Pos 11
347 #define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos)
348 #define MCLK_APBBMASK_TCC1_Pos 12
349 #define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos)
350 #define MCLK_APBBMASK_TC2_Pos 13
351 #define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos)
352 #define MCLK_APBBMASK_TC3_Pos 14
353 #define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos)
354 #define MCLK_APBBMASK_RAMECC_Pos 16
355 #define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos)
356 #define MCLK_APBBMASK_MASK _U_(0x00017ED7)
358 /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
359 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
360 typedef union {
361  struct {
362  uint32_t :2;
363  uint32_t GMAC_:1;
364  uint32_t TCC2_:1;
365  uint32_t TCC3_:1;
366  uint32_t TC4_:1;
367  uint32_t TC5_:1;
368  uint32_t PDEC_:1;
369  uint32_t AC_:1;
370  uint32_t AES_:1;
371  uint32_t TRNG_:1;
372  uint32_t ICM_:1;
373  uint32_t :1;
374  uint32_t QSPI_:1;
375  uint32_t CCL_:1;
376  uint32_t :17;
377  } bit;
378  uint32_t reg;
380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
381 
382 #define MCLK_APBCMASK_OFFSET 0x1C
383 #define MCLK_APBCMASK_RESETVALUE _U_(0x00002000)
385 #define MCLK_APBCMASK_GMAC_Pos 2
386 #define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos)
387 #define MCLK_APBCMASK_TCC2_Pos 3
388 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
389 #define MCLK_APBCMASK_TCC3_Pos 4
390 #define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos)
391 #define MCLK_APBCMASK_TC4_Pos 5
392 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
393 #define MCLK_APBCMASK_TC5_Pos 6
394 #define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos)
395 #define MCLK_APBCMASK_PDEC_Pos 7
396 #define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos)
397 #define MCLK_APBCMASK_AC_Pos 8
398 #define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
399 #define MCLK_APBCMASK_AES_Pos 9
400 #define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos)
401 #define MCLK_APBCMASK_TRNG_Pos 10
402 #define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos)
403 #define MCLK_APBCMASK_ICM_Pos 11
404 #define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos)
405 #define MCLK_APBCMASK_QSPI_Pos 13
406 #define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos)
407 #define MCLK_APBCMASK_CCL_Pos 14
408 #define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
409 #define MCLK_APBCMASK_MASK _U_(0x00006FFC)
411 /* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */
412 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
413 typedef union {
414  struct {
415  uint32_t SERCOM4_:1;
416  uint32_t SERCOM5_:1;
417  uint32_t SERCOM6_:1;
418  uint32_t SERCOM7_:1;
419  uint32_t TCC4_:1;
420  uint32_t TC6_:1;
421  uint32_t TC7_:1;
422  uint32_t ADC0_:1;
423  uint32_t ADC1_:1;
424  uint32_t DAC_:1;
425  uint32_t I2S_:1;
426  uint32_t PCC_:1;
427  uint32_t :20;
428  } bit;
429  uint32_t reg;
431 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
432 
433 #define MCLK_APBDMASK_OFFSET 0x20
434 #define MCLK_APBDMASK_RESETVALUE _U_(0x00000000)
436 #define MCLK_APBDMASK_SERCOM4_Pos 0
437 #define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos)
438 #define MCLK_APBDMASK_SERCOM5_Pos 1
439 #define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos)
440 #define MCLK_APBDMASK_SERCOM6_Pos 2
441 #define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos)
442 #define MCLK_APBDMASK_SERCOM7_Pos 3
443 #define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos)
444 #define MCLK_APBDMASK_TCC4_Pos 4
445 #define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos)
446 #define MCLK_APBDMASK_TC6_Pos 5
447 #define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos)
448 #define MCLK_APBDMASK_TC7_Pos 6
449 #define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos)
450 #define MCLK_APBDMASK_ADC0_Pos 7
451 #define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos)
452 #define MCLK_APBDMASK_ADC1_Pos 8
453 #define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos)
454 #define MCLK_APBDMASK_DAC_Pos 9
455 #define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos)
456 #define MCLK_APBDMASK_I2S_Pos 10
457 #define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos)
458 #define MCLK_APBDMASK_PCC_Pos 11
459 #define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos)
460 #define MCLK_APBDMASK_MASK _U_(0x00000FFF)
463 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
464 typedef struct {
465  RoReg8 Reserved1[0x1];
471  RoReg8 Reserved2[0xA];
477 } Mclk;
478 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
479 
482 #endif /* _SAME54_MCLK_COMPONENT_ */
MCLK_INTENCLR_Type::CKRDY
uint8_t CKRDY
Definition: mclk.h:46
MCLK_APBDMASK_Type::SERCOM6_
uint32_t SERCOM6_
Definition: mclk.h:417
MCLK_APBCMASK_Type::AC_
uint32_t AC_
Definition: mclk.h:369
MCLK_APBCMASK_Type::ICM_
uint32_t ICM_
Definition: mclk.h:372
MCLK_APBDMASK_Type::TC6_
uint32_t TC6_
Definition: mclk.h:420
Mclk::APBCMASK
__IO MCLK_APBCMASK_Type APBCMASK
Offset: 0x1C (R/W 32) APBC Mask.
Definition: mclk.h:475
MCLK_AHBMASK_Type::DMAC_
uint32_t DMAC_
Definition: mclk.h:163
MCLK_APBAMASK_Type::TC1_
uint32_t TC1_
Definition: mclk.h:256
Mclk::HSDIV
__I MCLK_HSDIV_Type HSDIV
Offset: 0x04 (R/ 8) HS Clock Division.
Definition: mclk.h:469
MCLK_APBDMASK_Type::TCC4_
uint32_t TCC4_
Definition: mclk.h:419
MCLK_APBAMASK_Type::SERCOM1_
uint32_t SERCOM1_
Definition: mclk.h:254
MCLK_APBAMASK_Type
Definition: mclk.h:239
MCLK_APBBMASK_Type::TCC1_
uint32_t TCC1_
Definition: mclk.h:316
MCLK_APBDMASK_Type::ADC1_
uint32_t ADC1_
Definition: mclk.h:423
MCLK_HSDIV_Type::DIV
uint8_t DIV
Definition: mclk.h:100
MCLK_APBDMASK_Type::SERCOM4_
uint32_t SERCOM4_
Definition: mclk.h:415
MCLK_AHBMASK_Type::HMATRIX_
uint32_t HMATRIX_
Definition: mclk.h:159
MCLK_CPUDIV_Type::DIV
uint8_t DIV
Definition: mclk.h:120
MCLK_APBBMASK_Type::DSU_
uint32_t DSU_
Definition: mclk.h:305
MCLK_AHBMASK_Type::reg
uint32_t reg
Definition: mclk.h:180
MCLK_AHBMASK_Type::BKUPRAM_
uint32_t BKUPRAM_
Definition: mclk.h:165
MCLK_APBDMASK_Type::SERCOM5_
uint32_t SERCOM5_
Definition: mclk.h:416
MCLK_APBBMASK_Type::TCC0_
uint32_t TCC0_
Definition: mclk.h:315
MCLK_INTENCLR_Type::reg
uint8_t reg
Definition: mclk.h:49
MCLK_APBCMASK_Type::CCL_
uint32_t CCL_
Definition: mclk.h:375
MCLK_APBBMASK_Type::HMATRIX_
uint32_t HMATRIX_
Definition: mclk.h:310
MCLK_APBBMASK_Type::USB_
uint32_t USB_
Definition: mclk.h:304
MCLK_AHBMASK_Type::GMAC_
uint32_t GMAC_
Definition: mclk.h:168
MCLK_AHBMASK_Type::PAC_
uint32_t PAC_
Definition: mclk.h:166
MCLK_APBAMASK_Type::PAC_
uint32_t PAC_
Definition: mclk.h:241
MCLK_AHBMASK_Type::HSRAM_
uint32_t HSRAM_
Definition: mclk.h:161
MCLK_APBCMASK_Type
Definition: mclk.h:360
MCLK_CPUDIV_Type::reg
uint8_t reg
Definition: mclk.h:122
Mclk::INTENSET
__IO MCLK_INTENSET_Type INTENSET
Offset: 0x02 (R/W 8) Interrupt Enable Set.
Definition: mclk.h:467
MCLK_APBCMASK_Type::TC4_
uint32_t TC4_
Definition: mclk.h:366
MCLK_APBAMASK_Type::PM_
uint32_t PM_
Definition: mclk.h:242
MCLK_AHBMASK_Type::PUKCC_
uint32_t PUKCC_
Definition: mclk.h:174
MCLK_AHBMASK_Type::CAN1_
uint32_t CAN1_
Definition: mclk.h:172
MCLK_APBBMASK_Type::RAMECC_
uint32_t RAMECC_
Definition: mclk.h:320
MCLK_APBAMASK_Type::MCLK_
uint32_t MCLK_
Definition: mclk.h:243
MCLK_APBBMASK_Type::reg
uint32_t reg
Definition: mclk.h:323
MCLK_AHBMASK_Type::DSU_
uint32_t DSU_
Definition: mclk.h:158
MCLK_APBDMASK_Type::I2S_
uint32_t I2S_
Definition: mclk.h:425
MCLK_INTFLAG_Type::reg
uint8_t reg
Definition: mclk.h:85
MCLK_APBAMASK_Type::OSCCTRL_
uint32_t OSCCTRL_
Definition: mclk.h:245
Mclk::APBBMASK
__IO MCLK_APBBMASK_Type APBBMASK
Offset: 0x18 (R/W 32) APBB Mask.
Definition: mclk.h:474
MCLK_APBAMASK_Type::reg
uint32_t reg
Definition: mclk.h:259
MCLK_APBDMASK_Type::reg
uint32_t reg
Definition: mclk.h:429
MCLK_APBBMASK_Type::NVMCTRL_
uint32_t NVMCTRL_
Definition: mclk.h:306
MCLK_AHBMASK_Type::HPB0_
uint32_t HPB0_
Definition: mclk.h:154
Mclk::INTENCLR
__IO MCLK_INTENCLR_Type INTENCLR
Offset: 0x01 (R/W 8) Interrupt Enable Clear.
Definition: mclk.h:466
MCLK_APBCMASK_Type::QSPI_
uint32_t QSPI_
Definition: mclk.h:374
Mclk::APBDMASK
__IO MCLK_APBDMASK_Type APBDMASK
Offset: 0x20 (R/W 32) APBD Mask.
Definition: mclk.h:476
MCLK_AHBMASK_Type::QSPI_2X_
uint32_t QSPI_2X_
Definition: mclk.h:175
MCLK_APBCMASK_Type::TRNG_
uint32_t TRNG_
Definition: mclk.h:371
MCLK_INTENSET_Type::CKRDY
uint8_t CKRDY
Definition: mclk.h:64
MCLK_APBAMASK_Type::TC0_
uint32_t TC0_
Definition: mclk.h:255
Mclk::AHBMASK
__IO MCLK_AHBMASK_Type AHBMASK
Offset: 0x10 (R/W 32) AHB Mask.
Definition: mclk.h:472
MCLK_APBCMASK_Type::reg
uint32_t reg
Definition: mclk.h:378
MCLK_AHBMASK_Type::SDHC0_
uint32_t SDHC0_
Definition: mclk.h:169
MCLK_APBBMASK_Type::TC2_
uint32_t TC2_
Definition: mclk.h:317
MCLK_INTFLAG_Type
Definition: mclk.h:80
MCLK_INTENSET_Type
Definition: mclk.h:62
MCLK_APBAMASK_Type::EIC_
uint32_t EIC_
Definition: mclk.h:251
MCLK_INTFLAG_Type::uint8_t
__I uint8_t
Definition: mclk.h:83
MCLK_APBBMASK_Type
Definition: mclk.h:302
Mclk::INTFLAG
__IO MCLK_INTFLAG_Type INTFLAG
Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear.
Definition: mclk.h:468
MCLK_APBAMASK_Type::OSC32KCTRL_
uint32_t OSC32KCTRL_
Definition: mclk.h:246
MCLK_APBAMASK_Type::GCLK_
uint32_t GCLK_
Definition: mclk.h:248
MCLK_APBBMASK_Type::PORT_
uint32_t PORT_
Definition: mclk.h:308
Mclk::CPUDIV
__IO MCLK_CPUDIV_Type CPUDIV
Offset: 0x05 (R/W 8) CPU Clock Division.
Definition: mclk.h:470
MCLK_AHBMASK_Type::NVMCTRL_
uint32_t NVMCTRL_
Definition: mclk.h:160
MCLK_AHBMASK_Type::USB_
uint32_t USB_
Definition: mclk.h:164
MCLK_INTFLAG_Type::CKRDY
__I uint8_t CKRDY
Definition: mclk.h:82
MCLK_APBAMASK_Type::SUPC_
uint32_t SUPC_
Definition: mclk.h:247
MCLK_INTENSET_Type::reg
uint8_t reg
Definition: mclk.h:67
MCLK_APBAMASK_Type::FREQM_
uint32_t FREQM_
Definition: mclk.h:252
MCLK_APBDMASK_Type::PCC_
uint32_t PCC_
Definition: mclk.h:426
Mclk::APBAMASK
__IO MCLK_APBAMASK_Type APBAMASK
Offset: 0x14 (R/W 32) APBA Mask.
Definition: mclk.h:473
MCLK_APBBMASK_Type::TC3_
uint32_t TC3_
Definition: mclk.h:318
MCLK_APBAMASK_Type::RTC_
uint32_t RTC_
Definition: mclk.h:250
MCLK_APBDMASK_Type::SERCOM7_
uint32_t SERCOM7_
Definition: mclk.h:418
MCLK_APBCMASK_Type::GMAC_
uint32_t GMAC_
Definition: mclk.h:363
MCLK_AHBMASK_Type
Definition: mclk.h:152
MCLK_APBAMASK_Type::RSTC_
uint32_t RSTC_
Definition: mclk.h:244
MCLK_AHBMASK_Type::HPB1_
uint32_t HPB1_
Definition: mclk.h:155
MCLK_APBBMASK_Type::EVSYS_
uint32_t EVSYS_
Definition: mclk.h:311
Mclk
MCLK hardware registers.
Definition: mclk.h:464
MCLK_APBCMASK_Type::TCC2_
uint32_t TCC2_
Definition: mclk.h:364
MCLK_INTENCLR_Type
Definition: mclk.h:44
MCLK_AHBMASK_Type::NVMCTRL_CACHE_
uint32_t NVMCTRL_CACHE_
Definition: mclk.h:177
MCLK_APBDMASK_Type
Definition: mclk.h:413
MCLK_HSDIV_Type::reg
uint8_t reg
Definition: mclk.h:102
MCLK_AHBMASK_Type::HPB3_
uint32_t HPB3_
Definition: mclk.h:157
MCLK_HSDIV_Type
Definition: mclk.h:98
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
MCLK_CPUDIV_Type
Definition: mclk.h:118
MCLK_AHBMASK_Type::NVMCTRL_SMEEPROM_
uint32_t NVMCTRL_SMEEPROM_
Definition: mclk.h:176
MCLK_AHBMASK_Type::SDHC1_
uint32_t SDHC1_
Definition: mclk.h:170
MCLK_APBDMASK_Type::TC7_
uint32_t TC7_
Definition: mclk.h:421
MCLK_AHBMASK_Type::ICM_
uint32_t ICM_
Definition: mclk.h:173
MCLK_APBCMASK_Type::AES_
uint32_t AES_
Definition: mclk.h:370
MCLK_APBCMASK_Type::PDEC_
uint32_t PDEC_
Definition: mclk.h:368
MCLK_AHBMASK_Type::CAN0_
uint32_t CAN0_
Definition: mclk.h:171
MCLK_APBDMASK_Type::DAC_
uint32_t DAC_
Definition: mclk.h:424
MCLK_AHBMASK_Type::HPB2_
uint32_t HPB2_
Definition: mclk.h:156
MCLK_AHBMASK_Type::QSPI_
uint32_t QSPI_
Definition: mclk.h:167
MCLK_APBBMASK_Type::SERCOM2_
uint32_t SERCOM2_
Definition: mclk.h:313
MCLK_APBDMASK_Type::ADC0_
uint32_t ADC0_
Definition: mclk.h:422
MCLK_APBAMASK_Type::SERCOM0_
uint32_t SERCOM0_
Definition: mclk.h:253
MCLK_APBAMASK_Type::WDT_
uint32_t WDT_
Definition: mclk.h:249
MCLK_APBCMASK_Type::TC5_
uint32_t TC5_
Definition: mclk.h:367
MCLK_AHBMASK_Type::CMCC_
uint32_t CMCC_
Definition: mclk.h:162
MCLK_APBBMASK_Type::SERCOM3_
uint32_t SERCOM3_
Definition: mclk.h:314
MCLK_APBCMASK_Type::TCC3_
uint32_t TCC3_
Definition: mclk.h:365