SAME54P20A Test Project
freqm.h
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1 
30 #ifndef _SAME54_FREQM_COMPONENT_
31 #define _SAME54_FREQM_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define FREQM_U2257
40 #define REV_FREQM 0x110
41 
42 /* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t SWRST:1;
47  uint8_t ENABLE:1;
48  uint8_t :6;
49  } bit;
50  uint8_t reg;
52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
53 
54 #define FREQM_CTRLA_OFFSET 0x00
55 #define FREQM_CTRLA_RESETVALUE _U_(0x00)
57 #define FREQM_CTRLA_SWRST_Pos 0
58 #define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
59 #define FREQM_CTRLA_ENABLE_Pos 1
60 #define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
61 #define FREQM_CTRLA_MASK _U_(0x03)
63 /* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
65 typedef union {
66  struct {
67  uint8_t START:1;
68  uint8_t :7;
69  } bit;
70  uint8_t reg;
72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
73 
74 #define FREQM_CTRLB_OFFSET 0x01
75 #define FREQM_CTRLB_RESETVALUE _U_(0x00)
77 #define FREQM_CTRLB_START_Pos 0
78 #define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
79 #define FREQM_CTRLB_MASK _U_(0x01)
81 /* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
83 typedef union {
84  struct {
85  uint16_t REFNUM:8;
86  uint16_t :8;
87  } bit;
88  uint16_t reg;
90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
91 
92 #define FREQM_CFGA_OFFSET 0x02
93 #define FREQM_CFGA_RESETVALUE _U_(0x0000)
95 #define FREQM_CFGA_REFNUM_Pos 0
96 #define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
97 #define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
98 #define FREQM_CFGA_MASK _U_(0x00FF)
100 /* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
102 typedef union {
103  struct {
104  uint8_t DONE:1;
105  uint8_t :7;
106  } bit;
107  uint8_t reg;
109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
110 
111 #define FREQM_INTENCLR_OFFSET 0x08
112 #define FREQM_INTENCLR_RESETVALUE _U_(0x00)
114 #define FREQM_INTENCLR_DONE_Pos 0
115 #define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
116 #define FREQM_INTENCLR_MASK _U_(0x01)
118 /* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
120 typedef union {
121  struct {
122  uint8_t DONE:1;
123  uint8_t :7;
124  } bit;
125  uint8_t reg;
127 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
128 
129 #define FREQM_INTENSET_OFFSET 0x09
130 #define FREQM_INTENSET_RESETVALUE _U_(0x00)
132 #define FREQM_INTENSET_DONE_Pos 0
133 #define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
134 #define FREQM_INTENSET_MASK _U_(0x01)
136 /* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
138 typedef union { // __I to avoid read-modify-write on write-to-clear register
139  struct {
140  __I uint8_t DONE:1;
141  __I uint8_t :7;
142  } bit;
143  uint8_t reg;
145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
146 
147 #define FREQM_INTFLAG_OFFSET 0x0A
148 #define FREQM_INTFLAG_RESETVALUE _U_(0x00)
150 #define FREQM_INTFLAG_DONE_Pos 0
151 #define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
152 #define FREQM_INTFLAG_MASK _U_(0x01)
154 /* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
156 typedef union {
157  struct {
158  uint8_t BUSY:1;
159  uint8_t OVF:1;
160  uint8_t :6;
161  } bit;
162  uint8_t reg;
164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
165 
166 #define FREQM_STATUS_OFFSET 0x0B
167 #define FREQM_STATUS_RESETVALUE _U_(0x00)
169 #define FREQM_STATUS_BUSY_Pos 0
170 #define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
171 #define FREQM_STATUS_OVF_Pos 1
172 #define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
173 #define FREQM_STATUS_MASK _U_(0x03)
175 /* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
177 typedef union {
178  struct {
179  uint32_t SWRST:1;
180  uint32_t ENABLE:1;
181  uint32_t :30;
182  } bit;
183  uint32_t reg;
185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
186 
187 #define FREQM_SYNCBUSY_OFFSET 0x0C
188 #define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000)
190 #define FREQM_SYNCBUSY_SWRST_Pos 0
191 #define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
192 #define FREQM_SYNCBUSY_ENABLE_Pos 1
193 #define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
194 #define FREQM_SYNCBUSY_MASK _U_(0x00000003)
196 /* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
198 typedef union {
199  struct {
200  uint32_t VALUE:24;
201  uint32_t :8;
202  } bit;
203  uint32_t reg;
205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
206 
207 #define FREQM_VALUE_OFFSET 0x10
208 #define FREQM_VALUE_RESETVALUE _U_(0x00000000)
210 #define FREQM_VALUE_VALUE_Pos 0
211 #define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
212 #define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
213 #define FREQM_VALUE_MASK _U_(0x00FFFFFF)
216 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
217 typedef struct {
221  RoReg8 Reserved1[0x4];
228 } Freqm;
229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
230 
233 #endif /* _SAME54_FREQM_COMPONENT_ */
FREQM_CTRLA_Type::reg
uint8_t reg
Definition: freqm.h:50
Freqm::STATUS
__IO FREQM_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status Register.
Definition: freqm.h:225
FREQM_VALUE_Type::reg
uint32_t reg
Definition: freqm.h:203
Freqm::CFGA
__IO FREQM_CFGA_Type CFGA
Offset: 0x02 (R/W 16) Config A register.
Definition: freqm.h:220
Freqm::VALUE
__I FREQM_VALUE_Type VALUE
Offset: 0x10 (R/ 32) Count Value Register.
Definition: freqm.h:227
FREQM_CTRLA_Type::ENABLE
uint8_t ENABLE
Definition: freqm.h:47
FREQM_CTRLB_Type::reg
uint8_t reg
Definition: freqm.h:70
FREQM_INTFLAG_Type::uint8_t
__I uint8_t
Definition: freqm.h:141
Freqm
FREQM hardware registers.
Definition: freqm.h:217
FREQM_STATUS_Type::OVF
uint8_t OVF
Definition: freqm.h:159
Freqm::INTENSET
__IO FREQM_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set Register.
Definition: freqm.h:223
FREQM_CFGA_Type
Definition: freqm.h:83
FREQM_STATUS_Type
Definition: freqm.h:156
FREQM_VALUE_Type
Definition: freqm.h:198
Freqm::SYNCBUSY
__I FREQM_SYNCBUSY_Type SYNCBUSY
Offset: 0x0C (R/ 32) Synchronization Busy Register.
Definition: freqm.h:226
FREQM_CFGA_Type::REFNUM
uint16_t REFNUM
Definition: freqm.h:85
FREQM_SYNCBUSY_Type::SWRST
uint32_t SWRST
Definition: freqm.h:179
FREQM_CTRLB_Type
Definition: freqm.h:65
FREQM_CTRLA_Type::SWRST
uint8_t SWRST
Definition: freqm.h:46
FREQM_CFGA_Type::reg
uint16_t reg
Definition: freqm.h:88
Freqm::INTENCLR
__IO FREQM_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear Register.
Definition: freqm.h:222
FREQM_SYNCBUSY_Type
Definition: freqm.h:177
FREQM_INTFLAG_Type::reg
uint8_t reg
Definition: freqm.h:143
FREQM_INTENSET_Type
Definition: freqm.h:120
FREQM_INTENSET_Type::DONE
uint8_t DONE
Definition: freqm.h:122
FREQM_SYNCBUSY_Type::reg
uint32_t reg
Definition: freqm.h:183
FREQM_INTFLAG_Type
Definition: freqm.h:138
FREQM_INTFLAG_Type::DONE
__I uint8_t DONE
Definition: freqm.h:140
FREQM_INTENSET_Type::reg
uint8_t reg
Definition: freqm.h:125
FREQM_SYNCBUSY_Type::ENABLE
uint32_t ENABLE
Definition: freqm.h:180
FREQM_INTENCLR_Type::DONE
uint8_t DONE
Definition: freqm.h:104
Freqm::CTRLB
__O FREQM_CTRLB_Type CTRLB
Offset: 0x01 ( /W 8) Control B Register.
Definition: freqm.h:219
FREQM_INTENCLR_Type::reg
uint8_t reg
Definition: freqm.h:107
Freqm::INTFLAG
__IO FREQM_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Register.
Definition: freqm.h:224
FREQM_CTRLA_Type
Definition: freqm.h:44
FREQM_CTRLB_Type::START
uint8_t START
Definition: freqm.h:67
FREQM_VALUE_Type::VALUE
uint32_t VALUE
Definition: freqm.h:200
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
FREQM_STATUS_Type::BUSY
uint8_t BUSY
Definition: freqm.h:158
FREQM_STATUS_Type::reg
uint8_t reg
Definition: freqm.h:162
Freqm::CTRLA
__IO FREQM_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A Register.
Definition: freqm.h:218
FREQM_INTENCLR_Type
Definition: freqm.h:102