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30 #ifndef _SAME54_AES_COMPONENT_
31 #define _SAME54_AES_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
64 #define AES_CTRLA_OFFSET 0x00
65 #define AES_CTRLA_RESETVALUE _U_(0x00000000)
67 #define AES_CTRLA_SWRST_Pos 0
68 #define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
69 #define AES_CTRLA_ENABLE_Pos 1
70 #define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
71 #define AES_CTRLA_AESMODE_Pos 2
72 #define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
73 #define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
74 #define AES_CTRLA_AESMODE_ECB_Val _U_(0x0)
75 #define AES_CTRLA_AESMODE_CBC_Val _U_(0x1)
76 #define AES_CTRLA_AESMODE_OFB_Val _U_(0x2)
77 #define AES_CTRLA_AESMODE_CFB_Val _U_(0x3)
78 #define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4)
79 #define AES_CTRLA_AESMODE_CCM_Val _U_(0x5)
80 #define AES_CTRLA_AESMODE_GCM_Val _U_(0x6)
81 #define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
82 #define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
83 #define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
84 #define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
85 #define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
86 #define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
87 #define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
88 #define AES_CTRLA_CFBS_Pos 5
89 #define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
90 #define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
91 #define AES_CTRLA_CFBS_128BIT_Val _U_(0x0)
92 #define AES_CTRLA_CFBS_64BIT_Val _U_(0x1)
93 #define AES_CTRLA_CFBS_32BIT_Val _U_(0x2)
94 #define AES_CTRLA_CFBS_16BIT_Val _U_(0x3)
95 #define AES_CTRLA_CFBS_8BIT_Val _U_(0x4)
96 #define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
97 #define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
98 #define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
99 #define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
100 #define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
101 #define AES_CTRLA_KEYSIZE_Pos 8
102 #define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
103 #define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
104 #define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0)
105 #define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1)
106 #define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2)
107 #define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
108 #define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
109 #define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
110 #define AES_CTRLA_CIPHER_Pos 10
111 #define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
112 #define AES_CTRLA_CIPHER_DEC_Val _U_(0x0)
113 #define AES_CTRLA_CIPHER_ENC_Val _U_(0x1)
114 #define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
115 #define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
116 #define AES_CTRLA_STARTMODE_Pos 11
117 #define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
118 #define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0)
119 #define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1)
120 #define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
121 #define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
122 #define AES_CTRLA_LOD_Pos 12
123 #define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
124 #define AES_CTRLA_LOD_NONE_Val _U_(0x0)
125 #define AES_CTRLA_LOD_LAST_Val _U_(0x1)
126 #define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
127 #define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
128 #define AES_CTRLA_KEYGEN_Pos 13
129 #define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
130 #define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0)
131 #define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1)
132 #define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
133 #define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
134 #define AES_CTRLA_XORKEY_Pos 14
135 #define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
136 #define AES_CTRLA_XORKEY_NONE_Val _U_(0x0)
137 #define AES_CTRLA_XORKEY_XOR_Val _U_(0x1)
138 #define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
139 #define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
140 #define AES_CTRLA_CTYPE_Pos 16
141 #define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
142 #define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
143 #define AES_CTRLA_MASK _U_(0x000F7FFF)
146 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
159 #define AES_CTRLB_OFFSET 0x04
160 #define AES_CTRLB_RESETVALUE _U_(0x00)
162 #define AES_CTRLB_START_Pos 0
163 #define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
164 #define AES_CTRLB_NEWMSG_Pos 1
165 #define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
166 #define AES_CTRLB_EOM_Pos 2
167 #define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
168 #define AES_CTRLB_GFMUL_Pos 3
169 #define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
170 #define AES_CTRLB_MASK _U_(0x0F)
173 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
184 #define AES_INTENCLR_OFFSET 0x05
185 #define AES_INTENCLR_RESETVALUE _U_(0x00)
187 #define AES_INTENCLR_ENCCMP_Pos 0
188 #define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
189 #define AES_INTENCLR_GFMCMP_Pos 1
190 #define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
191 #define AES_INTENCLR_MASK _U_(0x03)
194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
205 #define AES_INTENSET_OFFSET 0x06
206 #define AES_INTENSET_RESETVALUE _U_(0x00)
208 #define AES_INTENSET_ENCCMP_Pos 0
209 #define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
210 #define AES_INTENSET_GFMCMP_Pos 1
211 #define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
212 #define AES_INTENSET_MASK _U_(0x03)
215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
226 #define AES_INTFLAG_OFFSET 0x07
227 #define AES_INTFLAG_RESETVALUE _U_(0x00)
229 #define AES_INTFLAG_ENCCMP_Pos 0
230 #define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
231 #define AES_INTFLAG_GFMCMP_Pos 1
232 #define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
233 #define AES_INTFLAG_MASK _U_(0x03)
236 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
246 #define AES_DATABUFPTR_OFFSET 0x08
247 #define AES_DATABUFPTR_RESETVALUE _U_(0x00)
249 #define AES_DATABUFPTR_INDATAPTR_Pos 0
250 #define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
251 #define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
252 #define AES_DATABUFPTR_MASK _U_(0x03)
255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
265 #define AES_DBGCTRL_OFFSET 0x09
266 #define AES_DBGCTRL_RESETVALUE _U_(0x00)
268 #define AES_DBGCTRL_DBGRUN_Pos 0
269 #define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
270 #define AES_DBGCTRL_MASK _U_(0x01)
273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
279 #define AES_KEYWORD_OFFSET 0x0C
280 #define AES_KEYWORD_RESETVALUE _U_(0x00000000)
281 #define AES_KEYWORD_MASK _U_(0xFFFFFFFF)
284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
290 #define AES_INDATA_OFFSET 0x38
291 #define AES_INDATA_RESETVALUE _U_(0x00000000)
292 #define AES_INDATA_MASK _U_(0xFFFFFFFF)
295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
301 #define AES_INTVECTV_OFFSET 0x3C
302 #define AES_INTVECTV_RESETVALUE _U_(0x00000000)
303 #define AES_INTVECTV_MASK _U_(0xFFFFFFFF)
306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
312 #define AES_HASHKEY_OFFSET 0x5C
313 #define AES_HASHKEY_RESETVALUE _U_(0x00000000)
314 #define AES_HASHKEY_MASK _U_(0xFFFFFFFF)
317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
323 #define AES_GHASH_OFFSET 0x6C
324 #define AES_GHASH_RESETVALUE _U_(0x00000000)
325 #define AES_GHASH_MASK _U_(0xFFFFFFFF)
328 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
334 #define AES_CIPLEN_OFFSET 0x80
335 #define AES_CIPLEN_RESETVALUE _U_(0x00000000)
336 #define AES_CIPLEN_MASK _U_(0xFFFFFFFF)
339 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
345 #define AES_RANDSEED_OFFSET 0x84
346 #define AES_RANDSEED_RESETVALUE _U_(0x00000000)
347 #define AES_RANDSEED_MASK _U_(0xFFFFFFFF)
350 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO AES_RANDSEED_Type RANDSEED
Offset: 0x84 (R/W 32) Random Seed.
__IO AES_INTFLAG_Type INTFLAG
Offset: 0x07 (R/W 8) Interrupt Flag Status.
__IO AES_CTRLB_Type CTRLB
Offset: 0x04 (R/W 8) Control B.
__IO AES_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
__IO AES_INTENCLR_Type INTENCLR
Offset: 0x05 (R/W 8) Interrupt Enable Clear.
__IO AES_CIPLEN_Type CIPLEN
Offset: 0x80 (R/W 32) Cipher Length.
__IO AES_DATABUFPTR_Type DATABUFPTR
Offset: 0x08 (R/W 8) Data buffer pointer.
__IO AES_INTENSET_Type INTENSET
Offset: 0x06 (R/W 8) Interrupt Enable Set.
__IO AES_INDATA_Type INDATA
Offset: 0x38 (R/W 32) Indata.
volatile const uint8_t RoReg8
__IO AES_DBGCTRL_Type DBGCTRL
Offset: 0x09 (R/W 8) Debug control.