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30 #ifndef _SAME54_PCC_COMPONENT_
31 #define _SAME54_PCC_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
63 #define PCC_MR_OFFSET 0x00
64 #define PCC_MR_RESETVALUE _U_(0x00000000)
66 #define PCC_MR_PCEN_Pos 0
67 #define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
68 #define PCC_MR_DSIZE_Pos 4
69 #define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
70 #define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
71 #define PCC_MR_SCALE_Pos 8
72 #define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
73 #define PCC_MR_ALWYS_Pos 9
74 #define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
75 #define PCC_MR_HALFS_Pos 10
76 #define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
77 #define PCC_MR_FRSTS_Pos 11
78 #define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
79 #define PCC_MR_ISIZE_Pos 16
80 #define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
81 #define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
82 #define PCC_MR_CID_Pos 30
83 #define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
84 #define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
85 #define PCC_MR_MASK _U_(0xC0070F31)
88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
99 #define PCC_IER_OFFSET 0x04
100 #define PCC_IER_RESETVALUE _U_(0x00000000)
102 #define PCC_IER_DRDY_Pos 0
103 #define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
104 #define PCC_IER_OVRE_Pos 1
105 #define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
106 #define PCC_IER_MASK _U_(0x00000003)
109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
120 #define PCC_IDR_OFFSET 0x08
121 #define PCC_IDR_RESETVALUE _U_(0x00000000)
123 #define PCC_IDR_DRDY_Pos 0
124 #define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
125 #define PCC_IDR_OVRE_Pos 1
126 #define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
127 #define PCC_IDR_MASK _U_(0x00000003)
130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
141 #define PCC_IMR_OFFSET 0x0C
142 #define PCC_IMR_RESETVALUE _U_(0x00000000)
144 #define PCC_IMR_DRDY_Pos 0
145 #define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
146 #define PCC_IMR_OVRE_Pos 1
147 #define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
148 #define PCC_IMR_MASK _U_(0x00000003)
151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
162 #define PCC_ISR_OFFSET 0x10
163 #define PCC_ISR_RESETVALUE _U_(0x00000000)
165 #define PCC_ISR_DRDY_Pos 0
166 #define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
167 #define PCC_ISR_OVRE_Pos 1
168 #define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
169 #define PCC_ISR_MASK _U_(0x00000003)
172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
181 #define PCC_RHR_OFFSET 0x14
182 #define PCC_RHR_RESETVALUE _U_(0x00000000)
184 #define PCC_RHR_RDATA_Pos 0
185 #define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
186 #define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
187 #define PCC_RHR_MASK _U_(0xFFFFFFFF)
190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
201 #define PCC_WPMR_OFFSET 0xE0
202 #define PCC_WPMR_RESETVALUE _U_(0x00000000)
204 #define PCC_WPMR_WPEN_Pos 0
205 #define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
206 #define PCC_WPMR_WPKEY_Pos 8
207 #define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
208 #define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
209 #define PCC_WPMR_MASK _U_(0xFFFFFF01)
212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
224 #define PCC_WPSR_OFFSET 0xE4
225 #define PCC_WPSR_RESETVALUE _U_(0x00000000)
227 #define PCC_WPSR_WPVS_Pos 0
228 #define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
229 #define PCC_WPSR_WPVSRC_Pos 8
230 #define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
231 #define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
232 #define PCC_WPSR_MASK _U_(0x00FFFF01)
235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__I PCC_IMR_Type IMR
Offset: 0x0C (R/ 32) Interrupt Mask Register.
__IO PCC_MR_Type MR
Offset: 0x00 (R/W 32) Mode Register.
__I PCC_RHR_Type RHR
Offset: 0x14 (R/ 32) Reception Holding Register.
__O PCC_IER_Type IER
Offset: 0x04 ( /W 32) Interrupt Enable Register.
__IO PCC_WPMR_Type WPMR
Offset: 0xE0 (R/W 32) Write Protection Mode Register.
__I PCC_WPSR_Type WPSR
Offset: 0xE4 (R/ 32) Write Protection Status Register.
volatile const uint8_t RoReg8
__I PCC_ISR_Type ISR
Offset: 0x10 (R/ 32) Interrupt Status Register.
__O PCC_IDR_Type IDR
Offset: 0x08 ( /W 32) Interrupt Disable Register.