SAME54P20A Test Project
pm.h
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1 
30 #ifndef _SAME54_PM_COMPONENT_
31 #define _SAME54_PM_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define PM_U2406
40 #define REV_PM 0x100
41 
42 /* -------- PM_CTRLA : (PM Offset: 0x00) (R/W 8) Control A -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t :2;
47  uint8_t IORET:1;
48  uint8_t :5;
49  } bit;
50  uint8_t reg;
52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
53 
54 #define PM_CTRLA_OFFSET 0x00
55 #define PM_CTRLA_RESETVALUE _U_(0x00)
57 #define PM_CTRLA_IORET_Pos 2
58 #define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
59 #define PM_CTRLA_MASK _U_(0x04)
61 /* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
63 typedef union {
64  struct {
65  uint8_t SLEEPMODE:3;
66  uint8_t :5;
67  } bit;
68  uint8_t reg;
70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
71 
72 #define PM_SLEEPCFG_OFFSET 0x01
73 #define PM_SLEEPCFG_RESETVALUE _U_(0x02)
75 #define PM_SLEEPCFG_SLEEPMODE_Pos 0
76 #define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
77 #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
78 #define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0)
79 #define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1)
80 #define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2)
81 #define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4)
82 #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5)
83 #define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6)
84 #define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7)
85 #define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
86 #define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
87 #define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
88 #define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
89 #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
90 #define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
91 #define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
92 #define PM_SLEEPCFG_MASK _U_(0x07)
94 /* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
96 typedef union {
97  struct {
98  uint8_t SLEEPRDY:1;
99  uint8_t :7;
100  } bit;
101  uint8_t reg;
103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
104 
105 #define PM_INTENCLR_OFFSET 0x04
106 #define PM_INTENCLR_RESETVALUE _U_(0x00)
108 #define PM_INTENCLR_SLEEPRDY_Pos 0
109 #define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
110 #define PM_INTENCLR_MASK _U_(0x01)
112 /* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
114 typedef union {
115  struct {
116  uint8_t SLEEPRDY:1;
117  uint8_t :7;
118  } bit;
119  uint8_t reg;
121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
122 
123 #define PM_INTENSET_OFFSET 0x05
124 #define PM_INTENSET_RESETVALUE _U_(0x00)
126 #define PM_INTENSET_SLEEPRDY_Pos 0
127 #define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
128 #define PM_INTENSET_MASK _U_(0x01)
130 /* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
132 typedef union { // __I to avoid read-modify-write on write-to-clear register
133  struct {
134  __I uint8_t SLEEPRDY:1;
135  __I uint8_t :7;
136  } bit;
137  uint8_t reg;
139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
140 
141 #define PM_INTFLAG_OFFSET 0x06
142 #define PM_INTFLAG_RESETVALUE _U_(0x00)
144 #define PM_INTFLAG_SLEEPRDY_Pos 0
145 #define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
146 #define PM_INTFLAG_MASK _U_(0x01)
148 /* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 8) Standby Configuration -------- */
149 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
150 typedef union {
151  struct {
152  uint8_t RAMCFG:2;
153  uint8_t :2;
154  uint8_t FASTWKUP:2;
155  uint8_t :2;
156  } bit;
157  uint8_t reg;
159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
160 
161 #define PM_STDBYCFG_OFFSET 0x08
162 #define PM_STDBYCFG_RESETVALUE _U_(0x00)
164 #define PM_STDBYCFG_RAMCFG_Pos 0
165 #define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
166 #define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
167 #define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0)
168 #define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1)
169 #define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2)
170 #define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
171 #define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
172 #define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
173 #define PM_STDBYCFG_FASTWKUP_Pos 4
174 #define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
175 #define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
176 #define PM_STDBYCFG_MASK _U_(0x33)
178 /* -------- PM_HIBCFG : (PM Offset: 0x09) (R/W 8) Hibernate Configuration -------- */
179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
180 typedef union {
181  struct {
182  uint8_t RAMCFG:2;
183  uint8_t BRAMCFG:2;
184  uint8_t :4;
185  } bit;
186  uint8_t reg;
188 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
189 
190 #define PM_HIBCFG_OFFSET 0x09
191 #define PM_HIBCFG_RESETVALUE _U_(0x00)
193 #define PM_HIBCFG_RAMCFG_Pos 0
194 #define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
195 #define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
196 #define PM_HIBCFG_BRAMCFG_Pos 2
197 #define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
198 #define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
199 #define PM_HIBCFG_MASK _U_(0x0F)
201 /* -------- PM_BKUPCFG : (PM Offset: 0x0A) (R/W 8) Backup Configuration -------- */
202 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
203 typedef union {
204  struct {
205  uint8_t BRAMCFG:2;
206  uint8_t :6;
207  } bit;
208  uint8_t reg;
210 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
211 
212 #define PM_BKUPCFG_OFFSET 0x0A
213 #define PM_BKUPCFG_RESETVALUE _U_(0x00)
215 #define PM_BKUPCFG_BRAMCFG_Pos 0
216 #define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
217 #define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
218 #define PM_BKUPCFG_MASK _U_(0x03)
220 /* -------- PM_PWSAKDLY : (PM Offset: 0x12) (R/W 8) Power Switch Acknowledge Delay -------- */
221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
222 typedef union {
223  struct {
224  uint8_t DLYVAL:7;
225  uint8_t IGNACK:1;
226  } bit;
227  uint8_t reg;
229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
230 
231 #define PM_PWSAKDLY_OFFSET 0x12
232 #define PM_PWSAKDLY_RESETVALUE _U_(0x00)
234 #define PM_PWSAKDLY_DLYVAL_Pos 0
235 #define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
236 #define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
237 #define PM_PWSAKDLY_IGNACK_Pos 7
238 #define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
239 #define PM_PWSAKDLY_MASK _U_(0xFF)
242 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
243 typedef struct {
246  RoReg8 Reserved1[0x2];
250  RoReg8 Reserved2[0x1];
254  RoReg8 Reserved3[0x7];
256 } Pm;
257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
258 
261 #endif /* _SAME54_PM_COMPONENT_ */
PM_INTENCLR_Type
Definition: pm.h:96
Pm::HIBCFG
__IO PM_HIBCFG_Type HIBCFG
Offset: 0x09 (R/W 8) Hibernate Configuration.
Definition: pm.h:252
Pm::INTENSET
__IO PM_INTENSET_Type INTENSET
Offset: 0x05 (R/W 8) Interrupt Enable Set.
Definition: pm.h:248
PM_STDBYCFG_Type::RAMCFG
uint8_t RAMCFG
Definition: pm.h:152
PM_HIBCFG_Type::RAMCFG
uint8_t RAMCFG
Definition: pm.h:182
PM_HIBCFG_Type::BRAMCFG
uint8_t BRAMCFG
Definition: pm.h:183
PM_INTFLAG_Type::reg
uint8_t reg
Definition: pm.h:137
Pm::CTRLA
__IO PM_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A.
Definition: pm.h:244
PM_STDBYCFG_Type::FASTWKUP
uint8_t FASTWKUP
Definition: pm.h:154
PM_BKUPCFG_Type
Definition: pm.h:203
PM_INTFLAG_Type::uint8_t
__I uint8_t
Definition: pm.h:135
PM_INTFLAG_Type::SLEEPRDY
__I uint8_t SLEEPRDY
Definition: pm.h:134
PM_PWSAKDLY_Type::DLYVAL
uint8_t DLYVAL
Definition: pm.h:224
PM_SLEEPCFG_Type::SLEEPMODE
uint8_t SLEEPMODE
Definition: pm.h:65
PM_SLEEPCFG_Type::reg
uint8_t reg
Definition: pm.h:68
PM_BKUPCFG_Type::BRAMCFG
uint8_t BRAMCFG
Definition: pm.h:205
Pm
PM hardware registers.
Definition: pm.h:243
PM_INTENSET_Type::SLEEPRDY
uint8_t SLEEPRDY
Definition: pm.h:116
Pm::INTFLAG
__IO PM_INTFLAG_Type INTFLAG
Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear.
Definition: pm.h:249
PM_CTRLA_Type::IORET
uint8_t IORET
Definition: pm.h:47
PM_SLEEPCFG_Type
Definition: pm.h:63
PM_BKUPCFG_Type::reg
uint8_t reg
Definition: pm.h:208
Pm::STDBYCFG
__IO PM_STDBYCFG_Type STDBYCFG
Offset: 0x08 (R/W 8) Standby Configuration.
Definition: pm.h:251
PM_INTFLAG_Type
Definition: pm.h:132
PM_STDBYCFG_Type
Definition: pm.h:150
PM_INTENCLR_Type::reg
uint8_t reg
Definition: pm.h:101
Pm::BKUPCFG
__IO PM_BKUPCFG_Type BKUPCFG
Offset: 0x0A (R/W 8) Backup Configuration.
Definition: pm.h:253
PM_PWSAKDLY_Type::IGNACK
uint8_t IGNACK
Definition: pm.h:225
PM_INTENCLR_Type::SLEEPRDY
uint8_t SLEEPRDY
Definition: pm.h:98
PM_CTRLA_Type
Definition: pm.h:44
Pm::INTENCLR
__IO PM_INTENCLR_Type INTENCLR
Offset: 0x04 (R/W 8) Interrupt Enable Clear.
Definition: pm.h:247
PM_PWSAKDLY_Type
Definition: pm.h:222
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
PM_HIBCFG_Type::reg
uint8_t reg
Definition: pm.h:186
PM_HIBCFG_Type
Definition: pm.h:180
PM_INTENSET_Type::reg
uint8_t reg
Definition: pm.h:119
Pm::SLEEPCFG
__IO PM_SLEEPCFG_Type SLEEPCFG
Offset: 0x01 (R/W 8) Sleep Configuration.
Definition: pm.h:245
PM_PWSAKDLY_Type::reg
uint8_t reg
Definition: pm.h:227
Pm::PWSAKDLY
__IO PM_PWSAKDLY_Type PWSAKDLY
Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay.
Definition: pm.h:255
PM_INTENSET_Type
Definition: pm.h:114
PM_STDBYCFG_Type::reg
uint8_t reg
Definition: pm.h:157
PM_CTRLA_Type::reg
uint8_t reg
Definition: pm.h:50