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30 #ifndef _SAME54_DAC_COMPONENT_
31 #define _SAME54_DAC_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
54 #define DAC_CTRLA_OFFSET 0x00
55 #define DAC_CTRLA_RESETVALUE _U_(0x00)
57 #define DAC_CTRLA_SWRST_Pos 0
58 #define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
59 #define DAC_CTRLA_ENABLE_Pos 1
60 #define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
61 #define DAC_CTRLA_MASK _U_(0x03)
64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
75 #define DAC_CTRLB_OFFSET 0x01
76 #define DAC_CTRLB_RESETVALUE _U_(0x02)
78 #define DAC_CTRLB_DIFF_Pos 0
79 #define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos)
80 #define DAC_CTRLB_REFSEL_Pos 1
81 #define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
82 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
83 #define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0)
84 #define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1)
85 #define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2)
86 #define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3)
87 #define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos)
88 #define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos)
89 #define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos)
90 #define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos)
91 #define DAC_CTRLB_MASK _U_(0x07)
94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
116 #define DAC_EVCTRL_OFFSET 0x02
117 #define DAC_EVCTRL_RESETVALUE _U_(0x00)
119 #define DAC_EVCTRL_STARTEI0_Pos 0
120 #define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos)
121 #define DAC_EVCTRL_STARTEI1_Pos 1
122 #define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos)
123 #define DAC_EVCTRL_STARTEI_Pos 0
124 #define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos)
125 #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos))
126 #define DAC_EVCTRL_EMPTYEO0_Pos 2
127 #define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos)
128 #define DAC_EVCTRL_EMPTYEO1_Pos 3
129 #define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos)
130 #define DAC_EVCTRL_EMPTYEO_Pos 2
131 #define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos)
132 #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos))
133 #define DAC_EVCTRL_INVEI0_Pos 4
134 #define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos)
135 #define DAC_EVCTRL_INVEI1_Pos 5
136 #define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos)
137 #define DAC_EVCTRL_INVEI_Pos 4
138 #define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos)
139 #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos))
140 #define DAC_EVCTRL_RESRDYEO0_Pos 6
141 #define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos)
142 #define DAC_EVCTRL_RESRDYEO1_Pos 7
143 #define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos)
144 #define DAC_EVCTRL_RESRDYEO_Pos 6
145 #define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos)
146 #define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos))
147 #define DAC_EVCTRL_MASK _U_(0xFF)
150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
172 #define DAC_INTENCLR_OFFSET 0x04
173 #define DAC_INTENCLR_RESETVALUE _U_(0x00)
175 #define DAC_INTENCLR_UNDERRUN0_Pos 0
176 #define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos)
177 #define DAC_INTENCLR_UNDERRUN1_Pos 1
178 #define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos)
179 #define DAC_INTENCLR_UNDERRUN_Pos 0
180 #define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos)
181 #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos))
182 #define DAC_INTENCLR_EMPTY0_Pos 2
183 #define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos)
184 #define DAC_INTENCLR_EMPTY1_Pos 3
185 #define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos)
186 #define DAC_INTENCLR_EMPTY_Pos 2
187 #define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos)
188 #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos))
189 #define DAC_INTENCLR_RESRDY0_Pos 4
190 #define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos)
191 #define DAC_INTENCLR_RESRDY1_Pos 5
192 #define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos)
193 #define DAC_INTENCLR_RESRDY_Pos 4
194 #define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos)
195 #define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos))
196 #define DAC_INTENCLR_OVERRUN0_Pos 6
197 #define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos)
198 #define DAC_INTENCLR_OVERRUN1_Pos 7
199 #define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos)
200 #define DAC_INTENCLR_OVERRUN_Pos 6
201 #define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos)
202 #define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos))
203 #define DAC_INTENCLR_MASK _U_(0xFF)
206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
228 #define DAC_INTENSET_OFFSET 0x05
229 #define DAC_INTENSET_RESETVALUE _U_(0x00)
231 #define DAC_INTENSET_UNDERRUN0_Pos 0
232 #define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos)
233 #define DAC_INTENSET_UNDERRUN1_Pos 1
234 #define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos)
235 #define DAC_INTENSET_UNDERRUN_Pos 0
236 #define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos)
237 #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos))
238 #define DAC_INTENSET_EMPTY0_Pos 2
239 #define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos)
240 #define DAC_INTENSET_EMPTY1_Pos 3
241 #define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos)
242 #define DAC_INTENSET_EMPTY_Pos 2
243 #define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos)
244 #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos))
245 #define DAC_INTENSET_RESRDY0_Pos 4
246 #define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos)
247 #define DAC_INTENSET_RESRDY1_Pos 5
248 #define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos)
249 #define DAC_INTENSET_RESRDY_Pos 4
250 #define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos)
251 #define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos))
252 #define DAC_INTENSET_OVERRUN0_Pos 6
253 #define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos)
254 #define DAC_INTENSET_OVERRUN1_Pos 7
255 #define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos)
256 #define DAC_INTENSET_OVERRUN_Pos 6
257 #define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos)
258 #define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos))
259 #define DAC_INTENSET_MASK _U_(0xFF)
262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
284 #define DAC_INTFLAG_OFFSET 0x06
285 #define DAC_INTFLAG_RESETVALUE _U_(0x00)
287 #define DAC_INTFLAG_UNDERRUN0_Pos 0
288 #define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos)
289 #define DAC_INTFLAG_UNDERRUN1_Pos 1
290 #define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos)
291 #define DAC_INTFLAG_UNDERRUN_Pos 0
292 #define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos)
293 #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos))
294 #define DAC_INTFLAG_EMPTY0_Pos 2
295 #define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos)
296 #define DAC_INTFLAG_EMPTY1_Pos 3
297 #define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos)
298 #define DAC_INTFLAG_EMPTY_Pos 2
299 #define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos)
300 #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos))
301 #define DAC_INTFLAG_RESRDY0_Pos 4
302 #define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos)
303 #define DAC_INTFLAG_RESRDY1_Pos 5
304 #define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos)
305 #define DAC_INTFLAG_RESRDY_Pos 4
306 #define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos)
307 #define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos))
308 #define DAC_INTFLAG_OVERRUN0_Pos 6
309 #define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos)
310 #define DAC_INTFLAG_OVERRUN1_Pos 7
311 #define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos)
312 #define DAC_INTFLAG_OVERRUN_Pos 6
313 #define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos)
314 #define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos))
315 #define DAC_INTFLAG_MASK _U_(0xFF)
318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
336 #define DAC_STATUS_OFFSET 0x07
337 #define DAC_STATUS_RESETVALUE _U_(0x00)
339 #define DAC_STATUS_READY0_Pos 0
340 #define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos)
341 #define DAC_STATUS_READY1_Pos 1
342 #define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos)
343 #define DAC_STATUS_READY_Pos 0
344 #define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos)
345 #define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos))
346 #define DAC_STATUS_EOC0_Pos 2
347 #define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos)
348 #define DAC_STATUS_EOC1_Pos 3
349 #define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos)
350 #define DAC_STATUS_EOC_Pos 2
351 #define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos)
352 #define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos))
353 #define DAC_STATUS_MASK _U_(0x0F)
356 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
377 #define DAC_SYNCBUSY_OFFSET 0x08
378 #define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000)
380 #define DAC_SYNCBUSY_SWRST_Pos 0
381 #define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
382 #define DAC_SYNCBUSY_ENABLE_Pos 1
383 #define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
384 #define DAC_SYNCBUSY_DATA0_Pos 2
385 #define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos)
386 #define DAC_SYNCBUSY_DATA1_Pos 3
387 #define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos)
388 #define DAC_SYNCBUSY_DATA_Pos 2
389 #define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos)
390 #define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos))
391 #define DAC_SYNCBUSY_DATABUF0_Pos 4
392 #define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos)
393 #define DAC_SYNCBUSY_DATABUF1_Pos 5
394 #define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos)
395 #define DAC_SYNCBUSY_DATABUF_Pos 4
396 #define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos)
397 #define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos))
398 #define DAC_SYNCBUSY_MASK _U_(0x0000003F)
401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
419 #define DAC_DACCTRL_OFFSET 0x0C
420 #define DAC_DACCTRL_RESETVALUE _U_(0x0000)
422 #define DAC_DACCTRL_LEFTADJ_Pos 0
423 #define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos)
424 #define DAC_DACCTRL_ENABLE_Pos 1
425 #define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos)
426 #define DAC_DACCTRL_CCTRL_Pos 2
427 #define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos)
428 #define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos))
429 #define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0)
430 #define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1)
431 #define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2)
432 #define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos)
433 #define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos)
434 #define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos)
435 #define DAC_DACCTRL_FEXT_Pos 5
436 #define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos)
437 #define DAC_DACCTRL_RUNSTDBY_Pos 6
438 #define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos)
439 #define DAC_DACCTRL_DITHER_Pos 7
440 #define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos)
441 #define DAC_DACCTRL_REFRESH_Pos 8
442 #define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos)
443 #define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos))
444 #define DAC_DACCTRL_OSR_Pos 13
445 #define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos)
446 #define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos))
447 #define DAC_DACCTRL_MASK _U_(0xEFEF)
450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
459 #define DAC_DATA_OFFSET 0x10
460 #define DAC_DATA_RESETVALUE _U_(0x0000)
462 #define DAC_DATA_DATA_Pos 0
463 #define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
464 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
465 #define DAC_DATA_MASK _U_(0xFFFF)
468 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
477 #define DAC_DATABUF_OFFSET 0x14
478 #define DAC_DATABUF_RESETVALUE _U_(0x0000)
480 #define DAC_DATABUF_DATABUF_Pos 0
481 #define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
482 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
483 #define DAC_DATABUF_MASK _U_(0xFFFF)
486 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
496 #define DAC_DBGCTRL_OFFSET 0x18
497 #define DAC_DBGCTRL_RESETVALUE _U_(0x00)
499 #define DAC_DBGCTRL_DBGRUN_Pos 0
500 #define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
501 #define DAC_DBGCTRL_MASK _U_(0x01)
504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
513 #define DAC_RESULT_OFFSET 0x1C
514 #define DAC_RESULT_RESETVALUE _U_(0x0000)
516 #define DAC_RESULT_RESULT_Pos 0
517 #define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos)
518 #define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos))
519 #define DAC_RESULT_MASK _U_(0xFFFF)
522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__I DAC_STATUS_Type STATUS
Offset: 0x07 (R/ 8) Status.
__I DAC_SYNCBUSY_Type SYNCBUSY
Offset: 0x08 (R/ 32) Synchronization Busy.
__IO DAC_DBGCTRL_Type DBGCTRL
Offset: 0x18 (R/W 8) Debug Control.
__IO DAC_EVCTRL_Type EVCTRL
Offset: 0x02 (R/W 8) Event Control.
__IO DAC_CTRLB_Type CTRLB
Offset: 0x01 (R/W 8) Control B.
__IO DAC_INTENCLR_Type INTENCLR
Offset: 0x04 (R/W 8) Interrupt Enable Clear.
__IO DAC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A.
__IO DAC_INTFLAG_Type INTFLAG
Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear.
volatile const uint8_t RoReg8
__IO DAC_INTENSET_Type INTENSET
Offset: 0x05 (R/W 8) Interrupt Enable Set.