SAME54P20A Test Project
osc32kctrl.h
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1 
30 #ifndef _SAME54_OSC32KCTRL_COMPONENT_
31 #define _SAME54_OSC32KCTRL_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define OSC32KCTRL_U2400
40 #define REV_OSC32KCTRL 0x100
41 
42 /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t XOSC32KRDY:1;
47  uint32_t :1;
48  uint32_t XOSC32KFAIL:1;
49  uint32_t :29;
50  } bit;
51  uint32_t reg;
53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
54 
55 #define OSC32KCTRL_INTENCLR_OFFSET 0x00
56 #define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000)
58 #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0
59 #define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
60 #define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2
61 #define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
62 #define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005)
64 /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
65 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
66 typedef union {
67  struct {
68  uint32_t XOSC32KRDY:1;
69  uint32_t :1;
70  uint32_t XOSC32KFAIL:1;
71  uint32_t :29;
72  } bit;
73  uint32_t reg;
75 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
76 
77 #define OSC32KCTRL_INTENSET_OFFSET 0x04
78 #define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000)
80 #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0
81 #define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
82 #define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2
83 #define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
84 #define OSC32KCTRL_INTENSET_MASK _U_(0x00000005)
86 /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
88 typedef union { // __I to avoid read-modify-write on write-to-clear register
89  struct {
90  __I uint32_t XOSC32KRDY:1;
91  __I uint32_t :1;
92  __I uint32_t XOSC32KFAIL:1;
93  __I uint32_t :29;
94  } bit;
95  uint32_t reg;
97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
98 
99 #define OSC32KCTRL_INTFLAG_OFFSET 0x08
100 #define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000)
102 #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0
103 #define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
104 #define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2
105 #define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
106 #define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005)
108 /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
110 typedef union {
111  struct {
112  uint32_t XOSC32KRDY:1;
113  uint32_t :1;
114  uint32_t XOSC32KFAIL:1;
115  uint32_t XOSC32KSW:1;
116  uint32_t :28;
117  } bit;
118  uint32_t reg;
120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
121 
122 #define OSC32KCTRL_STATUS_OFFSET 0x0C
123 #define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000)
125 #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0
126 #define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
127 #define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2
128 #define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
129 #define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3
130 #define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
131 #define OSC32KCTRL_STATUS_MASK _U_(0x0000000D)
133 /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
135 typedef union {
136  struct {
137  uint8_t RTCSEL:3;
138  uint8_t :5;
139  } bit;
140  uint8_t reg;
142 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
143 
144 #define OSC32KCTRL_RTCCTRL_OFFSET 0x10
145 #define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00)
147 #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0
148 #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
149 #define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
150 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)
151 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)
152 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)
153 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)
154 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
155 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
156 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
157 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
158 #define OSC32KCTRL_RTCCTRL_MASK _U_(0x07)
160 /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
161 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
162 typedef union {
163  struct {
164  uint16_t :1;
165  uint16_t ENABLE:1;
166  uint16_t XTALEN:1;
167  uint16_t EN32K:1;
168  uint16_t EN1K:1;
169  uint16_t :1;
170  uint16_t RUNSTDBY:1;
171  uint16_t ONDEMAND:1;
172  uint16_t STARTUP:3;
173  uint16_t :1;
174  uint16_t WRTLOCK:1;
175  uint16_t CGM:2;
176  uint16_t :1;
177  } bit;
178  uint16_t reg;
180 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
181 
182 #define OSC32KCTRL_XOSC32K_OFFSET 0x14
183 #define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080)
185 #define OSC32KCTRL_XOSC32K_ENABLE_Pos 1
186 #define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
187 #define OSC32KCTRL_XOSC32K_XTALEN_Pos 2
188 #define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
189 #define OSC32KCTRL_XOSC32K_EN32K_Pos 3
190 #define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
191 #define OSC32KCTRL_XOSC32K_EN1K_Pos 4
192 #define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
193 #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6
194 #define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
195 #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7
196 #define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
197 #define OSC32KCTRL_XOSC32K_STARTUP_Pos 8
198 #define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
199 #define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
200 #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12
201 #define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
202 #define OSC32KCTRL_XOSC32K_CGM_Pos 13
203 #define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
204 #define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
205 #define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1)
206 #define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2)
207 #define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
208 #define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
209 #define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE)
211 /* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
213 typedef union {
214  struct {
215  uint8_t CFDEN:1;
216  uint8_t SWBACK:1;
217  uint8_t CFDPRESC:1;
218  uint8_t :5;
219  } bit;
220  uint8_t reg;
222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
223 
224 #define OSC32KCTRL_CFDCTRL_OFFSET 0x16
225 #define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00)
227 #define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0
228 #define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
229 #define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1
230 #define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
231 #define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2
232 #define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
233 #define OSC32KCTRL_CFDCTRL_MASK _U_(0x07)
235 /* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
236 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
237 typedef union {
238  struct {
239  uint8_t CFDEO:1;
240  uint8_t :7;
241  } bit;
242  uint8_t reg;
244 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
245 
246 #define OSC32KCTRL_EVCTRL_OFFSET 0x17
247 #define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00)
249 #define OSC32KCTRL_EVCTRL_CFDEO_Pos 0
250 #define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
251 #define OSC32KCTRL_EVCTRL_MASK _U_(0x01)
253 /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
254 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
255 typedef union {
256  struct {
257  uint32_t :1;
258  uint32_t EN32K:1;
259  uint32_t EN1K:1;
260  uint32_t :5;
261  uint32_t CALIB:6;
262  uint32_t :1;
263  uint32_t WRTLOCK:1;
264  uint32_t :16;
265  } bit;
266  uint32_t reg;
268 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
269 
270 #define OSC32KCTRL_OSCULP32K_OFFSET 0x1C
271 #define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000)
273 #define OSC32KCTRL_OSCULP32K_EN32K_Pos 1
274 #define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
275 #define OSC32KCTRL_OSCULP32K_EN1K_Pos 2
276 #define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
277 #define OSC32KCTRL_OSCULP32K_CALIB_Pos 8
278 #define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
279 #define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
280 #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15
281 #define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
282 #define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06)
285 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
286 typedef struct {
292  RoReg8 Reserved1[0x3];
296  RoReg8 Reserved2[0x4];
298 } Osc32kctrl;
299 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
300 
303 #endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
OSC32KCTRL_INTFLAG_Type::uint32_t
__I uint32_t
Definition: osc32kctrl.h:91
OSC32KCTRL_INTFLAG_Type::reg
uint32_t reg
Definition: osc32kctrl.h:95
Osc32kctrl
OSC32KCTRL hardware registers.
Definition: osc32kctrl.h:286
OSC32KCTRL_STATUS_Type
Definition: osc32kctrl.h:110
OSC32KCTRL_XOSC32K_Type::reg
uint16_t reg
Definition: osc32kctrl.h:178
OSC32KCTRL_OSCULP32K_Type::CALIB
uint32_t CALIB
Definition: osc32kctrl.h:261
OSC32KCTRL_CFDCTRL_Type::reg
uint8_t reg
Definition: osc32kctrl.h:220
OSC32KCTRL_OSCULP32K_Type::reg
uint32_t reg
Definition: osc32kctrl.h:266
OSC32KCTRL_STATUS_Type::XOSC32KSW
uint32_t XOSC32KSW
Definition: osc32kctrl.h:115
Osc32kctrl::EVCTRL
__IO OSC32KCTRL_EVCTRL_Type EVCTRL
Offset: 0x17 (R/W 8) Event Control.
Definition: osc32kctrl.h:295
OSC32KCTRL_CFDCTRL_Type::CFDPRESC
uint8_t CFDPRESC
Definition: osc32kctrl.h:217
OSC32KCTRL_INTFLAG_Type
Definition: osc32kctrl.h:88
Osc32kctrl::STATUS
__I OSC32KCTRL_STATUS_Type STATUS
Offset: 0x0C (R/ 32) Power and Clocks Status.
Definition: osc32kctrl.h:290
Osc32kctrl::CFDCTRL
__IO OSC32KCTRL_CFDCTRL_Type CFDCTRL
Offset: 0x16 (R/W 8) Clock Failure Detector Control.
Definition: osc32kctrl.h:294
OSC32KCTRL_OSCULP32K_Type
Definition: osc32kctrl.h:255
OSC32KCTRL_CFDCTRL_Type::SWBACK
uint8_t SWBACK
Definition: osc32kctrl.h:216
OSC32KCTRL_INTENSET_Type::XOSC32KFAIL
uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:70
OSC32KCTRL_INTFLAG_Type::XOSC32KRDY
__I uint32_t XOSC32KRDY
Definition: osc32kctrl.h:90
OSC32KCTRL_OSCULP32K_Type::EN32K
uint32_t EN32K
Definition: osc32kctrl.h:258
OSC32KCTRL_OSCULP32K_Type::WRTLOCK
uint32_t WRTLOCK
Definition: osc32kctrl.h:263
OSC32KCTRL_XOSC32K_Type::RUNSTDBY
uint16_t RUNSTDBY
Definition: osc32kctrl.h:170
Osc32kctrl::INTFLAG
__IO OSC32KCTRL_INTFLAG_Type INTFLAG
Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear.
Definition: osc32kctrl.h:289
OSC32KCTRL_XOSC32K_Type::STARTUP
uint16_t STARTUP
Definition: osc32kctrl.h:172
Osc32kctrl::XOSC32K
__IO OSC32KCTRL_XOSC32K_Type XOSC32K
Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control.
Definition: osc32kctrl.h:293
OSC32KCTRL_XOSC32K_Type::ONDEMAND
uint16_t ONDEMAND
Definition: osc32kctrl.h:171
OSC32KCTRL_EVCTRL_Type
Definition: osc32kctrl.h:237
Osc32kctrl::RTCCTRL
__IO OSC32KCTRL_RTCCTRL_Type RTCCTRL
Offset: 0x10 (R/W 8) RTC Clock Selection.
Definition: osc32kctrl.h:291
OSC32KCTRL_XOSC32K_Type::CGM
uint16_t CGM
Definition: osc32kctrl.h:175
OSC32KCTRL_EVCTRL_Type::CFDEO
uint8_t CFDEO
Definition: osc32kctrl.h:239
OSC32KCTRL_STATUS_Type::XOSC32KRDY
uint32_t XOSC32KRDY
Definition: osc32kctrl.h:112
OSC32KCTRL_INTFLAG_Type::XOSC32KFAIL
__I uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:92
OSC32KCTRL_INTENCLR_Type::XOSC32KRDY
uint32_t XOSC32KRDY
Definition: osc32kctrl.h:46
OSC32KCTRL_RTCCTRL_Type::RTCSEL
uint8_t RTCSEL
Definition: osc32kctrl.h:137
Osc32kctrl::OSCULP32K
__IO OSC32KCTRL_OSCULP32K_Type OSCULP32K
Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control.
Definition: osc32kctrl.h:297
OSC32KCTRL_EVCTRL_Type::reg
uint8_t reg
Definition: osc32kctrl.h:242
OSC32KCTRL_INTENSET_Type::XOSC32KRDY
uint32_t XOSC32KRDY
Definition: osc32kctrl.h:68
OSC32KCTRL_XOSC32K_Type::EN32K
uint16_t EN32K
Definition: osc32kctrl.h:167
OSC32KCTRL_CFDCTRL_Type::CFDEN
uint8_t CFDEN
Definition: osc32kctrl.h:215
OSC32KCTRL_XOSC32K_Type::EN1K
uint16_t EN1K
Definition: osc32kctrl.h:168
OSC32KCTRL_INTENCLR_Type
Definition: osc32kctrl.h:44
OSC32KCTRL_XOSC32K_Type
Definition: osc32kctrl.h:162
OSC32KCTRL_OSCULP32K_Type::EN1K
uint32_t EN1K
Definition: osc32kctrl.h:259
OSC32KCTRL_STATUS_Type::XOSC32KFAIL
uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:114
OSC32KCTRL_INTENSET_Type::reg
uint32_t reg
Definition: osc32kctrl.h:73
OSC32KCTRL_STATUS_Type::reg
uint32_t reg
Definition: osc32kctrl.h:118
OSC32KCTRL_CFDCTRL_Type
Definition: osc32kctrl.h:213
OSC32KCTRL_RTCCTRL_Type::reg
uint8_t reg
Definition: osc32kctrl.h:140
Osc32kctrl::INTENSET
__IO OSC32KCTRL_INTENSET_Type INTENSET
Offset: 0x04 (R/W 32) Interrupt Enable Set.
Definition: osc32kctrl.h:288
Osc32kctrl::INTENCLR
__IO OSC32KCTRL_INTENCLR_Type INTENCLR
Offset: 0x00 (R/W 32) Interrupt Enable Clear.
Definition: osc32kctrl.h:287
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
OSC32KCTRL_RTCCTRL_Type
Definition: osc32kctrl.h:135
OSC32KCTRL_INTENCLR_Type::XOSC32KFAIL
uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:48
OSC32KCTRL_XOSC32K_Type::XTALEN
uint16_t XTALEN
Definition: osc32kctrl.h:166
OSC32KCTRL_XOSC32K_Type::ENABLE
uint16_t ENABLE
Definition: osc32kctrl.h:165
OSC32KCTRL_XOSC32K_Type::WRTLOCK
uint16_t WRTLOCK
Definition: osc32kctrl.h:174
OSC32KCTRL_INTENSET_Type
Definition: osc32kctrl.h:66
OSC32KCTRL_INTENCLR_Type::reg
uint32_t reg
Definition: osc32kctrl.h:51