SAME54P20A Test Project
cmcc.h
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1 
30 #ifndef _SAME54_CMCC_COMPONENT_
31 #define _SAME54_CMCC_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define CMCC_U2015
40 #define REV_CMCC 0x600
41 
42 /* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t :1;
47  uint32_t GCLK:1;
48  uint32_t :2;
49  uint32_t RRP:1;
50  uint32_t WAYNUM:2;
51  uint32_t LCKDOWN:1;
52  uint32_t CSIZE:3;
53  uint32_t CLSIZE:3;
54  uint32_t :18;
55  } bit;
56  uint32_t reg;
58 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
59 
60 #define CMCC_TYPE_OFFSET 0x00
61 #define CMCC_TYPE_RESETVALUE _U_(0x000012D2)
63 #define CMCC_TYPE_GCLK_Pos 1
64 #define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
65 #define CMCC_TYPE_RRP_Pos 4
66 #define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
67 #define CMCC_TYPE_WAYNUM_Pos 5
68 #define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
69 #define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
70 #define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0)
71 #define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1)
72 #define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2)
73 #define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
74 #define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
75 #define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
76 #define CMCC_TYPE_LCKDOWN_Pos 7
77 #define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
78 #define CMCC_TYPE_CSIZE_Pos 8
79 #define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
80 #define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
81 #define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0)
82 #define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1)
83 #define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2)
84 #define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3)
85 #define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4)
86 #define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5)
87 #define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6)
88 #define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
89 #define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
90 #define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
91 #define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
92 #define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
93 #define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
94 #define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
95 #define CMCC_TYPE_CLSIZE_Pos 11
96 #define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
97 #define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
98 #define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0)
99 #define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1)
100 #define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2)
101 #define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3)
102 #define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4)
103 #define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5)
104 #define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
105 #define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
106 #define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
107 #define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
108 #define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
109 #define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
110 #define CMCC_TYPE_MASK _U_(0x00003FF2)
112 /* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
114 typedef union {
115  struct {
116  uint32_t :1;
117  uint32_t ICDIS:1;
118  uint32_t DCDIS:1;
119  uint32_t :1;
120  uint32_t CSIZESW:3;
121  uint32_t :25;
122  } bit;
123  uint32_t reg;
124 } CMCC_CFG_Type;
125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
126 
127 #define CMCC_CFG_OFFSET 0x04
128 #define CMCC_CFG_RESETVALUE _U_(0x00000020)
130 #define CMCC_CFG_ICDIS_Pos 1
131 #define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
132 #define CMCC_CFG_DCDIS_Pos 2
133 #define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
134 #define CMCC_CFG_CSIZESW_Pos 4
135 #define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
136 #define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
137 #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0)
138 #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1)
139 #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2)
140 #define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3)
141 #define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4)
142 #define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5)
143 #define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6)
144 #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
145 #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
146 #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
147 #define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
148 #define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
149 #define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
150 #define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
151 #define CMCC_CFG_MASK _U_(0x00000076)
153 /* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
154 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
155 typedef union {
156  struct {
157  uint32_t CEN:1;
158  uint32_t :31;
159  } bit;
160  uint32_t reg;
162 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
163 
164 #define CMCC_CTRL_OFFSET 0x08
165 #define CMCC_CTRL_RESETVALUE _U_(0x00000000)
167 #define CMCC_CTRL_CEN_Pos 0
168 #define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
169 #define CMCC_CTRL_MASK _U_(0x00000001)
171 /* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
173 typedef union {
174  struct {
175  uint32_t CSTS:1;
176  uint32_t :31;
177  } bit;
178  uint32_t reg;
179 } CMCC_SR_Type;
180 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
181 
182 #define CMCC_SR_OFFSET 0x0C
183 #define CMCC_SR_RESETVALUE _U_(0x00000000)
185 #define CMCC_SR_CSTS_Pos 0
186 #define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
187 #define CMCC_SR_MASK _U_(0x00000001)
189 /* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
191 typedef union {
192  struct {
193  uint32_t LCKWAY:4;
194  uint32_t :28;
195  } bit;
196  uint32_t reg;
198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
199 
200 #define CMCC_LCKWAY_OFFSET 0x10
201 #define CMCC_LCKWAY_RESETVALUE _U_(0x00000000)
203 #define CMCC_LCKWAY_LCKWAY_Pos 0
204 #define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
205 #define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
206 #define CMCC_LCKWAY_MASK _U_(0x0000000F)
208 /* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
209 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
210 typedef union {
211  struct {
212  uint32_t INVALL:1;
213  uint32_t :31;
214  } bit;
215  uint32_t reg;
217 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
218 
219 #define CMCC_MAINT0_OFFSET 0x20
220 #define CMCC_MAINT0_RESETVALUE _U_(0x00000000)
222 #define CMCC_MAINT0_INVALL_Pos 0
223 #define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
224 #define CMCC_MAINT0_MASK _U_(0x00000001)
226 /* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
228 typedef union {
229  struct {
230  uint32_t :4;
231  uint32_t INDEX:8;
232  uint32_t :16;
233  uint32_t WAY:4;
234  } bit;
235  uint32_t reg;
237 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
238 
239 #define CMCC_MAINT1_OFFSET 0x24
240 #define CMCC_MAINT1_RESETVALUE _U_(0x00000000)
242 #define CMCC_MAINT1_INDEX_Pos 4
243 #define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
244 #define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
245 #define CMCC_MAINT1_WAY_Pos 28
246 #define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
247 #define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
248 #define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0)
249 #define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1)
250 #define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2)
251 #define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3)
252 #define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
253 #define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
254 #define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
255 #define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
256 #define CMCC_MAINT1_MASK _U_(0xF0000FF0)
258 /* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
260 typedef union {
261  struct {
262  uint32_t MODE:2;
263  uint32_t :30;
264  } bit;
265  uint32_t reg;
267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
268 
269 #define CMCC_MCFG_OFFSET 0x28
270 #define CMCC_MCFG_RESETVALUE _U_(0x00000000)
272 #define CMCC_MCFG_MODE_Pos 0
273 #define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
274 #define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
275 #define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0)
276 #define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1)
277 #define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2)
278 #define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
279 #define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
280 #define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
281 #define CMCC_MCFG_MASK _U_(0x00000003)
283 /* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
285 typedef union {
286  struct {
287  uint32_t MENABLE:1;
288  uint32_t :31;
289  } bit;
290  uint32_t reg;
291 } CMCC_MEN_Type;
292 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
293 
294 #define CMCC_MEN_OFFSET 0x2C
295 #define CMCC_MEN_RESETVALUE _U_(0x00000000)
297 #define CMCC_MEN_MENABLE_Pos 0
298 #define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
299 #define CMCC_MEN_MASK _U_(0x00000001)
301 /* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
302 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
303 typedef union {
304  struct {
305  uint32_t SWRST:1;
306  uint32_t :31;
307  } bit;
308  uint32_t reg;
310 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
311 
312 #define CMCC_MCTRL_OFFSET 0x30
313 #define CMCC_MCTRL_RESETVALUE _U_(0x00000000)
315 #define CMCC_MCTRL_SWRST_Pos 0
316 #define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
317 #define CMCC_MCTRL_MASK _U_(0x00000001)
319 /* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
320 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
321 typedef union {
322  struct {
323  uint32_t EVENT_CNT:32;
324  } bit;
325  uint32_t reg;
326 } CMCC_MSR_Type;
327 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
328 
329 #define CMCC_MSR_OFFSET 0x34
330 #define CMCC_MSR_RESETVALUE _U_(0x00000000)
332 #define CMCC_MSR_EVENT_CNT_Pos 0
333 #define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
334 #define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
335 #define CMCC_MSR_MASK _U_(0xFFFFFFFF)
338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
339 typedef struct {
345  RoReg8 Reserved1[0xC];
352 } Cmcc;
353 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
354 
357 #endif /* _SAME54_CMCC_COMPONENT_ */
Cmcc::MCFG
__IO CMCC_MCFG_Type MCFG
Offset: 0x28 (R/W 32) Cache Monitor Configuration Register.
Definition: cmcc.h:348
Cmcc::TYPE
__I CMCC_TYPE_Type TYPE
Offset: 0x00 (R/ 32) Cache Type Register.
Definition: cmcc.h:340
CMCC_MAINT0_Type::reg
uint32_t reg
Definition: cmcc.h:215
CMCC_MAINT1_Type::INDEX
uint32_t INDEX
Definition: cmcc.h:231
CMCC_TYPE_Type::WAYNUM
uint32_t WAYNUM
Definition: cmcc.h:50
CMCC_MEN_Type
Definition: cmcc.h:285
CMCC_TYPE_Type
Definition: cmcc.h:44
CMCC_SR_Type
Definition: cmcc.h:173
CMCC_MCTRL_Type::SWRST
uint32_t SWRST
Definition: cmcc.h:305
CMCC_CFG_Type::CSIZESW
uint32_t CSIZESW
Definition: cmcc.h:120
Cmcc::CFG
__IO CMCC_CFG_Type CFG
Offset: 0x04 (R/W 32) Cache Configuration Register.
Definition: cmcc.h:341
CMCC_MEN_Type::reg
uint32_t reg
Definition: cmcc.h:290
Cmcc::MAINT0
__O CMCC_MAINT0_Type MAINT0
Offset: 0x20 ( /W 32) Cache Maintenance Register 0.
Definition: cmcc.h:346
CMCC_MSR_Type
Definition: cmcc.h:321
CMCC_CTRL_Type::CEN
uint32_t CEN
Definition: cmcc.h:157
CMCC_TYPE_Type::CLSIZE
uint32_t CLSIZE
Definition: cmcc.h:53
Cmcc::MAINT1
__O CMCC_MAINT1_Type MAINT1
Offset: 0x24 ( /W 32) Cache Maintenance Register 1.
Definition: cmcc.h:347
CMCC_CFG_Type::DCDIS
uint32_t DCDIS
Definition: cmcc.h:118
Cmcc::CTRL
__O CMCC_CTRL_Type CTRL
Offset: 0x08 ( /W 32) Cache Control Register.
Definition: cmcc.h:342
CMCC_MSR_Type::reg
uint32_t reg
Definition: cmcc.h:325
CMCC_LCKWAY_Type
Definition: cmcc.h:191
Cmcc::MSR
__I CMCC_MSR_Type MSR
Offset: 0x34 (R/ 32) Cache Monitor Status Register.
Definition: cmcc.h:351
CMCC_MCTRL_Type::reg
uint32_t reg
Definition: cmcc.h:308
CMCC_CFG_Type::ICDIS
uint32_t ICDIS
Definition: cmcc.h:117
Cmcc::MCTRL
__O CMCC_MCTRL_Type MCTRL
Offset: 0x30 ( /W 32) Cache Monitor Control Register.
Definition: cmcc.h:350
CMCC_MSR_Type::EVENT_CNT
uint32_t EVENT_CNT
Definition: cmcc.h:323
CMCC_SR_Type::CSTS
uint32_t CSTS
Definition: cmcc.h:175
Cmcc::SR
__I CMCC_SR_Type SR
Offset: 0x0C (R/ 32) Cache Status Register.
Definition: cmcc.h:343
CMCC_CFG_Type::reg
uint32_t reg
Definition: cmcc.h:123
CMCC_MAINT0_Type
Definition: cmcc.h:210
Cmcc
CMCC APB hardware registers.
Definition: cmcc.h:339
CMCC_CTRL_Type
Definition: cmcc.h:155
CMCC_TYPE_Type::CSIZE
uint32_t CSIZE
Definition: cmcc.h:52
CMCC_CFG_Type
Definition: cmcc.h:114
CMCC_LCKWAY_Type::LCKWAY
uint32_t LCKWAY
Definition: cmcc.h:193
CMCC_LCKWAY_Type::reg
uint32_t reg
Definition: cmcc.h:196
CMCC_SR_Type::reg
uint32_t reg
Definition: cmcc.h:178
CMCC_TYPE_Type::GCLK
uint32_t GCLK
Definition: cmcc.h:47
CMCC_MAINT0_Type::INVALL
uint32_t INVALL
Definition: cmcc.h:212
Cmcc::LCKWAY
__IO CMCC_LCKWAY_Type LCKWAY
Offset: 0x10 (R/W 32) Cache Lock per Way Register.
Definition: cmcc.h:344
CMCC_MAINT1_Type
Definition: cmcc.h:228
CMCC_TYPE_Type::RRP
uint32_t RRP
Definition: cmcc.h:49
CMCC_TYPE_Type::LCKDOWN
uint32_t LCKDOWN
Definition: cmcc.h:51
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
CMCC_MAINT1_Type::WAY
uint32_t WAY
Definition: cmcc.h:233
Cmcc::MEN
__IO CMCC_MEN_Type MEN
Offset: 0x2C (R/W 32) Cache Monitor Enable Register.
Definition: cmcc.h:349
CMCC_MCFG_Type::reg
uint32_t reg
Definition: cmcc.h:265
CMCC_MAINT1_Type::reg
uint32_t reg
Definition: cmcc.h:235
CMCC_CTRL_Type::reg
uint32_t reg
Definition: cmcc.h:160
CMCC_TYPE_Type::reg
uint32_t reg
Definition: cmcc.h:56
CMCC_MCFG_Type::MODE
uint32_t MODE
Definition: cmcc.h:262
CMCC_MCTRL_Type
Definition: cmcc.h:303
CMCC_MEN_Type::MENABLE
uint32_t MENABLE
Definition: cmcc.h:287
CMCC_MCFG_Type
Definition: cmcc.h:260