SAME54P20A Test Project
ramecc.h
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1 
30 #ifndef _SAME54_RAMECC_COMPONENT_
31 #define _SAME54_RAMECC_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define RAMECC_U2268
40 #define REV_RAMECC 0x100
41 
42 /* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t SINGLEE:1;
47  uint8_t DUALE:1;
48  uint8_t :6;
49  } bit;
50  uint8_t reg;
52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
53 
54 #define RAMECC_INTENCLR_OFFSET 0x0
55 #define RAMECC_INTENCLR_RESETVALUE _U_(0x00)
57 #define RAMECC_INTENCLR_SINGLEE_Pos 0
58 #define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
59 #define RAMECC_INTENCLR_DUALE_Pos 1
60 #define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
61 #define RAMECC_INTENCLR_MASK _U_(0x03)
63 /* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */
64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
65 typedef union {
66  struct {
67  uint8_t SINGLEE:1;
68  uint8_t DUALE:1;
69  uint8_t :6;
70  } bit;
71  uint8_t reg;
73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
74 
75 #define RAMECC_INTENSET_OFFSET 0x1
76 #define RAMECC_INTENSET_RESETVALUE _U_(0x00)
78 #define RAMECC_INTENSET_SINGLEE_Pos 0
79 #define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
80 #define RAMECC_INTENSET_DUALE_Pos 1
81 #define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
82 #define RAMECC_INTENSET_MASK _U_(0x03)
84 /* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */
85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
86 typedef union { // __I to avoid read-modify-write on write-to-clear register
87  struct {
88  __I uint8_t SINGLEE:1;
89  __I uint8_t DUALE:1;
90  __I uint8_t :6;
91  } bit;
92  uint8_t reg;
94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
95 
96 #define RAMECC_INTFLAG_OFFSET 0x2
97 #define RAMECC_INTFLAG_RESETVALUE _U_(0x00)
99 #define RAMECC_INTFLAG_SINGLEE_Pos 0
100 #define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
101 #define RAMECC_INTFLAG_DUALE_Pos 1
102 #define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
103 #define RAMECC_INTFLAG_MASK _U_(0x03)
105 /* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */
106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
107 typedef union {
108  struct {
109  uint8_t ECCDIS:1;
110  uint8_t :7;
111  } bit;
112  uint8_t reg;
114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
115 
116 #define RAMECC_STATUS_OFFSET 0x3
117 #define RAMECC_STATUS_RESETVALUE _U_(0x00)
119 #define RAMECC_STATUS_ECCDIS_Pos 0
120 #define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
121 #define RAMECC_STATUS_MASK _U_(0x01)
123 /* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */
124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
125 typedef union {
126  struct {
127  uint32_t ERRADDR:17;
128  uint32_t :15;
129  } bit;
130  uint32_t reg;
132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
133 
134 #define RAMECC_ERRADDR_OFFSET 0x4
135 #define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000)
137 #define RAMECC_ERRADDR_ERRADDR_Pos 0
138 #define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
139 #define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
140 #define RAMECC_ERRADDR_MASK _U_(0x0001FFFF)
142 /* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */
143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
144 typedef union {
145  struct {
146  uint8_t ECCDIS:1;
147  uint8_t ECCELOG:1;
148  uint8_t :6;
149  } bit;
150  uint8_t reg;
152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
153 
154 #define RAMECC_DBGCTRL_OFFSET 0xF
155 #define RAMECC_DBGCTRL_RESETVALUE _U_(0x00)
157 #define RAMECC_DBGCTRL_ECCDIS_Pos 0
158 #define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
159 #define RAMECC_DBGCTRL_ECCELOG_Pos 1
160 #define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
161 #define RAMECC_DBGCTRL_MASK _U_(0x03)
164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
165 typedef struct {
171  RoReg8 Reserved1[0x7];
173 } Ramecc;
174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
175 
178 #endif /* _SAME54_RAMECC_COMPONENT_ */
RAMECC_DBGCTRL_Type::ECCDIS
uint8_t ECCDIS
Definition: ramecc.h:146
Ramecc::STATUS
__I RAMECC_STATUS_Type STATUS
Offset: 0x3 (R/ 8) Status.
Definition: ramecc.h:169
RAMECC_INTFLAG_Type::reg
uint8_t reg
Definition: ramecc.h:92
RAMECC_STATUS_Type::ECCDIS
uint8_t ECCDIS
Definition: ramecc.h:109
RAMECC_INTENSET_Type::reg
uint8_t reg
Definition: ramecc.h:71
RAMECC_INTFLAG_Type::SINGLEE
__I uint8_t SINGLEE
Definition: ramecc.h:88
Ramecc
RAMECC hardware registers.
Definition: ramecc.h:165
Ramecc::ERRADDR
__I RAMECC_ERRADDR_Type ERRADDR
Offset: 0x4 (R/ 32) Error Address.
Definition: ramecc.h:170
RAMECC_STATUS_Type::reg
uint8_t reg
Definition: ramecc.h:112
RAMECC_INTENSET_Type::SINGLEE
uint8_t SINGLEE
Definition: ramecc.h:67
RAMECC_ERRADDR_Type::reg
uint32_t reg
Definition: ramecc.h:130
RAMECC_INTFLAG_Type::uint8_t
__I uint8_t
Definition: ramecc.h:90
RAMECC_INTENCLR_Type::SINGLEE
uint8_t SINGLEE
Definition: ramecc.h:46
RAMECC_INTENCLR_Type
Definition: ramecc.h:44
RAMECC_DBGCTRL_Type::reg
uint8_t reg
Definition: ramecc.h:150
RAMECC_ERRADDR_Type::ERRADDR
uint32_t ERRADDR
Definition: ramecc.h:127
RAMECC_DBGCTRL_Type
Definition: ramecc.h:144
RAMECC_INTENSET_Type::DUALE
uint8_t DUALE
Definition: ramecc.h:68
RAMECC_STATUS_Type
Definition: ramecc.h:107
RAMECC_INTENSET_Type
Definition: ramecc.h:65
Ramecc::DBGCTRL
__IO RAMECC_DBGCTRL_Type DBGCTRL
Offset: 0xF (R/W 8) Debug Control.
Definition: ramecc.h:172
Ramecc::INTENSET
__IO RAMECC_INTENSET_Type INTENSET
Offset: 0x1 (R/W 8) Interrupt Enable Set.
Definition: ramecc.h:167
RAMECC_INTFLAG_Type::DUALE
__I uint8_t DUALE
Definition: ramecc.h:89
Ramecc::INTENCLR
__IO RAMECC_INTENCLR_Type INTENCLR
Offset: 0x0 (R/W 8) Interrupt Enable Clear.
Definition: ramecc.h:166
RAMECC_DBGCTRL_Type::ECCELOG
uint8_t ECCELOG
Definition: ramecc.h:147
RAMECC_INTENCLR_Type::DUALE
uint8_t DUALE
Definition: ramecc.h:47
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
RAMECC_INTENCLR_Type::reg
uint8_t reg
Definition: ramecc.h:50
RAMECC_INTFLAG_Type
Definition: ramecc.h:86
Ramecc::INTFLAG
__IO RAMECC_INTFLAG_Type INTFLAG
Offset: 0x2 (R/W 8) Interrupt Flag.
Definition: ramecc.h:168
RAMECC_ERRADDR_Type
Definition: ramecc.h:125