SAME54P20A Test Project
pcc.h
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1 
30 #ifndef _SAME54_PCC_COMPONENT_
31 #define _SAME54_PCC_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define PCC_U2017
40 #define REV_PCC 0x110
41 
42 /* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t PCEN:1;
47  uint32_t :3;
48  uint32_t DSIZE:2;
49  uint32_t :2;
50  uint32_t SCALE:1;
51  uint32_t ALWYS:1;
52  uint32_t HALFS:1;
53  uint32_t FRSTS:1;
54  uint32_t :4;
55  uint32_t ISIZE:3;
56  uint32_t :11;
57  uint32_t CID:2;
58  } bit;
59  uint32_t reg;
60 } PCC_MR_Type;
61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
62 
63 #define PCC_MR_OFFSET 0x00
64 #define PCC_MR_RESETVALUE _U_(0x00000000)
66 #define PCC_MR_PCEN_Pos 0
67 #define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
68 #define PCC_MR_DSIZE_Pos 4
69 #define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
70 #define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
71 #define PCC_MR_SCALE_Pos 8
72 #define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
73 #define PCC_MR_ALWYS_Pos 9
74 #define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
75 #define PCC_MR_HALFS_Pos 10
76 #define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
77 #define PCC_MR_FRSTS_Pos 11
78 #define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
79 #define PCC_MR_ISIZE_Pos 16
80 #define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
81 #define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
82 #define PCC_MR_CID_Pos 30
83 #define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
84 #define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
85 #define PCC_MR_MASK _U_(0xC0070F31)
87 /* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */
88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
89 typedef union {
90  struct {
91  uint32_t DRDY:1;
92  uint32_t OVRE:1;
93  uint32_t :30;
94  } bit;
95  uint32_t reg;
96 } PCC_IER_Type;
97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
98 
99 #define PCC_IER_OFFSET 0x04
100 #define PCC_IER_RESETVALUE _U_(0x00000000)
102 #define PCC_IER_DRDY_Pos 0
103 #define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
104 #define PCC_IER_OVRE_Pos 1
105 #define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
106 #define PCC_IER_MASK _U_(0x00000003)
108 /* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */
109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
110 typedef union {
111  struct {
112  uint32_t DRDY:1;
113  uint32_t OVRE:1;
114  uint32_t :30;
115  } bit;
116  uint32_t reg;
117 } PCC_IDR_Type;
118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
119 
120 #define PCC_IDR_OFFSET 0x08
121 #define PCC_IDR_RESETVALUE _U_(0x00000000)
123 #define PCC_IDR_DRDY_Pos 0
124 #define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
125 #define PCC_IDR_OVRE_Pos 1
126 #define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
127 #define PCC_IDR_MASK _U_(0x00000003)
129 /* -------- PCC_IMR : (PCC Offset: 0x0C) (R/ 32) Interrupt Mask Register -------- */
130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
131 typedef union {
132  struct {
133  uint32_t DRDY:1;
134  uint32_t OVRE:1;
135  uint32_t :30;
136  } bit;
137  uint32_t reg;
138 } PCC_IMR_Type;
139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
140 
141 #define PCC_IMR_OFFSET 0x0C
142 #define PCC_IMR_RESETVALUE _U_(0x00000000)
144 #define PCC_IMR_DRDY_Pos 0
145 #define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
146 #define PCC_IMR_OVRE_Pos 1
147 #define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
148 #define PCC_IMR_MASK _U_(0x00000003)
150 /* -------- PCC_ISR : (PCC Offset: 0x10) (R/ 32) Interrupt Status Register -------- */
151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
152 typedef union {
153  struct {
154  uint32_t DRDY:1;
155  uint32_t OVRE:1;
156  uint32_t :30;
157  } bit;
158  uint32_t reg;
159 } PCC_ISR_Type;
160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
161 
162 #define PCC_ISR_OFFSET 0x10
163 #define PCC_ISR_RESETVALUE _U_(0x00000000)
165 #define PCC_ISR_DRDY_Pos 0
166 #define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
167 #define PCC_ISR_OVRE_Pos 1
168 #define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
169 #define PCC_ISR_MASK _U_(0x00000003)
171 /* -------- PCC_RHR : (PCC Offset: 0x14) (R/ 32) Reception Holding Register -------- */
172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
173 typedef union {
174  struct {
175  uint32_t RDATA:32;
176  } bit;
177  uint32_t reg;
178 } PCC_RHR_Type;
179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
180 
181 #define PCC_RHR_OFFSET 0x14
182 #define PCC_RHR_RESETVALUE _U_(0x00000000)
184 #define PCC_RHR_RDATA_Pos 0
185 #define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
186 #define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
187 #define PCC_RHR_MASK _U_(0xFFFFFFFF)
189 /* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */
190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
191 typedef union {
192  struct {
193  uint32_t WPEN:1;
194  uint32_t :7;
195  uint32_t WPKEY:24;
196  } bit;
197  uint32_t reg;
198 } PCC_WPMR_Type;
199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
200 
201 #define PCC_WPMR_OFFSET 0xE0
202 #define PCC_WPMR_RESETVALUE _U_(0x00000000)
204 #define PCC_WPMR_WPEN_Pos 0
205 #define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
206 #define PCC_WPMR_WPKEY_Pos 8
207 #define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
208 #define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
209 #define PCC_WPMR_MASK _U_(0xFFFFFF01)
211 /* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/ 32) Write Protection Status Register -------- */
212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
213 typedef union {
214  struct {
215  uint32_t WPVS:1;
216  uint32_t :7;
217  uint32_t WPVSRC:16;
218  uint32_t :8;
219  } bit;
220  uint32_t reg;
221 } PCC_WPSR_Type;
222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
223 
224 #define PCC_WPSR_OFFSET 0xE4
225 #define PCC_WPSR_RESETVALUE _U_(0x00000000)
227 #define PCC_WPSR_WPVS_Pos 0
228 #define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
229 #define PCC_WPSR_WPVSRC_Pos 8
230 #define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
231 #define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
232 #define PCC_WPSR_MASK _U_(0x00FFFF01)
235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
236 typedef struct {
243  RoReg8 Reserved1[0xC8];
246 } Pcc;
247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
248 
251 #endif /* _SAME54_PCC_COMPONENT_ */
Pcc::IMR
__I PCC_IMR_Type IMR
Offset: 0x0C (R/ 32) Interrupt Mask Register.
Definition: pcc.h:240
PCC_RHR_Type::RDATA
uint32_t RDATA
Definition: pcc.h:175
PCC_MR_Type::reg
uint32_t reg
Definition: pcc.h:59
PCC_WPMR_Type::reg
uint32_t reg
Definition: pcc.h:197
PCC_IER_Type::reg
uint32_t reg
Definition: pcc.h:95
PCC_MR_Type::ISIZE
uint32_t ISIZE
Definition: pcc.h:55
Pcc::MR
__IO PCC_MR_Type MR
Offset: 0x00 (R/W 32) Mode Register.
Definition: pcc.h:237
PCC_IMR_Type
Definition: pcc.h:131
PCC_WPSR_Type::WPVS
uint32_t WPVS
Definition: pcc.h:215
Pcc::RHR
__I PCC_RHR_Type RHR
Offset: 0x14 (R/ 32) Reception Holding Register.
Definition: pcc.h:242
PCC_WPSR_Type
Definition: pcc.h:213
PCC_IMR_Type::DRDY
uint32_t DRDY
Definition: pcc.h:133
PCC_IMR_Type::reg
uint32_t reg
Definition: pcc.h:137
PCC_MR_Type::HALFS
uint32_t HALFS
Definition: pcc.h:52
PCC_WPMR_Type::WPEN
uint32_t WPEN
Definition: pcc.h:193
Pcc::IER
__O PCC_IER_Type IER
Offset: 0x04 ( /W 32) Interrupt Enable Register.
Definition: pcc.h:238
PCC_IER_Type::OVRE
uint32_t OVRE
Definition: pcc.h:92
PCC_IDR_Type
Definition: pcc.h:110
PCC_MR_Type::FRSTS
uint32_t FRSTS
Definition: pcc.h:53
Pcc::WPMR
__IO PCC_WPMR_Type WPMR
Offset: 0xE0 (R/W 32) Write Protection Mode Register.
Definition: pcc.h:244
PCC_WPSR_Type::reg
uint32_t reg
Definition: pcc.h:220
PCC_RHR_Type
Definition: pcc.h:173
PCC_IDR_Type::DRDY
uint32_t DRDY
Definition: pcc.h:112
PCC_ISR_Type::reg
uint32_t reg
Definition: pcc.h:158
PCC_IER_Type::DRDY
uint32_t DRDY
Definition: pcc.h:91
PCC_IDR_Type::reg
uint32_t reg
Definition: pcc.h:116
PCC_IDR_Type::OVRE
uint32_t OVRE
Definition: pcc.h:113
PCC_ISR_Type::DRDY
uint32_t DRDY
Definition: pcc.h:154
PCC_MR_Type::SCALE
uint32_t SCALE
Definition: pcc.h:50
Pcc::WPSR
__I PCC_WPSR_Type WPSR
Offset: 0xE4 (R/ 32) Write Protection Status Register.
Definition: pcc.h:245
PCC_MR_Type::PCEN
uint32_t PCEN
Definition: pcc.h:46
PCC_MR_Type
Definition: pcc.h:44
PCC_WPMR_Type
Definition: pcc.h:191
PCC_MR_Type::ALWYS
uint32_t ALWYS
Definition: pcc.h:51
PCC_MR_Type::DSIZE
uint32_t DSIZE
Definition: pcc.h:48
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
PCC_ISR_Type::OVRE
uint32_t OVRE
Definition: pcc.h:155
PCC_RHR_Type::reg
uint32_t reg
Definition: pcc.h:177
PCC_IER_Type
Definition: pcc.h:89
PCC_WPMR_Type::WPKEY
uint32_t WPKEY
Definition: pcc.h:195
Pcc
PCC hardware registers.
Definition: pcc.h:236
PCC_WPSR_Type::WPVSRC
uint32_t WPVSRC
Definition: pcc.h:217
PCC_IMR_Type::OVRE
uint32_t OVRE
Definition: pcc.h:134
PCC_ISR_Type
Definition: pcc.h:152
PCC_MR_Type::CID
uint32_t CID
Definition: pcc.h:57
Pcc::ISR
__I PCC_ISR_Type ISR
Offset: 0x10 (R/ 32) Interrupt Status Register.
Definition: pcc.h:241
Pcc::IDR
__O PCC_IDR_Type IDR
Offset: 0x08 ( /W 32) Interrupt Disable Register.
Definition: pcc.h:239