Go to the documentation of this file.
30 #ifndef _SAME54_PM_COMPONENT_
31 #define _SAME54_PM_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
54 #define PM_CTRLA_OFFSET 0x00
55 #define PM_CTRLA_RESETVALUE _U_(0x00)
57 #define PM_CTRLA_IORET_Pos 2
58 #define PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)
59 #define PM_CTRLA_MASK _U_(0x04)
62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
72 #define PM_SLEEPCFG_OFFSET 0x01
73 #define PM_SLEEPCFG_RESETVALUE _U_(0x02)
75 #define PM_SLEEPCFG_SLEEPMODE_Pos 0
76 #define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
77 #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
78 #define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0)
79 #define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1)
80 #define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2)
81 #define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4)
82 #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5)
83 #define PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6)
84 #define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7)
85 #define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
86 #define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
87 #define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
88 #define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
89 #define PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
90 #define PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
91 #define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
92 #define PM_SLEEPCFG_MASK _U_(0x07)
95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
105 #define PM_INTENCLR_OFFSET 0x04
106 #define PM_INTENCLR_RESETVALUE _U_(0x00)
108 #define PM_INTENCLR_SLEEPRDY_Pos 0
109 #define PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)
110 #define PM_INTENCLR_MASK _U_(0x01)
113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
123 #define PM_INTENSET_OFFSET 0x05
124 #define PM_INTENSET_RESETVALUE _U_(0x00)
126 #define PM_INTENSET_SLEEPRDY_Pos 0
127 #define PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)
128 #define PM_INTENSET_MASK _U_(0x01)
131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
141 #define PM_INTFLAG_OFFSET 0x06
142 #define PM_INTFLAG_RESETVALUE _U_(0x00)
144 #define PM_INTFLAG_SLEEPRDY_Pos 0
145 #define PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)
146 #define PM_INTFLAG_MASK _U_(0x01)
149 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
161 #define PM_STDBYCFG_OFFSET 0x08
162 #define PM_STDBYCFG_RESETVALUE _U_(0x00)
164 #define PM_STDBYCFG_RAMCFG_Pos 0
165 #define PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)
166 #define PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))
167 #define PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0)
168 #define PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1)
169 #define PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2)
170 #define PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)
171 #define PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)
172 #define PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)
173 #define PM_STDBYCFG_FASTWKUP_Pos 4
174 #define PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)
175 #define PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))
176 #define PM_STDBYCFG_MASK _U_(0x33)
179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
190 #define PM_HIBCFG_OFFSET 0x09
191 #define PM_HIBCFG_RESETVALUE _U_(0x00)
193 #define PM_HIBCFG_RAMCFG_Pos 0
194 #define PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)
195 #define PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))
196 #define PM_HIBCFG_BRAMCFG_Pos 2
197 #define PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)
198 #define PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))
199 #define PM_HIBCFG_MASK _U_(0x0F)
202 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
212 #define PM_BKUPCFG_OFFSET 0x0A
213 #define PM_BKUPCFG_RESETVALUE _U_(0x00)
215 #define PM_BKUPCFG_BRAMCFG_Pos 0
216 #define PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)
217 #define PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))
218 #define PM_BKUPCFG_MASK _U_(0x03)
221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
231 #define PM_PWSAKDLY_OFFSET 0x12
232 #define PM_PWSAKDLY_RESETVALUE _U_(0x00)
234 #define PM_PWSAKDLY_DLYVAL_Pos 0
235 #define PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)
236 #define PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))
237 #define PM_PWSAKDLY_IGNACK_Pos 7
238 #define PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)
239 #define PM_PWSAKDLY_MASK _U_(0xFF)
242 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO PM_HIBCFG_Type HIBCFG
Offset: 0x09 (R/W 8) Hibernate Configuration.
__IO PM_INTENSET_Type INTENSET
Offset: 0x05 (R/W 8) Interrupt Enable Set.
__IO PM_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A.
__IO PM_INTFLAG_Type INTFLAG
Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear.
__IO PM_STDBYCFG_Type STDBYCFG
Offset: 0x08 (R/W 8) Standby Configuration.
__IO PM_BKUPCFG_Type BKUPCFG
Offset: 0x0A (R/W 8) Backup Configuration.
__IO PM_INTENCLR_Type INTENCLR
Offset: 0x04 (R/W 8) Interrupt Enable Clear.
volatile const uint8_t RoReg8
__IO PM_SLEEPCFG_Type SLEEPCFG
Offset: 0x01 (R/W 8) Sleep Configuration.
__IO PM_PWSAKDLY_Type PWSAKDLY
Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay.