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30 #ifndef _SAME54_FREQM_COMPONENT_
31 #define _SAME54_FREQM_COMPONENT_
40 #define REV_FREQM 0x110
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
54 #define FREQM_CTRLA_OFFSET 0x00
55 #define FREQM_CTRLA_RESETVALUE _U_(0x00)
57 #define FREQM_CTRLA_SWRST_Pos 0
58 #define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
59 #define FREQM_CTRLA_ENABLE_Pos 1
60 #define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
61 #define FREQM_CTRLA_MASK _U_(0x03)
64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
74 #define FREQM_CTRLB_OFFSET 0x01
75 #define FREQM_CTRLB_RESETVALUE _U_(0x00)
77 #define FREQM_CTRLB_START_Pos 0
78 #define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
79 #define FREQM_CTRLB_MASK _U_(0x01)
82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
92 #define FREQM_CFGA_OFFSET 0x02
93 #define FREQM_CFGA_RESETVALUE _U_(0x0000)
95 #define FREQM_CFGA_REFNUM_Pos 0
96 #define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
97 #define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
98 #define FREQM_CFGA_MASK _U_(0x00FF)
101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
111 #define FREQM_INTENCLR_OFFSET 0x08
112 #define FREQM_INTENCLR_RESETVALUE _U_(0x00)
114 #define FREQM_INTENCLR_DONE_Pos 0
115 #define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
116 #define FREQM_INTENCLR_MASK _U_(0x01)
119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
129 #define FREQM_INTENSET_OFFSET 0x09
130 #define FREQM_INTENSET_RESETVALUE _U_(0x00)
132 #define FREQM_INTENSET_DONE_Pos 0
133 #define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
134 #define FREQM_INTENSET_MASK _U_(0x01)
137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
147 #define FREQM_INTFLAG_OFFSET 0x0A
148 #define FREQM_INTFLAG_RESETVALUE _U_(0x00)
150 #define FREQM_INTFLAG_DONE_Pos 0
151 #define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
152 #define FREQM_INTFLAG_MASK _U_(0x01)
155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
166 #define FREQM_STATUS_OFFSET 0x0B
167 #define FREQM_STATUS_RESETVALUE _U_(0x00)
169 #define FREQM_STATUS_BUSY_Pos 0
170 #define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
171 #define FREQM_STATUS_OVF_Pos 1
172 #define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
173 #define FREQM_STATUS_MASK _U_(0x03)
176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
187 #define FREQM_SYNCBUSY_OFFSET 0x0C
188 #define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000)
190 #define FREQM_SYNCBUSY_SWRST_Pos 0
191 #define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
192 #define FREQM_SYNCBUSY_ENABLE_Pos 1
193 #define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
194 #define FREQM_SYNCBUSY_MASK _U_(0x00000003)
197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
207 #define FREQM_VALUE_OFFSET 0x10
208 #define FREQM_VALUE_RESETVALUE _U_(0x00000000)
210 #define FREQM_VALUE_VALUE_Pos 0
211 #define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
212 #define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
213 #define FREQM_VALUE_MASK _U_(0x00FFFFFF)
216 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO FREQM_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status Register.
__IO FREQM_CFGA_Type CFGA
Offset: 0x02 (R/W 16) Config A register.
__I FREQM_VALUE_Type VALUE
Offset: 0x10 (R/ 32) Count Value Register.
FREQM hardware registers.
__IO FREQM_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set Register.
__I FREQM_SYNCBUSY_Type SYNCBUSY
Offset: 0x0C (R/ 32) Synchronization Busy Register.
__IO FREQM_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear Register.
__O FREQM_CTRLB_Type CTRLB
Offset: 0x01 ( /W 8) Control B Register.
__IO FREQM_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Register.
volatile const uint8_t RoReg8
__IO FREQM_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A Register.