SAME54P20A Test Project
oscctrl.h
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1 
30 #ifndef _SAME54_OSCCTRL_COMPONENT_
31 #define _SAME54_OSCCTRL_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define OSCCTRL_U2401
40 #define REV_OSCCTRL 0x100
41 
42 /* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint8_t CFDEO0:1;
47  uint8_t CFDEO1:1;
48  uint8_t :6;
49  } bit;
50  struct {
51  uint8_t CFDEO:2;
52  uint8_t :6;
53  } vec;
54  uint8_t reg;
56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
57 
58 #define OSCCTRL_EVCTRL_OFFSET 0x00
59 #define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00)
61 #define OSCCTRL_EVCTRL_CFDEO0_Pos 0
62 #define OSCCTRL_EVCTRL_CFDEO0 (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos)
63 #define OSCCTRL_EVCTRL_CFDEO1_Pos 1
64 #define OSCCTRL_EVCTRL_CFDEO1 (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos)
65 #define OSCCTRL_EVCTRL_CFDEO_Pos 0
66 #define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos)
67 #define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos))
68 #define OSCCTRL_EVCTRL_MASK _U_(0x03)
70 /* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */
71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
72 typedef union {
73  struct {
74  uint32_t XOSCRDY0:1;
75  uint32_t XOSCRDY1:1;
76  uint32_t XOSCFAIL0:1;
77  uint32_t XOSCFAIL1:1;
78  uint32_t :4;
79  uint32_t DFLLRDY:1;
80  uint32_t DFLLOOB:1;
81  uint32_t DFLLLCKF:1;
82  uint32_t DFLLLCKC:1;
83  uint32_t DFLLRCS:1;
84  uint32_t :3;
85  uint32_t DPLL0LCKR:1;
86  uint32_t DPLL0LCKF:1;
87  uint32_t DPLL0LTO:1;
88  uint32_t DPLL0LDRTO:1;
89  uint32_t :4;
90  uint32_t DPLL1LCKR:1;
91  uint32_t DPLL1LCKF:1;
92  uint32_t DPLL1LTO:1;
93  uint32_t DPLL1LDRTO:1;
94  uint32_t :4;
95  } bit;
96  struct {
97  uint32_t XOSCRDY:2;
98  uint32_t XOSCFAIL:2;
99  uint32_t :28;
100  } vec;
101  uint32_t reg;
103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
104 
105 #define OSCCTRL_INTENCLR_OFFSET 0x04
106 #define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000)
108 #define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0
109 #define OSCCTRL_INTENCLR_XOSCRDY0 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos)
110 #define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1
111 #define OSCCTRL_INTENCLR_XOSCRDY1 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos)
112 #define OSCCTRL_INTENCLR_XOSCRDY_Pos 0
113 #define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
114 #define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos))
115 #define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2
116 #define OSCCTRL_INTENCLR_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos)
117 #define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3
118 #define OSCCTRL_INTENCLR_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos)
119 #define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2
120 #define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
121 #define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos))
122 #define OSCCTRL_INTENCLR_DFLLRDY_Pos 8
123 #define OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos)
124 #define OSCCTRL_INTENCLR_DFLLOOB_Pos 9
125 #define OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos)
126 #define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10
127 #define OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos)
128 #define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11
129 #define OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos)
130 #define OSCCTRL_INTENCLR_DFLLRCS_Pos 12
131 #define OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos)
132 #define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16
133 #define OSCCTRL_INTENCLR_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos)
134 #define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17
135 #define OSCCTRL_INTENCLR_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos)
136 #define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18
137 #define OSCCTRL_INTENCLR_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos)
138 #define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19
139 #define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos)
140 #define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24
141 #define OSCCTRL_INTENCLR_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos)
142 #define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25
143 #define OSCCTRL_INTENCLR_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos)
144 #define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26
145 #define OSCCTRL_INTENCLR_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos)
146 #define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27
147 #define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos)
148 #define OSCCTRL_INTENCLR_MASK _U_(0x0F0F1F0F)
150 /* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */
151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
152 typedef union {
153  struct {
154  uint32_t XOSCRDY0:1;
155  uint32_t XOSCRDY1:1;
156  uint32_t XOSCFAIL0:1;
157  uint32_t XOSCFAIL1:1;
158  uint32_t :4;
159  uint32_t DFLLRDY:1;
160  uint32_t DFLLOOB:1;
161  uint32_t DFLLLCKF:1;
162  uint32_t DFLLLCKC:1;
163  uint32_t DFLLRCS:1;
164  uint32_t :3;
165  uint32_t DPLL0LCKR:1;
166  uint32_t DPLL0LCKF:1;
167  uint32_t DPLL0LTO:1;
168  uint32_t DPLL0LDRTO:1;
169  uint32_t :4;
170  uint32_t DPLL1LCKR:1;
171  uint32_t DPLL1LCKF:1;
172  uint32_t DPLL1LTO:1;
173  uint32_t DPLL1LDRTO:1;
174  uint32_t :4;
175  } bit;
176  struct {
177  uint32_t XOSCRDY:2;
178  uint32_t XOSCFAIL:2;
179  uint32_t :28;
180  } vec;
181  uint32_t reg;
183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
184 
185 #define OSCCTRL_INTENSET_OFFSET 0x08
186 #define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000)
188 #define OSCCTRL_INTENSET_XOSCRDY0_Pos 0
189 #define OSCCTRL_INTENSET_XOSCRDY0 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos)
190 #define OSCCTRL_INTENSET_XOSCRDY1_Pos 1
191 #define OSCCTRL_INTENSET_XOSCRDY1 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos)
192 #define OSCCTRL_INTENSET_XOSCRDY_Pos 0
193 #define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos)
194 #define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos))
195 #define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2
196 #define OSCCTRL_INTENSET_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos)
197 #define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3
198 #define OSCCTRL_INTENSET_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos)
199 #define OSCCTRL_INTENSET_XOSCFAIL_Pos 2
200 #define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
201 #define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos))
202 #define OSCCTRL_INTENSET_DFLLRDY_Pos 8
203 #define OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos)
204 #define OSCCTRL_INTENSET_DFLLOOB_Pos 9
205 #define OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos)
206 #define OSCCTRL_INTENSET_DFLLLCKF_Pos 10
207 #define OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos)
208 #define OSCCTRL_INTENSET_DFLLLCKC_Pos 11
209 #define OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos)
210 #define OSCCTRL_INTENSET_DFLLRCS_Pos 12
211 #define OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos)
212 #define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16
213 #define OSCCTRL_INTENSET_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos)
214 #define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17
215 #define OSCCTRL_INTENSET_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos)
216 #define OSCCTRL_INTENSET_DPLL0LTO_Pos 18
217 #define OSCCTRL_INTENSET_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos)
218 #define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19
219 #define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos)
220 #define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24
221 #define OSCCTRL_INTENSET_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos)
222 #define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25
223 #define OSCCTRL_INTENSET_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos)
224 #define OSCCTRL_INTENSET_DPLL1LTO_Pos 26
225 #define OSCCTRL_INTENSET_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos)
226 #define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27
227 #define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos)
228 #define OSCCTRL_INTENSET_MASK _U_(0x0F0F1F0F)
230 /* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */
231 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
232 typedef union { // __I to avoid read-modify-write on write-to-clear register
233  struct {
234  __I uint32_t XOSCRDY0:1;
235  __I uint32_t XOSCRDY1:1;
236  __I uint32_t XOSCFAIL0:1;
237  __I uint32_t XOSCFAIL1:1;
238  __I uint32_t :4;
239  __I uint32_t DFLLRDY:1;
240  __I uint32_t DFLLOOB:1;
241  __I uint32_t DFLLLCKF:1;
242  __I uint32_t DFLLLCKC:1;
243  __I uint32_t DFLLRCS:1;
244  __I uint32_t :3;
245  __I uint32_t DPLL0LCKR:1;
246  __I uint32_t DPLL0LCKF:1;
247  __I uint32_t DPLL0LTO:1;
248  __I uint32_t DPLL0LDRTO:1;
249  __I uint32_t :4;
250  __I uint32_t DPLL1LCKR:1;
251  __I uint32_t DPLL1LCKF:1;
252  __I uint32_t DPLL1LTO:1;
253  __I uint32_t DPLL1LDRTO:1;
254  __I uint32_t :4;
255  } bit;
256  struct {
257  __I uint32_t XOSCRDY:2;
258  __I uint32_t XOSCFAIL:2;
259  __I uint32_t :28;
260  } vec;
261  uint32_t reg;
263 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
264 
265 #define OSCCTRL_INTFLAG_OFFSET 0x0C
266 #define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000)
268 #define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0
269 #define OSCCTRL_INTFLAG_XOSCRDY0 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos)
270 #define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1
271 #define OSCCTRL_INTFLAG_XOSCRDY1 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos)
272 #define OSCCTRL_INTFLAG_XOSCRDY_Pos 0
273 #define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
274 #define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos))
275 #define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2
276 #define OSCCTRL_INTFLAG_XOSCFAIL0 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos)
277 #define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3
278 #define OSCCTRL_INTFLAG_XOSCFAIL1 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos)
279 #define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2
280 #define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
281 #define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos))
282 #define OSCCTRL_INTFLAG_DFLLRDY_Pos 8
283 #define OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos)
284 #define OSCCTRL_INTFLAG_DFLLOOB_Pos 9
285 #define OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos)
286 #define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10
287 #define OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos)
288 #define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11
289 #define OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos)
290 #define OSCCTRL_INTFLAG_DFLLRCS_Pos 12
291 #define OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos)
292 #define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16
293 #define OSCCTRL_INTFLAG_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos)
294 #define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17
295 #define OSCCTRL_INTFLAG_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos)
296 #define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18
297 #define OSCCTRL_INTFLAG_DPLL0LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos)
298 #define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19
299 #define OSCCTRL_INTFLAG_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos)
300 #define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24
301 #define OSCCTRL_INTFLAG_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos)
302 #define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25
303 #define OSCCTRL_INTFLAG_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos)
304 #define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26
305 #define OSCCTRL_INTFLAG_DPLL1LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos)
306 #define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27
307 #define OSCCTRL_INTFLAG_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos)
308 #define OSCCTRL_INTFLAG_MASK _U_(0x0F0F1F0F)
310 /* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/ 32) Status -------- */
311 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
312 typedef union {
313  struct {
314  uint32_t XOSCRDY0:1;
315  uint32_t XOSCRDY1:1;
316  uint32_t XOSCFAIL0:1;
317  uint32_t XOSCFAIL1:1;
318  uint32_t XOSCCKSW0:1;
319  uint32_t XOSCCKSW1:1;
320  uint32_t :2;
321  uint32_t DFLLRDY:1;
322  uint32_t DFLLOOB:1;
323  uint32_t DFLLLCKF:1;
324  uint32_t DFLLLCKC:1;
325  uint32_t DFLLRCS:1;
326  uint32_t :3;
327  uint32_t DPLL0LCKR:1;
328  uint32_t DPLL0LCKF:1;
329  uint32_t DPLL0TO:1;
330  uint32_t DPLL0LDRTO:1;
331  uint32_t :4;
332  uint32_t DPLL1LCKR:1;
333  uint32_t DPLL1LCKF:1;
334  uint32_t DPLL1TO:1;
335  uint32_t DPLL1LDRTO:1;
336  uint32_t :4;
337  } bit;
338  struct {
339  uint32_t XOSCRDY:2;
340  uint32_t XOSCFAIL:2;
341  uint32_t XOSCCKSW:2;
342  uint32_t :26;
343  } vec;
344  uint32_t reg;
346 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
347 
348 #define OSCCTRL_STATUS_OFFSET 0x10
349 #define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000)
351 #define OSCCTRL_STATUS_XOSCRDY0_Pos 0
352 #define OSCCTRL_STATUS_XOSCRDY0 (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos)
353 #define OSCCTRL_STATUS_XOSCRDY1_Pos 1
354 #define OSCCTRL_STATUS_XOSCRDY1 (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos)
355 #define OSCCTRL_STATUS_XOSCRDY_Pos 0
356 #define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos)
357 #define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos))
358 #define OSCCTRL_STATUS_XOSCFAIL0_Pos 2
359 #define OSCCTRL_STATUS_XOSCFAIL0 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos)
360 #define OSCCTRL_STATUS_XOSCFAIL1_Pos 3
361 #define OSCCTRL_STATUS_XOSCFAIL1 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos)
362 #define OSCCTRL_STATUS_XOSCFAIL_Pos 2
363 #define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos)
364 #define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos))
365 #define OSCCTRL_STATUS_XOSCCKSW0_Pos 4
366 #define OSCCTRL_STATUS_XOSCCKSW0 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos)
367 #define OSCCTRL_STATUS_XOSCCKSW1_Pos 5
368 #define OSCCTRL_STATUS_XOSCCKSW1 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos)
369 #define OSCCTRL_STATUS_XOSCCKSW_Pos 4
370 #define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos)
371 #define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos))
372 #define OSCCTRL_STATUS_DFLLRDY_Pos 8
373 #define OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos)
374 #define OSCCTRL_STATUS_DFLLOOB_Pos 9
375 #define OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos)
376 #define OSCCTRL_STATUS_DFLLLCKF_Pos 10
377 #define OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos)
378 #define OSCCTRL_STATUS_DFLLLCKC_Pos 11
379 #define OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos)
380 #define OSCCTRL_STATUS_DFLLRCS_Pos 12
381 #define OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos)
382 #define OSCCTRL_STATUS_DPLL0LCKR_Pos 16
383 #define OSCCTRL_STATUS_DPLL0LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos)
384 #define OSCCTRL_STATUS_DPLL0LCKF_Pos 17
385 #define OSCCTRL_STATUS_DPLL0LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos)
386 #define OSCCTRL_STATUS_DPLL0TO_Pos 18
387 #define OSCCTRL_STATUS_DPLL0TO (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos)
388 #define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19
389 #define OSCCTRL_STATUS_DPLL0LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos)
390 #define OSCCTRL_STATUS_DPLL1LCKR_Pos 24
391 #define OSCCTRL_STATUS_DPLL1LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos)
392 #define OSCCTRL_STATUS_DPLL1LCKF_Pos 25
393 #define OSCCTRL_STATUS_DPLL1LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos)
394 #define OSCCTRL_STATUS_DPLL1TO_Pos 26
395 #define OSCCTRL_STATUS_DPLL1TO (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos)
396 #define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27
397 #define OSCCTRL_STATUS_DPLL1LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos)
398 #define OSCCTRL_STATUS_MASK _U_(0x0F0F1F3F)
400 /* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */
401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
402 typedef union {
403  struct {
404  uint32_t :1;
405  uint32_t ENABLE:1;
406  uint32_t XTALEN:1;
407  uint32_t :3;
408  uint32_t RUNSTDBY:1;
409  uint32_t ONDEMAND:1;
410  uint32_t LOWBUFGAIN:1;
411  uint32_t IPTAT:2;
412  uint32_t IMULT:4;
413  uint32_t ENALC:1;
414  uint32_t CFDEN:1;
415  uint32_t SWBEN:1;
416  uint32_t :2;
417  uint32_t STARTUP:4;
418  uint32_t CFDPRESC:4;
419  uint32_t :4;
420  } bit;
421  uint32_t reg;
423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
424 
425 #define OSCCTRL_XOSCCTRL_OFFSET 0x14
426 #define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080)
428 #define OSCCTRL_XOSCCTRL_ENABLE_Pos 1
429 #define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
430 #define OSCCTRL_XOSCCTRL_XTALEN_Pos 2
431 #define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
432 #define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6
433 #define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
434 #define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7
435 #define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
436 #define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8
437 #define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos)
438 #define OSCCTRL_XOSCCTRL_IPTAT_Pos 9
439 #define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos)
440 #define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos))
441 #define OSCCTRL_XOSCCTRL_IMULT_Pos 11
442 #define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos)
443 #define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos))
444 #define OSCCTRL_XOSCCTRL_ENALC_Pos 15
445 #define OSCCTRL_XOSCCTRL_ENALC (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos)
446 #define OSCCTRL_XOSCCTRL_CFDEN_Pos 16
447 #define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
448 #define OSCCTRL_XOSCCTRL_SWBEN_Pos 17
449 #define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
450 #define OSCCTRL_XOSCCTRL_STARTUP_Pos 20
451 #define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
452 #define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
453 #define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24
454 #define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)
455 #define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos))
456 #define OSCCTRL_XOSCCTRL_MASK _U_(0x0FF3FFC6)
458 /* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */
459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
460 typedef union {
461  struct {
462  uint8_t :1;
463  uint8_t ENABLE:1;
464  uint8_t :4;
465  uint8_t RUNSTDBY:1;
466  uint8_t ONDEMAND:1;
467  } bit;
468  uint8_t reg;
470 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
471 
472 #define OSCCTRL_DFLLCTRLA_OFFSET 0x1C
473 #define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82)
475 #define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1
476 #define OSCCTRL_DFLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos)
477 #define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6
478 #define OSCCTRL_DFLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos)
479 #define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7
480 #define OSCCTRL_DFLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos)
481 #define OSCCTRL_DFLLCTRLA_MASK _U_(0xC2)
483 /* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */
484 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
485 typedef union {
486  struct {
487  uint8_t MODE:1;
488  uint8_t STABLE:1;
489  uint8_t LLAW:1;
490  uint8_t USBCRM:1;
491  uint8_t CCDIS:1;
492  uint8_t QLDIS:1;
493  uint8_t BPLCKC:1;
494  uint8_t WAITLOCK:1;
495  } bit;
496  uint8_t reg;
498 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
499 
500 #define OSCCTRL_DFLLCTRLB_OFFSET 0x20
501 #define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00)
503 #define OSCCTRL_DFLLCTRLB_MODE_Pos 0
504 #define OSCCTRL_DFLLCTRLB_MODE (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos)
505 #define OSCCTRL_DFLLCTRLB_STABLE_Pos 1
506 #define OSCCTRL_DFLLCTRLB_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos)
507 #define OSCCTRL_DFLLCTRLB_LLAW_Pos 2
508 #define OSCCTRL_DFLLCTRLB_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos)
509 #define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3
510 #define OSCCTRL_DFLLCTRLB_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos)
511 #define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4
512 #define OSCCTRL_DFLLCTRLB_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos)
513 #define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5
514 #define OSCCTRL_DFLLCTRLB_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos)
515 #define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6
516 #define OSCCTRL_DFLLCTRLB_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos)
517 #define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7
518 #define OSCCTRL_DFLLCTRLB_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos)
519 #define OSCCTRL_DFLLCTRLB_MASK _U_(0xFF)
521 /* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */
522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
523 typedef union {
524  struct {
525  uint32_t FINE:8;
526  uint32_t :2;
527  uint32_t COARSE:6;
528  uint32_t DIFF:16;
529  } bit;
530  uint32_t reg;
532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
533 
534 #define OSCCTRL_DFLLVAL_OFFSET 0x24
535 #define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000)
537 #define OSCCTRL_DFLLVAL_FINE_Pos 0
538 #define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos)
539 #define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos))
540 #define OSCCTRL_DFLLVAL_COARSE_Pos 10
541 #define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos)
542 #define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos))
543 #define OSCCTRL_DFLLVAL_DIFF_Pos 16
544 #define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos)
545 #define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos))
546 #define OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFCFF)
548 /* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */
549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
550 typedef union {
551  struct {
552  uint32_t MUL:16;
553  uint32_t FSTEP:8;
554  uint32_t :2;
555  uint32_t CSTEP:6;
556  } bit;
557  uint32_t reg;
559 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
560 
561 #define OSCCTRL_DFLLMUL_OFFSET 0x28
562 #define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000)
564 #define OSCCTRL_DFLLMUL_MUL_Pos 0
565 #define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos)
566 #define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos))
567 #define OSCCTRL_DFLLMUL_FSTEP_Pos 16
568 #define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos)
569 #define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos))
570 #define OSCCTRL_DFLLMUL_CSTEP_Pos 26
571 #define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos)
572 #define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos))
573 #define OSCCTRL_DFLLMUL_MASK _U_(0xFCFFFFFF)
575 /* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */
576 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
577 typedef union {
578  struct {
579  uint8_t :1;
580  uint8_t ENABLE:1;
581  uint8_t DFLLCTRLB:1;
582  uint8_t DFLLVAL:1;
583  uint8_t DFLLMUL:1;
584  uint8_t :3;
585  } bit;
586  uint8_t reg;
588 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
589 
590 #define OSCCTRL_DFLLSYNC_OFFSET 0x2C
591 #define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00)
593 #define OSCCTRL_DFLLSYNC_ENABLE_Pos 1
594 #define OSCCTRL_DFLLSYNC_ENABLE (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos)
595 #define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2
596 #define OSCCTRL_DFLLSYNC_DFLLCTRLB (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos)
597 #define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3
598 #define OSCCTRL_DFLLSYNC_DFLLVAL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos)
599 #define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4
600 #define OSCCTRL_DFLLSYNC_DFLLMUL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos)
601 #define OSCCTRL_DFLLSYNC_MASK _U_(0x1E)
603 /* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W 8) DPLL DPLL Control A -------- */
604 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
605 typedef union {
606  struct {
607  uint8_t :1;
608  uint8_t ENABLE:1;
609  uint8_t :4;
610  uint8_t RUNSTDBY:1;
611  uint8_t ONDEMAND:1;
612  } bit;
613  uint8_t reg;
615 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
616 
617 #define OSCCTRL_DPLLCTRLA_OFFSET 0x30
618 #define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80)
620 #define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1
621 #define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
622 #define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6
623 #define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
624 #define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7
625 #define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
626 #define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2)
628 /* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */
629 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
630 typedef union {
631  struct {
632  uint32_t LDR:13;
633  uint32_t :3;
634  uint32_t LDRFRAC:5;
635  uint32_t :11;
636  } bit;
637  uint32_t reg;
639 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
640 
641 #define OSCCTRL_DPLLRATIO_OFFSET 0x34
642 #define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000)
644 #define OSCCTRL_DPLLRATIO_LDR_Pos 0
645 #define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
646 #define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
647 #define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16
648 #define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
649 #define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
650 #define OSCCTRL_DPLLRATIO_MASK _U_(0x001F1FFF)
652 /* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */
653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
654 typedef union {
655  struct {
656  uint32_t FILTER:4;
657  uint32_t WUF:1;
658  uint32_t REFCLK:3;
659  uint32_t LTIME:3;
660  uint32_t LBYPASS:1;
661  uint32_t DCOFILTER:3;
662  uint32_t DCOEN:1;
663  uint32_t DIV:11;
664  uint32_t :5;
665  } bit;
666  uint32_t reg;
668 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
669 
670 #define OSCCTRL_DPLLCTRLB_OFFSET 0x38
671 #define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020)
673 #define OSCCTRL_DPLLCTRLB_FILTER_Pos 0
674 #define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
675 #define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
676 #define OSCCTRL_DPLLCTRLB_WUF_Pos 4
677 #define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
678 #define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5
679 #define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
680 #define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
681 #define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0)
682 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1)
683 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2)
684 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3)
685 #define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
686 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
687 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
688 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
689 #define OSCCTRL_DPLLCTRLB_LTIME_Pos 8
690 #define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
691 #define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
692 #define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0)
693 #define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4)
694 #define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5)
695 #define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6)
696 #define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7)
697 #define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
698 #define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
699 #define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
700 #define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
701 #define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos)
702 #define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11
703 #define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
704 #define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12
705 #define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)
706 #define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos))
707 #define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15
708 #define OSCCTRL_DPLLCTRLB_DCOEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos)
709 #define OSCCTRL_DPLLCTRLB_DIV_Pos 16
710 #define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
711 #define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
712 #define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FFFFFF)
714 /* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/ 32) DPLL DPLL Synchronization Busy -------- */
715 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
716 typedef union {
717  struct {
718  uint32_t :1;
719  uint32_t ENABLE:1;
720  uint32_t DPLLRATIO:1;
721  uint32_t :29;
722  } bit;
723  uint32_t reg;
725 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
726 
727 #define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C
728 #define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000)
730 #define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1
731 #define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
732 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2
733 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
734 #define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x00000006)
736 /* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/ 32) DPLL DPLL Status -------- */
737 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
738 typedef union {
739  struct {
740  uint32_t LOCK:1;
741  uint32_t CLKRDY:1;
742  uint32_t :30;
743  } bit;
744  uint32_t reg;
746 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
747 
748 #define OSCCTRL_DPLLSTATUS_OFFSET 0x40
749 #define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000)
751 #define OSCCTRL_DPLLSTATUS_LOCK_Pos 0
752 #define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
753 #define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1
754 #define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
755 #define OSCCTRL_DPLLSTATUS_MASK _U_(0x00000003)
758 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
759 typedef struct {
761  RoReg8 Reserved1[0x3];
766 } OscctrlDpll;
767 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
768 
770 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
771 typedef struct {
773  RoReg8 Reserved1[0x3];
778  __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL[2];
780  RoReg8 Reserved2[0x3];
782  RoReg8 Reserved3[0x3];
786  RoReg8 Reserved4[0x3];
787  OscctrlDpll Dpll[2];
788 } Oscctrl;
789 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
790 
793 #endif /* _SAME54_OSCCTRL_COMPONENT_ */
Oscctrl::INTENCLR
__IO OSCCTRL_INTENCLR_Type INTENCLR
Offset: 0x04 (R/W 32) Interrupt Enable Clear.
Definition: oscctrl.h:774
OSCCTRL_STATUS_Type::DPLL0LCKR
uint32_t DPLL0LCKR
Definition: oscctrl.h:327
OSCCTRL_DFLLMUL_Type::FSTEP
uint32_t FSTEP
Definition: oscctrl.h:553
OSCCTRL_DFLLCTRLB_Type::USBCRM
uint8_t USBCRM
Definition: oscctrl.h:490
OSCCTRL_STATUS_Type::DPLL1LCKR
uint32_t DPLL1LCKR
Definition: oscctrl.h:332
OSCCTRL_DFLLCTRLB_Type::CCDIS
uint8_t CCDIS
Definition: oscctrl.h:491
OSCCTRL_INTENCLR_Type::DPLL0LCKF
uint32_t DPLL0LCKF
Definition: oscctrl.h:86
Oscctrl::DFLLVAL
__IO OSCCTRL_DFLLVAL_Type DFLLVAL
Offset: 0x24 (R/W 32) DFLL48M Value.
Definition: oscctrl.h:783
OSCCTRL_XOSCCTRL_Type::CFDEN
uint32_t CFDEN
Definition: oscctrl.h:414
OSCCTRL_INTFLAG_Type::DPLL1LCKR
__I uint32_t DPLL1LCKR
Definition: oscctrl.h:250
OSCCTRL_DFLLVAL_Type::FINE
uint32_t FINE
Definition: oscctrl.h:525
OSCCTRL_DPLLCTRLB_Type::WUF
uint32_t WUF
Definition: oscctrl.h:657
OSCCTRL_INTENCLR_Type::reg
uint32_t reg
Definition: oscctrl.h:101
OSCCTRL_DFLLCTRLA_Type::ONDEMAND
uint8_t ONDEMAND
Definition: oscctrl.h:466
OSCCTRL_DFLLVAL_Type
Definition: oscctrl.h:523
OSCCTRL_DFLLMUL_Type
Definition: oscctrl.h:550
OSCCTRL_XOSCCTRL_Type::CFDPRESC
uint32_t CFDPRESC
Definition: oscctrl.h:418
OSCCTRL_STATUS_Type::DPLL1LCKF
uint32_t DPLL1LCKF
Definition: oscctrl.h:333
OSCCTRL_INTFLAG_Type::DFLLRCS
__I uint32_t DFLLRCS
Definition: oscctrl.h:243
OSCCTRL_XOSCCTRL_Type::reg
uint32_t reg
Definition: oscctrl.h:421
OSCCTRL_INTENCLR_Type::DPLL1LCKF
uint32_t DPLL1LCKF
Definition: oscctrl.h:91
OscctrlDpll::DPLLCTRLA
__IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA
Offset: 0x00 (R/W 8) DPLL Control A.
Definition: oscctrl.h:760
Oscctrl::DFLLCTRLB
__IO OSCCTRL_DFLLCTRLB_Type DFLLCTRLB
Offset: 0x20 (R/W 8) DFLL48M Control B.
Definition: oscctrl.h:781
OSCCTRL_XOSCCTRL_Type::SWBEN
uint32_t SWBEN
Definition: oscctrl.h:415
OSCCTRL_DFLLCTRLA_Type::ENABLE
uint8_t ENABLE
Definition: oscctrl.h:463
OSCCTRL_DFLLCTRLA_Type::reg
uint8_t reg
Definition: oscctrl.h:468
OSCCTRL_INTENSET_Type::XOSCRDY
uint32_t XOSCRDY
Definition: oscctrl.h:177
OSCCTRL_INTENCLR_Type::XOSCFAIL1
uint32_t XOSCFAIL1
Definition: oscctrl.h:77
OSCCTRL_DPLLCTRLB_Type::DCOFILTER
uint32_t DCOFILTER
Definition: oscctrl.h:661
OSCCTRL_STATUS_Type::DPLL0LDRTO
uint32_t DPLL0LDRTO
Definition: oscctrl.h:330
OSCCTRL_INTENSET_Type::DFLLRCS
uint32_t DFLLRCS
Definition: oscctrl.h:163
OSCCTRL_XOSCCTRL_Type::LOWBUFGAIN
uint32_t LOWBUFGAIN
Definition: oscctrl.h:410
OSCCTRL_DPLLCTRLB_Type::REFCLK
uint32_t REFCLK
Definition: oscctrl.h:658
OSCCTRL_INTENSET_Type::reg
uint32_t reg
Definition: oscctrl.h:181
OSCCTRL_XOSCCTRL_Type::RUNSTDBY
uint32_t RUNSTDBY
Definition: oscctrl.h:408
OSCCTRL_DFLLCTRLB_Type::BPLCKC
uint8_t BPLCKC
Definition: oscctrl.h:493
OSCCTRL_INTENSET_Type::DFLLRDY
uint32_t DFLLRDY
Definition: oscctrl.h:159
OSCCTRL_STATUS_Type::DPLL0LCKF
uint32_t DPLL0LCKF
Definition: oscctrl.h:328
OSCCTRL_XOSCCTRL_Type::ENABLE
uint32_t ENABLE
Definition: oscctrl.h:405
OSCCTRL_INTENSET_Type::DPLL1LCKR
uint32_t DPLL1LCKR
Definition: oscctrl.h:170
OSCCTRL_DFLLSYNC_Type
Definition: oscctrl.h:577
OSCCTRL_INTENSET_Type::DPLL0LCKF
uint32_t DPLL0LCKF
Definition: oscctrl.h:166
OSCCTRL_INTENCLR_Type::DPLL1LDRTO
uint32_t DPLL1LDRTO
Definition: oscctrl.h:93
OSCCTRL_STATUS_Type::DFLLLCKC
uint32_t DFLLLCKC
Definition: oscctrl.h:324
OSCCTRL_DPLLSYNCBUSY_Type
Definition: oscctrl.h:716
OSCCTRL_STATUS_Type
Definition: oscctrl.h:312
OSCCTRL_INTENCLR_Type::DPLL0LTO
uint32_t DPLL0LTO
Definition: oscctrl.h:87
OSCCTRL_EVCTRL_Type::CFDEO
uint8_t CFDEO
Definition: oscctrl.h:51
OSCCTRL_DFLLCTRLA_Type::RUNSTDBY
uint8_t RUNSTDBY
Definition: oscctrl.h:465
OSCCTRL_INTENSET_Type::XOSCFAIL1
uint32_t XOSCFAIL1
Definition: oscctrl.h:157
OSCCTRL_DPLLCTRLB_Type::reg
uint32_t reg
Definition: oscctrl.h:666
OscctrlDpll::DPLLRATIO
__IO OSCCTRL_DPLLRATIO_Type DPLLRATIO
Offset: 0x04 (R/W 32) DPLL Ratio Control.
Definition: oscctrl.h:762
OSCCTRL_INTENCLR_Type::DFLLLCKC
uint32_t DFLLLCKC
Definition: oscctrl.h:82
OSCCTRL_DFLLSYNC_Type::DFLLVAL
uint8_t DFLLVAL
Definition: oscctrl.h:582
OSCCTRL_INTFLAG_Type
Definition: oscctrl.h:232
OSCCTRL_INTENSET_Type::XOSCFAIL0
uint32_t XOSCFAIL0
Definition: oscctrl.h:156
OscctrlDpll
OscctrlDpll hardware registers.
Definition: oscctrl.h:759
OSCCTRL_DPLLCTRLB_Type::LTIME
uint32_t LTIME
Definition: oscctrl.h:659
Oscctrl::DFLLMUL
__IO OSCCTRL_DFLLMUL_Type DFLLMUL
Offset: 0x28 (R/W 32) DFLL48M Multiplier.
Definition: oscctrl.h:784
Oscctrl::DFLLSYNC
__IO OSCCTRL_DFLLSYNC_Type DFLLSYNC
Offset: 0x2C (R/W 8) DFLL48M Synchronization.
Definition: oscctrl.h:785
OSCCTRL_STATUS_Type::XOSCCKSW1
uint32_t XOSCCKSW1
Definition: oscctrl.h:319
OSCCTRL_INTENSET_Type
Definition: oscctrl.h:152
OSCCTRL_DFLLVAL_Type::reg
uint32_t reg
Definition: oscctrl.h:530
OSCCTRL_DPLLRATIO_Type::LDR
uint32_t LDR
Definition: oscctrl.h:632
OSCCTRL_DPLLCTRLB_Type::LBYPASS
uint32_t LBYPASS
Definition: oscctrl.h:660
OSCCTRL_DFLLMUL_Type::reg
uint32_t reg
Definition: oscctrl.h:557
OSCCTRL_DPLLRATIO_Type::reg
uint32_t reg
Definition: oscctrl.h:637
OSCCTRL_DFLLCTRLA_Type
Definition: oscctrl.h:460
OSCCTRL_DPLLCTRLA_Type::RUNSTDBY
uint8_t RUNSTDBY
Definition: oscctrl.h:610
OSCCTRL_DPLLSTATUS_Type
Definition: oscctrl.h:738
OSCCTRL_DPLLCTRLB_Type::FILTER
uint32_t FILTER
Definition: oscctrl.h:656
OSCCTRL_DFLLCTRLB_Type::reg
uint8_t reg
Definition: oscctrl.h:496
OSCCTRL_DPLLCTRLB_Type::DIV
uint32_t DIV
Definition: oscctrl.h:663
OSCCTRL_INTENSET_Type::DPLL1LTO
uint32_t DPLL1LTO
Definition: oscctrl.h:172
OSCCTRL_STATUS_Type::DFLLRDY
uint32_t DFLLRDY
Definition: oscctrl.h:321
OSCCTRL_DFLLSYNC_Type::DFLLCTRLB
uint8_t DFLLCTRLB
Definition: oscctrl.h:581
OSCCTRL_DPLLSYNCBUSY_Type::reg
uint32_t reg
Definition: oscctrl.h:723
OSCCTRL_INTFLAG_Type::DPLL1LDRTO
__I uint32_t DPLL1LDRTO
Definition: oscctrl.h:253
OSCCTRL_DPLLSTATUS_Type::reg
uint32_t reg
Definition: oscctrl.h:744
OSCCTRL_DFLLCTRLB_Type
Definition: oscctrl.h:485
OSCCTRL_DPLLSYNCBUSY_Type::ENABLE
uint32_t ENABLE
Definition: oscctrl.h:719
Oscctrl::STATUS
__I OSCCTRL_STATUS_Type STATUS
Offset: 0x10 (R/ 32) Status.
Definition: oscctrl.h:777
OSCCTRL_XOSCCTRL_Type::ENALC
uint32_t ENALC
Definition: oscctrl.h:413
OSCCTRL_INTENCLR_Type::DPLL0LDRTO
uint32_t DPLL0LDRTO
Definition: oscctrl.h:88
OSCCTRL_INTENCLR_Type::DFLLLCKF
uint32_t DFLLLCKF
Definition: oscctrl.h:81
OSCCTRL_INTFLAG_Type::DFLLLCKC
__I uint32_t DFLLLCKC
Definition: oscctrl.h:242
OSCCTRL_INTFLAG_Type::XOSCFAIL1
__I uint32_t XOSCFAIL1
Definition: oscctrl.h:237
OSCCTRL_XOSCCTRL_Type
Definition: oscctrl.h:402
OSCCTRL_EVCTRL_Type::CFDEO0
uint8_t CFDEO0
Definition: oscctrl.h:46
OSCCTRL_INTFLAG_Type::DPLL0LTO
__I uint32_t DPLL0LTO
Definition: oscctrl.h:247
OSCCTRL_STATUS_Type::XOSCCKSW
uint32_t XOSCCKSW
Definition: oscctrl.h:341
OSCCTRL_DFLLMUL_Type::CSTEP
uint32_t CSTEP
Definition: oscctrl.h:555
OSCCTRL_DFLLVAL_Type::DIFF
uint32_t DIFF
Definition: oscctrl.h:528
OSCCTRL_DFLLCTRLB_Type::MODE
uint8_t MODE
Definition: oscctrl.h:487
OSCCTRL_INTENSET_Type::DPLL1LCKF
uint32_t DPLL1LCKF
Definition: oscctrl.h:171
OSCCTRL_DPLLRATIO_Type
Definition: oscctrl.h:630
OSCCTRL_INTFLAG_Type::DPLL1LTO
__I uint32_t DPLL1LTO
Definition: oscctrl.h:252
OSCCTRL_INTENCLR_Type::DFLLRCS
uint32_t DFLLRCS
Definition: oscctrl.h:83
OSCCTRL_XOSCCTRL_Type::IMULT
uint32_t IMULT
Definition: oscctrl.h:412
OSCCTRL_DPLLCTRLA_Type::reg
uint8_t reg
Definition: oscctrl.h:613
OSCCTRL_INTENSET_Type::DFLLLCKF
uint32_t DFLLLCKF
Definition: oscctrl.h:161
OSCCTRL_DPLLSTATUS_Type::CLKRDY
uint32_t CLKRDY
Definition: oscctrl.h:741
OSCCTRL_INTFLAG_Type::reg
uint32_t reg
Definition: oscctrl.h:261
OSCCTRL_INTENCLR_Type::DPLL0LCKR
uint32_t DPLL0LCKR
Definition: oscctrl.h:85
OSCCTRL_INTENSET_Type::DFLLOOB
uint32_t DFLLOOB
Definition: oscctrl.h:160
OSCCTRL_DFLLCTRLB_Type::LLAW
uint8_t LLAW
Definition: oscctrl.h:489
OSCCTRL_EVCTRL_Type::CFDEO1
uint8_t CFDEO1
Definition: oscctrl.h:47
OSCCTRL_STATUS_Type::XOSCRDY1
uint32_t XOSCRDY1
Definition: oscctrl.h:315
OSCCTRL_INTENSET_Type::XOSCRDY1
uint32_t XOSCRDY1
Definition: oscctrl.h:155
OSCCTRL_INTENCLR_Type
Definition: oscctrl.h:72
OSCCTRL_DFLLCTRLB_Type::WAITLOCK
uint8_t WAITLOCK
Definition: oscctrl.h:494
OSCCTRL_DFLLSYNC_Type::DFLLMUL
uint8_t DFLLMUL
Definition: oscctrl.h:583
OSCCTRL_INTFLAG_Type::DPLL0LCKF
__I uint32_t DPLL0LCKF
Definition: oscctrl.h:246
OSCCTRL_DFLLCTRLB_Type::STABLE
uint8_t STABLE
Definition: oscctrl.h:488
OSCCTRL_INTFLAG_Type::uint32_t
__I uint32_t
Definition: oscctrl.h:238
OSCCTRL_INTENCLR_Type::DPLL1LTO
uint32_t DPLL1LTO
Definition: oscctrl.h:92
OSCCTRL_INTFLAG_Type::DFLLLCKF
__I uint32_t DFLLLCKF
Definition: oscctrl.h:241
OSCCTRL_INTFLAG_Type::XOSCFAIL
__I uint32_t XOSCFAIL
Definition: oscctrl.h:258
OSCCTRL_STATUS_Type::DPLL1LDRTO
uint32_t DPLL1LDRTO
Definition: oscctrl.h:335
Oscctrl::DFLLCTRLA
__IO OSCCTRL_DFLLCTRLA_Type DFLLCTRLA
Offset: 0x1C (R/W 8) DFLL48M Control A.
Definition: oscctrl.h:779
OSCCTRL_DPLLSYNCBUSY_Type::DPLLRATIO
uint32_t DPLLRATIO
Definition: oscctrl.h:720
OSCCTRL_INTENCLR_Type::XOSCFAIL0
uint32_t XOSCFAIL0
Definition: oscctrl.h:76
OSCCTRL_DPLLCTRLA_Type::ENABLE
uint8_t ENABLE
Definition: oscctrl.h:608
OSCCTRL_STATUS_Type::DPLL1TO
uint32_t DPLL1TO
Definition: oscctrl.h:334
Oscctrl::EVCTRL
__IO OSCCTRL_EVCTRL_Type EVCTRL
Offset: 0x00 (R/W 8) Event Control.
Definition: oscctrl.h:772
OSCCTRL_STATUS_Type::DPLL0TO
uint32_t DPLL0TO
Definition: oscctrl.h:329
OSCCTRL_STATUS_Type::XOSCFAIL
uint32_t XOSCFAIL
Definition: oscctrl.h:340
OSCCTRL_INTENSET_Type::DFLLLCKC
uint32_t DFLLLCKC
Definition: oscctrl.h:162
OSCCTRL_STATUS_Type::reg
uint32_t reg
Definition: oscctrl.h:344
OSCCTRL_INTFLAG_Type::XOSCRDY
__I uint32_t XOSCRDY
Definition: oscctrl.h:257
OSCCTRL_DPLLSTATUS_Type::LOCK
uint32_t LOCK
Definition: oscctrl.h:740
OSCCTRL_INTENSET_Type::DPLL0LCKR
uint32_t DPLL0LCKR
Definition: oscctrl.h:165
OSCCTRL_DPLLCTRLA_Type::ONDEMAND
uint8_t ONDEMAND
Definition: oscctrl.h:611
OSCCTRL_XOSCCTRL_Type::XTALEN
uint32_t XTALEN
Definition: oscctrl.h:406
OSCCTRL_INTENSET_Type::XOSCFAIL
uint32_t XOSCFAIL
Definition: oscctrl.h:178
OscctrlDpll::DPLLCTRLB
__IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB
Offset: 0x08 (R/W 32) DPLL Control B.
Definition: oscctrl.h:763
OSCCTRL_XOSCCTRL_Type::IPTAT
uint32_t IPTAT
Definition: oscctrl.h:411
OSCCTRL_INTENSET_Type::DPLL0LTO
uint32_t DPLL0LTO
Definition: oscctrl.h:167
OSCCTRL_DFLLSYNC_Type::reg
uint8_t reg
Definition: oscctrl.h:586
OSCCTRL_DFLLCTRLB_Type::QLDIS
uint8_t QLDIS
Definition: oscctrl.h:492
OSCCTRL_STATUS_Type::DFLLOOB
uint32_t DFLLOOB
Definition: oscctrl.h:322
OSCCTRL_DFLLSYNC_Type::ENABLE
uint8_t ENABLE
Definition: oscctrl.h:580
Oscctrl
OSCCTRL hardware registers.
Definition: oscctrl.h:771
OSCCTRL_XOSCCTRL_Type::STARTUP
uint32_t STARTUP
Definition: oscctrl.h:417
OSCCTRL_DPLLCTRLB_Type::DCOEN
uint32_t DCOEN
Definition: oscctrl.h:662
OSCCTRL_EVCTRL_Type::reg
uint8_t reg
Definition: oscctrl.h:54
OSCCTRL_DFLLVAL_Type::COARSE
uint32_t COARSE
Definition: oscctrl.h:527
OSCCTRL_INTENCLR_Type::DFLLOOB
uint32_t DFLLOOB
Definition: oscctrl.h:80
OSCCTRL_INTENCLR_Type::DFLLRDY
uint32_t DFLLRDY
Definition: oscctrl.h:79
OSCCTRL_INTENCLR_Type::XOSCRDY0
uint32_t XOSCRDY0
Definition: oscctrl.h:74
OscctrlDpll::DPLLSTATUS
__I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS
Offset: 0x10 (R/ 32) DPLL Status.
Definition: oscctrl.h:765
OSCCTRL_DPLLCTRLA_Type
Definition: oscctrl.h:605
OSCCTRL_STATUS_Type::DFLLLCKF
uint32_t DFLLLCKF
Definition: oscctrl.h:323
OSCCTRL_STATUS_Type::DFLLRCS
uint32_t DFLLRCS
Definition: oscctrl.h:325
OSCCTRL_STATUS_Type::XOSCRDY
uint32_t XOSCRDY
Definition: oscctrl.h:339
OSCCTRL_INTFLAG_Type::DPLL0LDRTO
__I uint32_t DPLL0LDRTO
Definition: oscctrl.h:248
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
OSCCTRL_INTENCLR_Type::XOSCRDY1
uint32_t XOSCRDY1
Definition: oscctrl.h:75
OscctrlDpll::DPLLSYNCBUSY
__I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY
Offset: 0x0C (R/ 32) DPLL Synchronization Busy.
Definition: oscctrl.h:764
Oscctrl::INTENSET
__IO OSCCTRL_INTENSET_Type INTENSET
Offset: 0x08 (R/W 32) Interrupt Enable Set.
Definition: oscctrl.h:775
OSCCTRL_INTENCLR_Type::XOSCRDY
uint32_t XOSCRDY
Definition: oscctrl.h:97
OSCCTRL_INTENSET_Type::XOSCRDY0
uint32_t XOSCRDY0
Definition: oscctrl.h:154
OSCCTRL_INTFLAG_Type::DFLLOOB
__I uint32_t DFLLOOB
Definition: oscctrl.h:240
OSCCTRL_STATUS_Type::XOSCCKSW0
uint32_t XOSCCKSW0
Definition: oscctrl.h:318
OSCCTRL_EVCTRL_Type
Definition: oscctrl.h:44
OSCCTRL_STATUS_Type::XOSCFAIL0
uint32_t XOSCFAIL0
Definition: oscctrl.h:316
OSCCTRL_INTFLAG_Type::DPLL0LCKR
__I uint32_t DPLL0LCKR
Definition: oscctrl.h:245
OSCCTRL_INTENSET_Type::DPLL0LDRTO
uint32_t DPLL0LDRTO
Definition: oscctrl.h:168
OSCCTRL_INTFLAG_Type::DPLL1LCKF
__I uint32_t DPLL1LCKF
Definition: oscctrl.h:251
OSCCTRL_STATUS_Type::XOSCRDY0
uint32_t XOSCRDY0
Definition: oscctrl.h:314
OSCCTRL_DPLLCTRLB_Type
Definition: oscctrl.h:654
OSCCTRL_INTFLAG_Type::XOSCRDY1
__I uint32_t XOSCRDY1
Definition: oscctrl.h:235
OSCCTRL_INTFLAG_Type::DFLLRDY
__I uint32_t DFLLRDY
Definition: oscctrl.h:239
OSCCTRL_INTENCLR_Type::XOSCFAIL
uint32_t XOSCFAIL
Definition: oscctrl.h:98
OSCCTRL_INTFLAG_Type::XOSCRDY0
__I uint32_t XOSCRDY0
Definition: oscctrl.h:234
OSCCTRL_INTENCLR_Type::DPLL1LCKR
uint32_t DPLL1LCKR
Definition: oscctrl.h:90
OSCCTRL_INTENSET_Type::DPLL1LDRTO
uint32_t DPLL1LDRTO
Definition: oscctrl.h:173
OSCCTRL_STATUS_Type::XOSCFAIL1
uint32_t XOSCFAIL1
Definition: oscctrl.h:317
OSCCTRL_DPLLRATIO_Type::LDRFRAC
uint32_t LDRFRAC
Definition: oscctrl.h:634
OSCCTRL_DFLLMUL_Type::MUL
uint32_t MUL
Definition: oscctrl.h:552
OSCCTRL_XOSCCTRL_Type::ONDEMAND
uint32_t ONDEMAND
Definition: oscctrl.h:409
Oscctrl::INTFLAG
__IO OSCCTRL_INTFLAG_Type INTFLAG
Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear.
Definition: oscctrl.h:776
OSCCTRL_INTFLAG_Type::XOSCFAIL0
__I uint32_t XOSCFAIL0
Definition: oscctrl.h:236