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30 #ifndef _SAME54P19A_PIO_
31 #define _SAME54P19A_PIO_
34 #define PORT_PA00 (_UL_(1) << 0)
36 #define PORT_PA01 (_UL_(1) << 1)
38 #define PORT_PA02 (_UL_(1) << 2)
40 #define PORT_PA03 (_UL_(1) << 3)
42 #define PORT_PA04 (_UL_(1) << 4)
44 #define PORT_PA05 (_UL_(1) << 5)
46 #define PORT_PA06 (_UL_(1) << 6)
48 #define PORT_PA07 (_UL_(1) << 7)
50 #define PORT_PA08 (_UL_(1) << 8)
52 #define PORT_PA09 (_UL_(1) << 9)
54 #define PORT_PA10 (_UL_(1) << 10)
56 #define PORT_PA11 (_UL_(1) << 11)
58 #define PORT_PA12 (_UL_(1) << 12)
60 #define PORT_PA13 (_UL_(1) << 13)
62 #define PORT_PA14 (_UL_(1) << 14)
64 #define PORT_PA15 (_UL_(1) << 15)
66 #define PORT_PA16 (_UL_(1) << 16)
68 #define PORT_PA17 (_UL_(1) << 17)
70 #define PORT_PA18 (_UL_(1) << 18)
72 #define PORT_PA19 (_UL_(1) << 19)
74 #define PORT_PA20 (_UL_(1) << 20)
76 #define PORT_PA21 (_UL_(1) << 21)
78 #define PORT_PA22 (_UL_(1) << 22)
80 #define PORT_PA23 (_UL_(1) << 23)
82 #define PORT_PA24 (_UL_(1) << 24)
84 #define PORT_PA25 (_UL_(1) << 25)
86 #define PORT_PA27 (_UL_(1) << 27)
88 #define PORT_PA30 (_UL_(1) << 30)
90 #define PORT_PA31 (_UL_(1) << 31)
92 #define PORT_PB00 (_UL_(1) << 0)
94 #define PORT_PB01 (_UL_(1) << 1)
96 #define PORT_PB02 (_UL_(1) << 2)
98 #define PORT_PB03 (_UL_(1) << 3)
100 #define PORT_PB04 (_UL_(1) << 4)
102 #define PORT_PB05 (_UL_(1) << 5)
104 #define PORT_PB06 (_UL_(1) << 6)
106 #define PORT_PB07 (_UL_(1) << 7)
108 #define PORT_PB08 (_UL_(1) << 8)
110 #define PORT_PB09 (_UL_(1) << 9)
112 #define PORT_PB10 (_UL_(1) << 10)
114 #define PORT_PB11 (_UL_(1) << 11)
116 #define PORT_PB12 (_UL_(1) << 12)
118 #define PORT_PB13 (_UL_(1) << 13)
120 #define PORT_PB14 (_UL_(1) << 14)
122 #define PORT_PB15 (_UL_(1) << 15)
124 #define PORT_PB16 (_UL_(1) << 16)
126 #define PORT_PB17 (_UL_(1) << 17)
128 #define PORT_PB18 (_UL_(1) << 18)
130 #define PORT_PB19 (_UL_(1) << 19)
132 #define PORT_PB20 (_UL_(1) << 20)
134 #define PORT_PB21 (_UL_(1) << 21)
136 #define PORT_PB22 (_UL_(1) << 22)
138 #define PORT_PB23 (_UL_(1) << 23)
140 #define PORT_PB24 (_UL_(1) << 24)
142 #define PORT_PB25 (_UL_(1) << 25)
144 #define PORT_PB26 (_UL_(1) << 26)
146 #define PORT_PB27 (_UL_(1) << 27)
148 #define PORT_PB28 (_UL_(1) << 28)
150 #define PORT_PB29 (_UL_(1) << 29)
152 #define PORT_PB30 (_UL_(1) << 30)
154 #define PORT_PB31 (_UL_(1) << 31)
156 #define PORT_PC00 (_UL_(1) << 0)
158 #define PORT_PC01 (_UL_(1) << 1)
160 #define PORT_PC02 (_UL_(1) << 2)
162 #define PORT_PC03 (_UL_(1) << 3)
164 #define PORT_PC04 (_UL_(1) << 4)
166 #define PORT_PC05 (_UL_(1) << 5)
168 #define PORT_PC06 (_UL_(1) << 6)
170 #define PORT_PC07 (_UL_(1) << 7)
172 #define PORT_PC10 (_UL_(1) << 10)
174 #define PORT_PC11 (_UL_(1) << 11)
176 #define PORT_PC12 (_UL_(1) << 12)
178 #define PORT_PC13 (_UL_(1) << 13)
180 #define PORT_PC14 (_UL_(1) << 14)
182 #define PORT_PC15 (_UL_(1) << 15)
184 #define PORT_PC16 (_UL_(1) << 16)
186 #define PORT_PC17 (_UL_(1) << 17)
188 #define PORT_PC18 (_UL_(1) << 18)
190 #define PORT_PC19 (_UL_(1) << 19)
192 #define PORT_PC20 (_UL_(1) << 20)
194 #define PORT_PC21 (_UL_(1) << 21)
196 #define PORT_PC22 (_UL_(1) << 22)
198 #define PORT_PC23 (_UL_(1) << 23)
200 #define PORT_PC24 (_UL_(1) << 24)
202 #define PORT_PC25 (_UL_(1) << 25)
204 #define PORT_PC26 (_UL_(1) << 26)
206 #define PORT_PC27 (_UL_(1) << 27)
208 #define PORT_PC28 (_UL_(1) << 28)
210 #define PORT_PC30 (_UL_(1) << 30)
212 #define PORT_PC31 (_UL_(1) << 31)
214 #define PORT_PD00 (_UL_(1) << 0)
216 #define PORT_PD01 (_UL_(1) << 1)
218 #define PORT_PD08 (_UL_(1) << 8)
220 #define PORT_PD09 (_UL_(1) << 9)
222 #define PORT_PD10 (_UL_(1) << 10)
224 #define PORT_PD11 (_UL_(1) << 11)
226 #define PORT_PD12 (_UL_(1) << 12)
228 #define PORT_PD20 (_UL_(1) << 20)
230 #define PORT_PD21 (_UL_(1) << 21)
232 #define PIN_PA30H_CM4_SWCLK _L_(30)
233 #define MUX_PA30H_CM4_SWCLK _L_(7)
234 #define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK)
235 #define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30)
236 #define PIN_PC27M_CM4_SWO _L_(91)
237 #define MUX_PC27M_CM4_SWO _L_(12)
238 #define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO)
239 #define PORT_PC27M_CM4_SWO (_UL_(1) << 27)
240 #define PIN_PB30H_CM4_SWO _L_(62)
241 #define MUX_PB30H_CM4_SWO _L_(7)
242 #define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO)
243 #define PORT_PB30H_CM4_SWO (_UL_(1) << 30)
244 #define PIN_PC27H_CM4_TRACECLK _L_(91)
245 #define MUX_PC27H_CM4_TRACECLK _L_(7)
246 #define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK)
247 #define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27)
248 #define PIN_PC28H_CM4_TRACEDATA0 _L_(92)
249 #define MUX_PC28H_CM4_TRACEDATA0 _L_(7)
250 #define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0)
251 #define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28)
252 #define PIN_PC26H_CM4_TRACEDATA1 _L_(90)
253 #define MUX_PC26H_CM4_TRACEDATA1 _L_(7)
254 #define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1)
255 #define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26)
256 #define PIN_PC25H_CM4_TRACEDATA2 _L_(89)
257 #define MUX_PC25H_CM4_TRACEDATA2 _L_(7)
258 #define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2)
259 #define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25)
260 #define PIN_PC24H_CM4_TRACEDATA3 _L_(88)
261 #define MUX_PC24H_CM4_TRACEDATA3 _L_(7)
262 #define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3)
263 #define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24)
265 #define PIN_PA03B_ANAREF_VREF0 _L_(3)
266 #define MUX_PA03B_ANAREF_VREF0 _L_(1)
267 #define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0)
268 #define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3)
269 #define PIN_PA04B_ANAREF_VREF1 _L_(4)
270 #define MUX_PA04B_ANAREF_VREF1 _L_(1)
271 #define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1)
272 #define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4)
273 #define PIN_PA06B_ANAREF_VREF2 _L_(6)
274 #define MUX_PA06B_ANAREF_VREF2 _L_(1)
275 #define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2)
276 #define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6)
278 #define PIN_PA30M_GCLK_IO0 _L_(30)
279 #define MUX_PA30M_GCLK_IO0 _L_(12)
280 #define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0)
281 #define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30)
282 #define PIN_PB14M_GCLK_IO0 _L_(46)
283 #define MUX_PB14M_GCLK_IO0 _L_(12)
284 #define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0)
285 #define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14)
286 #define PIN_PA14M_GCLK_IO0 _L_(14)
287 #define MUX_PA14M_GCLK_IO0 _L_(12)
288 #define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0)
289 #define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14)
290 #define PIN_PB22M_GCLK_IO0 _L_(54)
291 #define MUX_PB22M_GCLK_IO0 _L_(12)
292 #define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0)
293 #define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22)
294 #define PIN_PB15M_GCLK_IO1 _L_(47)
295 #define MUX_PB15M_GCLK_IO1 _L_(12)
296 #define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1)
297 #define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15)
298 #define PIN_PA15M_GCLK_IO1 _L_(15)
299 #define MUX_PA15M_GCLK_IO1 _L_(12)
300 #define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1)
301 #define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15)
302 #define PIN_PB23M_GCLK_IO1 _L_(55)
303 #define MUX_PB23M_GCLK_IO1 _L_(12)
304 #define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1)
305 #define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23)
306 #define PIN_PA27M_GCLK_IO1 _L_(27)
307 #define MUX_PA27M_GCLK_IO1 _L_(12)
308 #define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1)
309 #define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27)
310 #define PIN_PA16M_GCLK_IO2 _L_(16)
311 #define MUX_PA16M_GCLK_IO2 _L_(12)
312 #define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2)
313 #define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16)
314 #define PIN_PB16M_GCLK_IO2 _L_(48)
315 #define MUX_PB16M_GCLK_IO2 _L_(12)
316 #define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2)
317 #define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16)
318 #define PIN_PA17M_GCLK_IO3 _L_(17)
319 #define MUX_PA17M_GCLK_IO3 _L_(12)
320 #define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3)
321 #define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17)
322 #define PIN_PB17M_GCLK_IO3 _L_(49)
323 #define MUX_PB17M_GCLK_IO3 _L_(12)
324 #define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3)
325 #define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17)
326 #define PIN_PA10M_GCLK_IO4 _L_(10)
327 #define MUX_PA10M_GCLK_IO4 _L_(12)
328 #define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4)
329 #define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10)
330 #define PIN_PB10M_GCLK_IO4 _L_(42)
331 #define MUX_PB10M_GCLK_IO4 _L_(12)
332 #define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4)
333 #define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10)
334 #define PIN_PB18M_GCLK_IO4 _L_(50)
335 #define MUX_PB18M_GCLK_IO4 _L_(12)
336 #define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4)
337 #define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18)
338 #define PIN_PA11M_GCLK_IO5 _L_(11)
339 #define MUX_PA11M_GCLK_IO5 _L_(12)
340 #define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5)
341 #define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11)
342 #define PIN_PB11M_GCLK_IO5 _L_(43)
343 #define MUX_PB11M_GCLK_IO5 _L_(12)
344 #define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5)
345 #define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11)
346 #define PIN_PB19M_GCLK_IO5 _L_(51)
347 #define MUX_PB19M_GCLK_IO5 _L_(12)
348 #define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5)
349 #define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19)
350 #define PIN_PB12M_GCLK_IO6 _L_(44)
351 #define MUX_PB12M_GCLK_IO6 _L_(12)
352 #define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6)
353 #define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12)
354 #define PIN_PB20M_GCLK_IO6 _L_(52)
355 #define MUX_PB20M_GCLK_IO6 _L_(12)
356 #define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6)
357 #define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20)
358 #define PIN_PB13M_GCLK_IO7 _L_(45)
359 #define MUX_PB13M_GCLK_IO7 _L_(12)
360 #define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7)
361 #define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13)
362 #define PIN_PB21M_GCLK_IO7 _L_(53)
363 #define MUX_PB21M_GCLK_IO7 _L_(12)
364 #define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7)
365 #define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21)
367 #define PIN_PA00A_EIC_EXTINT0 _L_(0)
368 #define MUX_PA00A_EIC_EXTINT0 _L_(0)
369 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
370 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
371 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0)
372 #define PIN_PA16A_EIC_EXTINT0 _L_(16)
373 #define MUX_PA16A_EIC_EXTINT0 _L_(0)
374 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
375 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
376 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0)
377 #define PIN_PB00A_EIC_EXTINT0 _L_(32)
378 #define MUX_PB00A_EIC_EXTINT0 _L_(0)
379 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0)
380 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0)
381 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0)
382 #define PIN_PB16A_EIC_EXTINT0 _L_(48)
383 #define MUX_PB16A_EIC_EXTINT0 _L_(0)
384 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0)
385 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16)
386 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0)
387 #define PIN_PC00A_EIC_EXTINT0 _L_(64)
388 #define MUX_PC00A_EIC_EXTINT0 _L_(0)
389 #define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0)
390 #define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0)
391 #define PIN_PC00A_EIC_EXTINT_NUM _L_(0)
392 #define PIN_PC16A_EIC_EXTINT0 _L_(80)
393 #define MUX_PC16A_EIC_EXTINT0 _L_(0)
394 #define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0)
395 #define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16)
396 #define PIN_PC16A_EIC_EXTINT_NUM _L_(0)
397 #define PIN_PD00A_EIC_EXTINT0 _L_(96)
398 #define MUX_PD00A_EIC_EXTINT0 _L_(0)
399 #define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0)
400 #define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0)
401 #define PIN_PD00A_EIC_EXTINT_NUM _L_(0)
402 #define PIN_PA01A_EIC_EXTINT1 _L_(1)
403 #define MUX_PA01A_EIC_EXTINT1 _L_(0)
404 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
405 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
406 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1)
407 #define PIN_PA17A_EIC_EXTINT1 _L_(17)
408 #define MUX_PA17A_EIC_EXTINT1 _L_(0)
409 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
410 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
411 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1)
412 #define PIN_PB01A_EIC_EXTINT1 _L_(33)
413 #define MUX_PB01A_EIC_EXTINT1 _L_(0)
414 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1)
415 #define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1)
416 #define PIN_PB01A_EIC_EXTINT_NUM _L_(1)
417 #define PIN_PB17A_EIC_EXTINT1 _L_(49)
418 #define MUX_PB17A_EIC_EXTINT1 _L_(0)
419 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1)
420 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17)
421 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1)
422 #define PIN_PC01A_EIC_EXTINT1 _L_(65)
423 #define MUX_PC01A_EIC_EXTINT1 _L_(0)
424 #define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1)
425 #define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1)
426 #define PIN_PC01A_EIC_EXTINT_NUM _L_(1)
427 #define PIN_PC17A_EIC_EXTINT1 _L_(81)
428 #define MUX_PC17A_EIC_EXTINT1 _L_(0)
429 #define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1)
430 #define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17)
431 #define PIN_PC17A_EIC_EXTINT_NUM _L_(1)
432 #define PIN_PD01A_EIC_EXTINT1 _L_(97)
433 #define MUX_PD01A_EIC_EXTINT1 _L_(0)
434 #define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1)
435 #define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1)
436 #define PIN_PD01A_EIC_EXTINT_NUM _L_(1)
437 #define PIN_PA02A_EIC_EXTINT2 _L_(2)
438 #define MUX_PA02A_EIC_EXTINT2 _L_(0)
439 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
440 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
441 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2)
442 #define PIN_PA18A_EIC_EXTINT2 _L_(18)
443 #define MUX_PA18A_EIC_EXTINT2 _L_(0)
444 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
445 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
446 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2)
447 #define PIN_PB02A_EIC_EXTINT2 _L_(34)
448 #define MUX_PB02A_EIC_EXTINT2 _L_(0)
449 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2)
450 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2)
451 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2)
452 #define PIN_PB18A_EIC_EXTINT2 _L_(50)
453 #define MUX_PB18A_EIC_EXTINT2 _L_(0)
454 #define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2)
455 #define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18)
456 #define PIN_PB18A_EIC_EXTINT_NUM _L_(2)
457 #define PIN_PC02A_EIC_EXTINT2 _L_(66)
458 #define MUX_PC02A_EIC_EXTINT2 _L_(0)
459 #define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2)
460 #define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2)
461 #define PIN_PC02A_EIC_EXTINT_NUM _L_(2)
462 #define PIN_PC18A_EIC_EXTINT2 _L_(82)
463 #define MUX_PC18A_EIC_EXTINT2 _L_(0)
464 #define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2)
465 #define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18)
466 #define PIN_PC18A_EIC_EXTINT_NUM _L_(2)
467 #define PIN_PA03A_EIC_EXTINT3 _L_(3)
468 #define MUX_PA03A_EIC_EXTINT3 _L_(0)
469 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
470 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
471 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3)
472 #define PIN_PA19A_EIC_EXTINT3 _L_(19)
473 #define MUX_PA19A_EIC_EXTINT3 _L_(0)
474 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
475 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
476 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3)
477 #define PIN_PB03A_EIC_EXTINT3 _L_(35)
478 #define MUX_PB03A_EIC_EXTINT3 _L_(0)
479 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3)
480 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3)
481 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3)
482 #define PIN_PB19A_EIC_EXTINT3 _L_(51)
483 #define MUX_PB19A_EIC_EXTINT3 _L_(0)
484 #define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3)
485 #define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19)
486 #define PIN_PB19A_EIC_EXTINT_NUM _L_(3)
487 #define PIN_PC03A_EIC_EXTINT3 _L_(67)
488 #define MUX_PC03A_EIC_EXTINT3 _L_(0)
489 #define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3)
490 #define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3)
491 #define PIN_PC03A_EIC_EXTINT_NUM _L_(3)
492 #define PIN_PC19A_EIC_EXTINT3 _L_(83)
493 #define MUX_PC19A_EIC_EXTINT3 _L_(0)
494 #define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3)
495 #define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19)
496 #define PIN_PC19A_EIC_EXTINT_NUM _L_(3)
497 #define PIN_PD08A_EIC_EXTINT3 _L_(104)
498 #define MUX_PD08A_EIC_EXTINT3 _L_(0)
499 #define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3)
500 #define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8)
501 #define PIN_PD08A_EIC_EXTINT_NUM _L_(3)
502 #define PIN_PA04A_EIC_EXTINT4 _L_(4)
503 #define MUX_PA04A_EIC_EXTINT4 _L_(0)
504 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
505 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
506 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4)
507 #define PIN_PA20A_EIC_EXTINT4 _L_(20)
508 #define MUX_PA20A_EIC_EXTINT4 _L_(0)
509 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4)
510 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20)
511 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4)
512 #define PIN_PB04A_EIC_EXTINT4 _L_(36)
513 #define MUX_PB04A_EIC_EXTINT4 _L_(0)
514 #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4)
515 #define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4)
516 #define PIN_PB04A_EIC_EXTINT_NUM _L_(4)
517 #define PIN_PB20A_EIC_EXTINT4 _L_(52)
518 #define MUX_PB20A_EIC_EXTINT4 _L_(0)
519 #define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4)
520 #define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20)
521 #define PIN_PB20A_EIC_EXTINT_NUM _L_(4)
522 #define PIN_PC04A_EIC_EXTINT4 _L_(68)
523 #define MUX_PC04A_EIC_EXTINT4 _L_(0)
524 #define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4)
525 #define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4)
526 #define PIN_PC04A_EIC_EXTINT_NUM _L_(4)
527 #define PIN_PC20A_EIC_EXTINT4 _L_(84)
528 #define MUX_PC20A_EIC_EXTINT4 _L_(0)
529 #define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4)
530 #define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20)
531 #define PIN_PC20A_EIC_EXTINT_NUM _L_(4)
532 #define PIN_PD09A_EIC_EXTINT4 _L_(105)
533 #define MUX_PD09A_EIC_EXTINT4 _L_(0)
534 #define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4)
535 #define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9)
536 #define PIN_PD09A_EIC_EXTINT_NUM _L_(4)
537 #define PIN_PA05A_EIC_EXTINT5 _L_(5)
538 #define MUX_PA05A_EIC_EXTINT5 _L_(0)
539 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
540 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
541 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5)
542 #define PIN_PA21A_EIC_EXTINT5 _L_(21)
543 #define MUX_PA21A_EIC_EXTINT5 _L_(0)
544 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5)
545 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21)
546 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5)
547 #define PIN_PB05A_EIC_EXTINT5 _L_(37)
548 #define MUX_PB05A_EIC_EXTINT5 _L_(0)
549 #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5)
550 #define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5)
551 #define PIN_PB05A_EIC_EXTINT_NUM _L_(5)
552 #define PIN_PB21A_EIC_EXTINT5 _L_(53)
553 #define MUX_PB21A_EIC_EXTINT5 _L_(0)
554 #define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5)
555 #define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21)
556 #define PIN_PB21A_EIC_EXTINT_NUM _L_(5)
557 #define PIN_PC05A_EIC_EXTINT5 _L_(69)
558 #define MUX_PC05A_EIC_EXTINT5 _L_(0)
559 #define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5)
560 #define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5)
561 #define PIN_PC05A_EIC_EXTINT_NUM _L_(5)
562 #define PIN_PC21A_EIC_EXTINT5 _L_(85)
563 #define MUX_PC21A_EIC_EXTINT5 _L_(0)
564 #define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5)
565 #define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21)
566 #define PIN_PC21A_EIC_EXTINT_NUM _L_(5)
567 #define PIN_PD10A_EIC_EXTINT5 _L_(106)
568 #define MUX_PD10A_EIC_EXTINT5 _L_(0)
569 #define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5)
570 #define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10)
571 #define PIN_PD10A_EIC_EXTINT_NUM _L_(5)
572 #define PIN_PA06A_EIC_EXTINT6 _L_(6)
573 #define MUX_PA06A_EIC_EXTINT6 _L_(0)
574 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
575 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
576 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6)
577 #define PIN_PA22A_EIC_EXTINT6 _L_(22)
578 #define MUX_PA22A_EIC_EXTINT6 _L_(0)
579 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
580 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
581 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6)
582 #define PIN_PB06A_EIC_EXTINT6 _L_(38)
583 #define MUX_PB06A_EIC_EXTINT6 _L_(0)
584 #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6)
585 #define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6)
586 #define PIN_PB06A_EIC_EXTINT_NUM _L_(6)
587 #define PIN_PB22A_EIC_EXTINT6 _L_(54)
588 #define MUX_PB22A_EIC_EXTINT6 _L_(0)
589 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6)
590 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22)
591 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6)
592 #define PIN_PC06A_EIC_EXTINT6 _L_(70)
593 #define MUX_PC06A_EIC_EXTINT6 _L_(0)
594 #define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6)
595 #define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6)
596 #define PIN_PC06A_EIC_EXTINT_NUM _L_(6)
597 #define PIN_PC22A_EIC_EXTINT6 _L_(86)
598 #define MUX_PC22A_EIC_EXTINT6 _L_(0)
599 #define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6)
600 #define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22)
601 #define PIN_PC22A_EIC_EXTINT_NUM _L_(6)
602 #define PIN_PD11A_EIC_EXTINT6 _L_(107)
603 #define MUX_PD11A_EIC_EXTINT6 _L_(0)
604 #define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6)
605 #define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11)
606 #define PIN_PD11A_EIC_EXTINT_NUM _L_(6)
607 #define PIN_PA07A_EIC_EXTINT7 _L_(7)
608 #define MUX_PA07A_EIC_EXTINT7 _L_(0)
609 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
610 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
611 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7)
612 #define PIN_PA23A_EIC_EXTINT7 _L_(23)
613 #define MUX_PA23A_EIC_EXTINT7 _L_(0)
614 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
615 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
616 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7)
617 #define PIN_PB07A_EIC_EXTINT7 _L_(39)
618 #define MUX_PB07A_EIC_EXTINT7 _L_(0)
619 #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7)
620 #define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7)
621 #define PIN_PB07A_EIC_EXTINT_NUM _L_(7)
622 #define PIN_PB23A_EIC_EXTINT7 _L_(55)
623 #define MUX_PB23A_EIC_EXTINT7 _L_(0)
624 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7)
625 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23)
626 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7)
627 #define PIN_PC23A_EIC_EXTINT7 _L_(87)
628 #define MUX_PC23A_EIC_EXTINT7 _L_(0)
629 #define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7)
630 #define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23)
631 #define PIN_PC23A_EIC_EXTINT_NUM _L_(7)
632 #define PIN_PD12A_EIC_EXTINT7 _L_(108)
633 #define MUX_PD12A_EIC_EXTINT7 _L_(0)
634 #define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7)
635 #define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12)
636 #define PIN_PD12A_EIC_EXTINT_NUM _L_(7)
637 #define PIN_PA24A_EIC_EXTINT8 _L_(24)
638 #define MUX_PA24A_EIC_EXTINT8 _L_(0)
639 #define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8)
640 #define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24)
641 #define PIN_PA24A_EIC_EXTINT_NUM _L_(8)
642 #define PIN_PB08A_EIC_EXTINT8 _L_(40)
643 #define MUX_PB08A_EIC_EXTINT8 _L_(0)
644 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8)
645 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8)
646 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8)
647 #define PIN_PB24A_EIC_EXTINT8 _L_(56)
648 #define MUX_PB24A_EIC_EXTINT8 _L_(0)
649 #define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8)
650 #define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24)
651 #define PIN_PB24A_EIC_EXTINT_NUM _L_(8)
652 #define PIN_PC24A_EIC_EXTINT8 _L_(88)
653 #define MUX_PC24A_EIC_EXTINT8 _L_(0)
654 #define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8)
655 #define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24)
656 #define PIN_PC24A_EIC_EXTINT_NUM _L_(8)
657 #define PIN_PA09A_EIC_EXTINT9 _L_(9)
658 #define MUX_PA09A_EIC_EXTINT9 _L_(0)
659 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
660 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
661 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9)
662 #define PIN_PA25A_EIC_EXTINT9 _L_(25)
663 #define MUX_PA25A_EIC_EXTINT9 _L_(0)
664 #define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9)
665 #define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25)
666 #define PIN_PA25A_EIC_EXTINT_NUM _L_(9)
667 #define PIN_PB09A_EIC_EXTINT9 _L_(41)
668 #define MUX_PB09A_EIC_EXTINT9 _L_(0)
669 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9)
670 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9)
671 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9)
672 #define PIN_PB25A_EIC_EXTINT9 _L_(57)
673 #define MUX_PB25A_EIC_EXTINT9 _L_(0)
674 #define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9)
675 #define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25)
676 #define PIN_PB25A_EIC_EXTINT_NUM _L_(9)
677 #define PIN_PC07A_EIC_EXTINT9 _L_(71)
678 #define MUX_PC07A_EIC_EXTINT9 _L_(0)
679 #define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9)
680 #define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7)
681 #define PIN_PC07A_EIC_EXTINT_NUM _L_(9)
682 #define PIN_PC25A_EIC_EXTINT9 _L_(89)
683 #define MUX_PC25A_EIC_EXTINT9 _L_(0)
684 #define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9)
685 #define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25)
686 #define PIN_PC25A_EIC_EXTINT_NUM _L_(9)
687 #define PIN_PA10A_EIC_EXTINT10 _L_(10)
688 #define MUX_PA10A_EIC_EXTINT10 _L_(0)
689 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
690 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
691 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10)
692 #define PIN_PB10A_EIC_EXTINT10 _L_(42)
693 #define MUX_PB10A_EIC_EXTINT10 _L_(0)
694 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10)
695 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10)
696 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10)
697 #define PIN_PC10A_EIC_EXTINT10 _L_(74)
698 #define MUX_PC10A_EIC_EXTINT10 _L_(0)
699 #define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10)
700 #define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10)
701 #define PIN_PC10A_EIC_EXTINT_NUM _L_(10)
702 #define PIN_PC26A_EIC_EXTINT10 _L_(90)
703 #define MUX_PC26A_EIC_EXTINT10 _L_(0)
704 #define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10)
705 #define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26)
706 #define PIN_PC26A_EIC_EXTINT_NUM _L_(10)
707 #define PIN_PD20A_EIC_EXTINT10 _L_(116)
708 #define MUX_PD20A_EIC_EXTINT10 _L_(0)
709 #define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10)
710 #define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20)
711 #define PIN_PD20A_EIC_EXTINT_NUM _L_(10)
712 #define PIN_PA11A_EIC_EXTINT11 _L_(11)
713 #define MUX_PA11A_EIC_EXTINT11 _L_(0)
714 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
715 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
716 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11)
717 #define PIN_PA27A_EIC_EXTINT11 _L_(27)
718 #define MUX_PA27A_EIC_EXTINT11 _L_(0)
719 #define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11)
720 #define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27)
721 #define PIN_PA27A_EIC_EXTINT_NUM _L_(11)
722 #define PIN_PB11A_EIC_EXTINT11 _L_(43)
723 #define MUX_PB11A_EIC_EXTINT11 _L_(0)
724 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11)
725 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11)
726 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11)
727 #define PIN_PC11A_EIC_EXTINT11 _L_(75)
728 #define MUX_PC11A_EIC_EXTINT11 _L_(0)
729 #define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11)
730 #define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11)
731 #define PIN_PC11A_EIC_EXTINT_NUM _L_(11)
732 #define PIN_PC27A_EIC_EXTINT11 _L_(91)
733 #define MUX_PC27A_EIC_EXTINT11 _L_(0)
734 #define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11)
735 #define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27)
736 #define PIN_PC27A_EIC_EXTINT_NUM _L_(11)
737 #define PIN_PD21A_EIC_EXTINT11 _L_(117)
738 #define MUX_PD21A_EIC_EXTINT11 _L_(0)
739 #define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11)
740 #define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21)
741 #define PIN_PD21A_EIC_EXTINT_NUM _L_(11)
742 #define PIN_PA12A_EIC_EXTINT12 _L_(12)
743 #define MUX_PA12A_EIC_EXTINT12 _L_(0)
744 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12)
745 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12)
746 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12)
747 #define PIN_PB12A_EIC_EXTINT12 _L_(44)
748 #define MUX_PB12A_EIC_EXTINT12 _L_(0)
749 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12)
750 #define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12)
751 #define PIN_PB12A_EIC_EXTINT_NUM _L_(12)
752 #define PIN_PB26A_EIC_EXTINT12 _L_(58)
753 #define MUX_PB26A_EIC_EXTINT12 _L_(0)
754 #define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12)
755 #define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26)
756 #define PIN_PB26A_EIC_EXTINT_NUM _L_(12)
757 #define PIN_PC12A_EIC_EXTINT12 _L_(76)
758 #define MUX_PC12A_EIC_EXTINT12 _L_(0)
759 #define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12)
760 #define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12)
761 #define PIN_PC12A_EIC_EXTINT_NUM _L_(12)
762 #define PIN_PC28A_EIC_EXTINT12 _L_(92)
763 #define MUX_PC28A_EIC_EXTINT12 _L_(0)
764 #define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12)
765 #define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28)
766 #define PIN_PC28A_EIC_EXTINT_NUM _L_(12)
767 #define PIN_PA13A_EIC_EXTINT13 _L_(13)
768 #define MUX_PA13A_EIC_EXTINT13 _L_(0)
769 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13)
770 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13)
771 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13)
772 #define PIN_PB13A_EIC_EXTINT13 _L_(45)
773 #define MUX_PB13A_EIC_EXTINT13 _L_(0)
774 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13)
775 #define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13)
776 #define PIN_PB13A_EIC_EXTINT_NUM _L_(13)
777 #define PIN_PB27A_EIC_EXTINT13 _L_(59)
778 #define MUX_PB27A_EIC_EXTINT13 _L_(0)
779 #define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13)
780 #define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27)
781 #define PIN_PB27A_EIC_EXTINT_NUM _L_(13)
782 #define PIN_PC13A_EIC_EXTINT13 _L_(77)
783 #define MUX_PC13A_EIC_EXTINT13 _L_(0)
784 #define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13)
785 #define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13)
786 #define PIN_PC13A_EIC_EXTINT_NUM _L_(13)
787 #define PIN_PA30A_EIC_EXTINT14 _L_(30)
788 #define MUX_PA30A_EIC_EXTINT14 _L_(0)
789 #define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14)
790 #define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30)
791 #define PIN_PA30A_EIC_EXTINT_NUM _L_(14)
792 #define PIN_PB14A_EIC_EXTINT14 _L_(46)
793 #define MUX_PB14A_EIC_EXTINT14 _L_(0)
794 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14)
795 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14)
796 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14)
797 #define PIN_PB28A_EIC_EXTINT14 _L_(60)
798 #define MUX_PB28A_EIC_EXTINT14 _L_(0)
799 #define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14)
800 #define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28)
801 #define PIN_PB28A_EIC_EXTINT_NUM _L_(14)
802 #define PIN_PB30A_EIC_EXTINT14 _L_(62)
803 #define MUX_PB30A_EIC_EXTINT14 _L_(0)
804 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14)
805 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30)
806 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14)
807 #define PIN_PC14A_EIC_EXTINT14 _L_(78)
808 #define MUX_PC14A_EIC_EXTINT14 _L_(0)
809 #define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14)
810 #define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14)
811 #define PIN_PC14A_EIC_EXTINT_NUM _L_(14)
812 #define PIN_PC30A_EIC_EXTINT14 _L_(94)
813 #define MUX_PC30A_EIC_EXTINT14 _L_(0)
814 #define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14)
815 #define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30)
816 #define PIN_PC30A_EIC_EXTINT_NUM _L_(14)
817 #define PIN_PA14A_EIC_EXTINT14 _L_(14)
818 #define MUX_PA14A_EIC_EXTINT14 _L_(0)
819 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
820 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
821 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14)
822 #define PIN_PA15A_EIC_EXTINT15 _L_(15)
823 #define MUX_PA15A_EIC_EXTINT15 _L_(0)
824 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
825 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
826 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15)
827 #define PIN_PA31A_EIC_EXTINT15 _L_(31)
828 #define MUX_PA31A_EIC_EXTINT15 _L_(0)
829 #define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15)
830 #define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31)
831 #define PIN_PA31A_EIC_EXTINT_NUM _L_(15)
832 #define PIN_PB15A_EIC_EXTINT15 _L_(47)
833 #define MUX_PB15A_EIC_EXTINT15 _L_(0)
834 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15)
835 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15)
836 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15)
837 #define PIN_PB29A_EIC_EXTINT15 _L_(61)
838 #define MUX_PB29A_EIC_EXTINT15 _L_(0)
839 #define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15)
840 #define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29)
841 #define PIN_PB29A_EIC_EXTINT_NUM _L_(15)
842 #define PIN_PB31A_EIC_EXTINT15 _L_(63)
843 #define MUX_PB31A_EIC_EXTINT15 _L_(0)
844 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15)
845 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31)
846 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15)
847 #define PIN_PC15A_EIC_EXTINT15 _L_(79)
848 #define MUX_PC15A_EIC_EXTINT15 _L_(0)
849 #define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15)
850 #define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15)
851 #define PIN_PC15A_EIC_EXTINT_NUM _L_(15)
852 #define PIN_PC31A_EIC_EXTINT15 _L_(95)
853 #define MUX_PC31A_EIC_EXTINT15 _L_(0)
854 #define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15)
855 #define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31)
856 #define PIN_PC31A_EIC_EXTINT_NUM _L_(15)
857 #define PIN_PA08A_EIC_NMI _L_(8)
858 #define MUX_PA08A_EIC_NMI _L_(0)
859 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
860 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
862 #define PIN_PA04D_SERCOM0_PAD0 _L_(4)
863 #define MUX_PA04D_SERCOM0_PAD0 _L_(3)
864 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
865 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
866 #define PIN_PC17D_SERCOM0_PAD0 _L_(81)
867 #define MUX_PC17D_SERCOM0_PAD0 _L_(3)
868 #define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0)
869 #define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17)
870 #define PIN_PA08C_SERCOM0_PAD0 _L_(8)
871 #define MUX_PA08C_SERCOM0_PAD0 _L_(2)
872 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
873 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
874 #define PIN_PB24C_SERCOM0_PAD0 _L_(56)
875 #define MUX_PB24C_SERCOM0_PAD0 _L_(2)
876 #define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0)
877 #define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24)
878 #define PIN_PA05D_SERCOM0_PAD1 _L_(5)
879 #define MUX_PA05D_SERCOM0_PAD1 _L_(3)
880 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
881 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
882 #define PIN_PC16D_SERCOM0_PAD1 _L_(80)
883 #define MUX_PC16D_SERCOM0_PAD1 _L_(3)
884 #define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1)
885 #define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16)
886 #define PIN_PA09C_SERCOM0_PAD1 _L_(9)
887 #define MUX_PA09C_SERCOM0_PAD1 _L_(2)
888 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
889 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
890 #define PIN_PB25C_SERCOM0_PAD1 _L_(57)
891 #define MUX_PB25C_SERCOM0_PAD1 _L_(2)
892 #define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1)
893 #define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25)
894 #define PIN_PA06D_SERCOM0_PAD2 _L_(6)
895 #define MUX_PA06D_SERCOM0_PAD2 _L_(3)
896 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
897 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
898 #define PIN_PC18D_SERCOM0_PAD2 _L_(82)
899 #define MUX_PC18D_SERCOM0_PAD2 _L_(3)
900 #define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2)
901 #define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18)
902 #define PIN_PA10C_SERCOM0_PAD2 _L_(10)
903 #define MUX_PA10C_SERCOM0_PAD2 _L_(2)
904 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
905 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
906 #define PIN_PC24C_SERCOM0_PAD2 _L_(88)
907 #define MUX_PC24C_SERCOM0_PAD2 _L_(2)
908 #define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2)
909 #define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24)
910 #define PIN_PA07D_SERCOM0_PAD3 _L_(7)
911 #define MUX_PA07D_SERCOM0_PAD3 _L_(3)
912 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
913 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
914 #define PIN_PC19D_SERCOM0_PAD3 _L_(83)
915 #define MUX_PC19D_SERCOM0_PAD3 _L_(3)
916 #define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3)
917 #define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19)
918 #define PIN_PA11C_SERCOM0_PAD3 _L_(11)
919 #define MUX_PA11C_SERCOM0_PAD3 _L_(2)
920 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
921 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
922 #define PIN_PC25C_SERCOM0_PAD3 _L_(89)
923 #define MUX_PC25C_SERCOM0_PAD3 _L_(2)
924 #define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3)
925 #define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25)
927 #define PIN_PA00D_SERCOM1_PAD0 _L_(0)
928 #define MUX_PA00D_SERCOM1_PAD0 _L_(3)
929 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
930 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
931 #define PIN_PA16C_SERCOM1_PAD0 _L_(16)
932 #define MUX_PA16C_SERCOM1_PAD0 _L_(2)
933 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
934 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
935 #define PIN_PC22C_SERCOM1_PAD0 _L_(86)
936 #define MUX_PC22C_SERCOM1_PAD0 _L_(2)
937 #define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0)
938 #define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22)
939 #define PIN_PC27C_SERCOM1_PAD0 _L_(91)
940 #define MUX_PC27C_SERCOM1_PAD0 _L_(2)
941 #define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0)
942 #define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27)
943 #define PIN_PA01D_SERCOM1_PAD1 _L_(1)
944 #define MUX_PA01D_SERCOM1_PAD1 _L_(3)
945 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
946 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
947 #define PIN_PA17C_SERCOM1_PAD1 _L_(17)
948 #define MUX_PA17C_SERCOM1_PAD1 _L_(2)
949 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
950 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
951 #define PIN_PC23C_SERCOM1_PAD1 _L_(87)
952 #define MUX_PC23C_SERCOM1_PAD1 _L_(2)
953 #define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1)
954 #define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23)
955 #define PIN_PC28C_SERCOM1_PAD1 _L_(92)
956 #define MUX_PC28C_SERCOM1_PAD1 _L_(2)
957 #define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1)
958 #define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28)
959 #define PIN_PA30D_SERCOM1_PAD2 _L_(30)
960 #define MUX_PA30D_SERCOM1_PAD2 _L_(3)
961 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
962 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
963 #define PIN_PA18C_SERCOM1_PAD2 _L_(18)
964 #define MUX_PA18C_SERCOM1_PAD2 _L_(2)
965 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
966 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
967 #define PIN_PB22C_SERCOM1_PAD2 _L_(54)
968 #define MUX_PB22C_SERCOM1_PAD2 _L_(2)
969 #define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2)
970 #define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22)
971 #define PIN_PD20C_SERCOM1_PAD2 _L_(116)
972 #define MUX_PD20C_SERCOM1_PAD2 _L_(2)
973 #define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2)
974 #define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20)
975 #define PIN_PA31D_SERCOM1_PAD3 _L_(31)
976 #define MUX_PA31D_SERCOM1_PAD3 _L_(3)
977 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
978 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
979 #define PIN_PA19C_SERCOM1_PAD3 _L_(19)
980 #define MUX_PA19C_SERCOM1_PAD3 _L_(2)
981 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
982 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
983 #define PIN_PB23C_SERCOM1_PAD3 _L_(55)
984 #define MUX_PB23C_SERCOM1_PAD3 _L_(2)
985 #define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3)
986 #define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23)
987 #define PIN_PD21C_SERCOM1_PAD3 _L_(117)
988 #define MUX_PD21C_SERCOM1_PAD3 _L_(2)
989 #define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3)
990 #define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21)
992 #define PIN_PA04E_TC0_WO0 _L_(4)
993 #define MUX_PA04E_TC0_WO0 _L_(4)
994 #define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0)
995 #define PORT_PA04E_TC0_WO0 (_UL_(1) << 4)
996 #define PIN_PA08E_TC0_WO0 _L_(8)
997 #define MUX_PA08E_TC0_WO0 _L_(4)
998 #define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0)
999 #define PORT_PA08E_TC0_WO0 (_UL_(1) << 8)
1000 #define PIN_PB30E_TC0_WO0 _L_(62)
1001 #define MUX_PB30E_TC0_WO0 _L_(4)
1002 #define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0)
1003 #define PORT_PB30E_TC0_WO0 (_UL_(1) << 30)
1004 #define PIN_PA05E_TC0_WO1 _L_(5)
1005 #define MUX_PA05E_TC0_WO1 _L_(4)
1006 #define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1)
1007 #define PORT_PA05E_TC0_WO1 (_UL_(1) << 5)
1008 #define PIN_PA09E_TC0_WO1 _L_(9)
1009 #define MUX_PA09E_TC0_WO1 _L_(4)
1010 #define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1)
1011 #define PORT_PA09E_TC0_WO1 (_UL_(1) << 9)
1012 #define PIN_PB31E_TC0_WO1 _L_(63)
1013 #define MUX_PB31E_TC0_WO1 _L_(4)
1014 #define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1)
1015 #define PORT_PB31E_TC0_WO1 (_UL_(1) << 31)
1017 #define PIN_PA06E_TC1_WO0 _L_(6)
1018 #define MUX_PA06E_TC1_WO0 _L_(4)
1019 #define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0)
1020 #define PORT_PA06E_TC1_WO0 (_UL_(1) << 6)
1021 #define PIN_PA10E_TC1_WO0 _L_(10)
1022 #define MUX_PA10E_TC1_WO0 _L_(4)
1023 #define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0)
1024 #define PORT_PA10E_TC1_WO0 (_UL_(1) << 10)
1025 #define PIN_PA07E_TC1_WO1 _L_(7)
1026 #define MUX_PA07E_TC1_WO1 _L_(4)
1027 #define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1)
1028 #define PORT_PA07E_TC1_WO1 (_UL_(1) << 7)
1029 #define PIN_PA11E_TC1_WO1 _L_(11)
1030 #define MUX_PA11E_TC1_WO1 _L_(4)
1031 #define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1)
1032 #define PORT_PA11E_TC1_WO1 (_UL_(1) << 11)
1034 #define PIN_PA24H_USB_DM _L_(24)
1035 #define MUX_PA24H_USB_DM _L_(7)
1036 #define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM)
1037 #define PORT_PA24H_USB_DM (_UL_(1) << 24)
1038 #define PIN_PA25H_USB_DP _L_(25)
1039 #define MUX_PA25H_USB_DP _L_(7)
1040 #define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP)
1041 #define PORT_PA25H_USB_DP (_UL_(1) << 25)
1042 #define PIN_PA23H_USB_SOF_1KHZ _L_(23)
1043 #define MUX_PA23H_USB_SOF_1KHZ _L_(7)
1044 #define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ)
1045 #define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23)
1046 #define PIN_PB22H_USB_SOF_1KHZ _L_(54)
1047 #define MUX_PB22H_USB_SOF_1KHZ _L_(7)
1048 #define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ)
1049 #define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22)
1051 #define PIN_PA09D_SERCOM2_PAD0 _L_(9)
1052 #define MUX_PA09D_SERCOM2_PAD0 _L_(3)
1053 #define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0)
1054 #define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9)
1055 #define PIN_PB25D_SERCOM2_PAD0 _L_(57)
1056 #define MUX_PB25D_SERCOM2_PAD0 _L_(3)
1057 #define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0)
1058 #define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25)
1059 #define PIN_PA12C_SERCOM2_PAD0 _L_(12)
1060 #define MUX_PA12C_SERCOM2_PAD0 _L_(2)
1061 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0)
1062 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12)
1063 #define PIN_PB26C_SERCOM2_PAD0 _L_(58)
1064 #define MUX_PB26C_SERCOM2_PAD0 _L_(2)
1065 #define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0)
1066 #define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26)
1067 #define PIN_PA08D_SERCOM2_PAD1 _L_(8)
1068 #define MUX_PA08D_SERCOM2_PAD1 _L_(3)
1069 #define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1)
1070 #define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8)
1071 #define PIN_PB24D_SERCOM2_PAD1 _L_(56)
1072 #define MUX_PB24D_SERCOM2_PAD1 _L_(3)
1073 #define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1)
1074 #define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24)
1075 #define PIN_PA13C_SERCOM2_PAD1 _L_(13)
1076 #define MUX_PA13C_SERCOM2_PAD1 _L_(2)
1077 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1)
1078 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13)
1079 #define PIN_PB27C_SERCOM2_PAD1 _L_(59)
1080 #define MUX_PB27C_SERCOM2_PAD1 _L_(2)
1081 #define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1)
1082 #define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27)
1083 #define PIN_PA10D_SERCOM2_PAD2 _L_(10)
1084 #define MUX_PA10D_SERCOM2_PAD2 _L_(3)
1085 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
1086 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
1087 #define PIN_PC24D_SERCOM2_PAD2 _L_(88)
1088 #define MUX_PC24D_SERCOM2_PAD2 _L_(3)
1089 #define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2)
1090 #define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24)
1091 #define PIN_PB28C_SERCOM2_PAD2 _L_(60)
1092 #define MUX_PB28C_SERCOM2_PAD2 _L_(2)
1093 #define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2)
1094 #define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28)
1095 #define PIN_PA14C_SERCOM2_PAD2 _L_(14)
1096 #define MUX_PA14C_SERCOM2_PAD2 _L_(2)
1097 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
1098 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
1099 #define PIN_PA11D_SERCOM2_PAD3 _L_(11)
1100 #define MUX_PA11D_SERCOM2_PAD3 _L_(3)
1101 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
1102 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
1103 #define PIN_PC25D_SERCOM2_PAD3 _L_(89)
1104 #define MUX_PC25D_SERCOM2_PAD3 _L_(3)
1105 #define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3)
1106 #define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25)
1107 #define PIN_PB29C_SERCOM2_PAD3 _L_(61)
1108 #define MUX_PB29C_SERCOM2_PAD3 _L_(2)
1109 #define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3)
1110 #define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29)
1111 #define PIN_PA15C_SERCOM2_PAD3 _L_(15)
1112 #define MUX_PA15C_SERCOM2_PAD3 _L_(2)
1113 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
1114 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
1116 #define PIN_PA17D_SERCOM3_PAD0 _L_(17)
1117 #define MUX_PA17D_SERCOM3_PAD0 _L_(3)
1118 #define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0)
1119 #define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17)
1120 #define PIN_PC23D_SERCOM3_PAD0 _L_(87)
1121 #define MUX_PC23D_SERCOM3_PAD0 _L_(3)
1122 #define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0)
1123 #define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23)
1124 #define PIN_PA22C_SERCOM3_PAD0 _L_(22)
1125 #define MUX_PA22C_SERCOM3_PAD0 _L_(2)
1126 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
1127 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
1128 #define PIN_PB20C_SERCOM3_PAD0 _L_(52)
1129 #define MUX_PB20C_SERCOM3_PAD0 _L_(2)
1130 #define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0)
1131 #define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20)
1132 #define PIN_PA16D_SERCOM3_PAD1 _L_(16)
1133 #define MUX_PA16D_SERCOM3_PAD1 _L_(3)
1134 #define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1)
1135 #define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16)
1136 #define PIN_PC22D_SERCOM3_PAD1 _L_(86)
1137 #define MUX_PC22D_SERCOM3_PAD1 _L_(3)
1138 #define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1)
1139 #define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22)
1140 #define PIN_PA23C_SERCOM3_PAD1 _L_(23)
1141 #define MUX_PA23C_SERCOM3_PAD1 _L_(2)
1142 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
1143 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
1144 #define PIN_PB21C_SERCOM3_PAD1 _L_(53)
1145 #define MUX_PB21C_SERCOM3_PAD1 _L_(2)
1146 #define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1)
1147 #define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21)
1148 #define PIN_PA18D_SERCOM3_PAD2 _L_(18)
1149 #define MUX_PA18D_SERCOM3_PAD2 _L_(3)
1150 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
1151 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
1152 #define PIN_PA20D_SERCOM3_PAD2 _L_(20)
1153 #define MUX_PA20D_SERCOM3_PAD2 _L_(3)
1154 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2)
1155 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20)
1156 #define PIN_PD20D_SERCOM3_PAD2 _L_(116)
1157 #define MUX_PD20D_SERCOM3_PAD2 _L_(3)
1158 #define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2)
1159 #define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20)
1160 #define PIN_PA24C_SERCOM3_PAD2 _L_(24)
1161 #define MUX_PA24C_SERCOM3_PAD2 _L_(2)
1162 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
1163 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
1164 #define PIN_PA19D_SERCOM3_PAD3 _L_(19)
1165 #define MUX_PA19D_SERCOM3_PAD3 _L_(3)
1166 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
1167 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
1168 #define PIN_PA21D_SERCOM3_PAD3 _L_(21)
1169 #define MUX_PA21D_SERCOM3_PAD3 _L_(3)
1170 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3)
1171 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21)
1172 #define PIN_PD21D_SERCOM3_PAD3 _L_(117)
1173 #define MUX_PD21D_SERCOM3_PAD3 _L_(3)
1174 #define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3)
1175 #define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21)
1176 #define PIN_PA25C_SERCOM3_PAD3 _L_(25)
1177 #define MUX_PA25C_SERCOM3_PAD3 _L_(2)
1178 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
1179 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
1181 #define PIN_PA20G_TCC0_WO0 _L_(20)
1182 #define MUX_PA20G_TCC0_WO0 _L_(6)
1183 #define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0)
1184 #define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20)
1185 #define PIN_PB12G_TCC0_WO0 _L_(44)
1186 #define MUX_PB12G_TCC0_WO0 _L_(6)
1187 #define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0)
1188 #define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12)
1189 #define PIN_PA08F_TCC0_WO0 _L_(8)
1190 #define MUX_PA08F_TCC0_WO0 _L_(5)
1191 #define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0)
1192 #define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8)
1193 #define PIN_PC04F_TCC0_WO0 _L_(68)
1194 #define MUX_PC04F_TCC0_WO0 _L_(5)
1195 #define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0)
1196 #define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4)
1197 #define PIN_PC10F_TCC0_WO0 _L_(74)
1198 #define MUX_PC10F_TCC0_WO0 _L_(5)
1199 #define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0)
1200 #define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10)
1201 #define PIN_PC16F_TCC0_WO0 _L_(80)
1202 #define MUX_PC16F_TCC0_WO0 _L_(5)
1203 #define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0)
1204 #define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16)
1205 #define PIN_PA21G_TCC0_WO1 _L_(21)
1206 #define MUX_PA21G_TCC0_WO1 _L_(6)
1207 #define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1)
1208 #define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21)
1209 #define PIN_PB13G_TCC0_WO1 _L_(45)
1210 #define MUX_PB13G_TCC0_WO1 _L_(6)
1211 #define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1)
1212 #define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13)
1213 #define PIN_PA09F_TCC0_WO1 _L_(9)
1214 #define MUX_PA09F_TCC0_WO1 _L_(5)
1215 #define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1)
1216 #define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9)
1217 #define PIN_PC11F_TCC0_WO1 _L_(75)
1218 #define MUX_PC11F_TCC0_WO1 _L_(5)
1219 #define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1)
1220 #define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11)
1221 #define PIN_PC17F_TCC0_WO1 _L_(81)
1222 #define MUX_PC17F_TCC0_WO1 _L_(5)
1223 #define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1)
1224 #define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17)
1225 #define PIN_PD08F_TCC0_WO1 _L_(104)
1226 #define MUX_PD08F_TCC0_WO1 _L_(5)
1227 #define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1)
1228 #define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8)
1229 #define PIN_PA22G_TCC0_WO2 _L_(22)
1230 #define MUX_PA22G_TCC0_WO2 _L_(6)
1231 #define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2)
1232 #define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22)
1233 #define PIN_PB14G_TCC0_WO2 _L_(46)
1234 #define MUX_PB14G_TCC0_WO2 _L_(6)
1235 #define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2)
1236 #define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14)
1237 #define PIN_PA10F_TCC0_WO2 _L_(10)
1238 #define MUX_PA10F_TCC0_WO2 _L_(5)
1239 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
1240 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
1241 #define PIN_PC12F_TCC0_WO2 _L_(76)
1242 #define MUX_PC12F_TCC0_WO2 _L_(5)
1243 #define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2)
1244 #define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12)
1245 #define PIN_PC18F_TCC0_WO2 _L_(82)
1246 #define MUX_PC18F_TCC0_WO2 _L_(5)
1247 #define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2)
1248 #define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18)
1249 #define PIN_PD09F_TCC0_WO2 _L_(105)
1250 #define MUX_PD09F_TCC0_WO2 _L_(5)
1251 #define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2)
1252 #define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9)
1253 #define PIN_PA23G_TCC0_WO3 _L_(23)
1254 #define MUX_PA23G_TCC0_WO3 _L_(6)
1255 #define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3)
1256 #define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23)
1257 #define PIN_PB15G_TCC0_WO3 _L_(47)
1258 #define MUX_PB15G_TCC0_WO3 _L_(6)
1259 #define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3)
1260 #define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15)
1261 #define PIN_PA11F_TCC0_WO3 _L_(11)
1262 #define MUX_PA11F_TCC0_WO3 _L_(5)
1263 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
1264 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
1265 #define PIN_PC13F_TCC0_WO3 _L_(77)
1266 #define MUX_PC13F_TCC0_WO3 _L_(5)
1267 #define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3)
1268 #define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13)
1269 #define PIN_PC19F_TCC0_WO3 _L_(83)
1270 #define MUX_PC19F_TCC0_WO3 _L_(5)
1271 #define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3)
1272 #define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19)
1273 #define PIN_PD10F_TCC0_WO3 _L_(106)
1274 #define MUX_PD10F_TCC0_WO3 _L_(5)
1275 #define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3)
1276 #define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10)
1277 #define PIN_PA16G_TCC0_WO4 _L_(16)
1278 #define MUX_PA16G_TCC0_WO4 _L_(6)
1279 #define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4)
1280 #define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16)
1281 #define PIN_PB16G_TCC0_WO4 _L_(48)
1282 #define MUX_PB16G_TCC0_WO4 _L_(6)
1283 #define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4)
1284 #define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16)
1285 #define PIN_PB10F_TCC0_WO4 _L_(42)
1286 #define MUX_PB10F_TCC0_WO4 _L_(5)
1287 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4)
1288 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10)
1289 #define PIN_PC14F_TCC0_WO4 _L_(78)
1290 #define MUX_PC14F_TCC0_WO4 _L_(5)
1291 #define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4)
1292 #define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14)
1293 #define PIN_PC20F_TCC0_WO4 _L_(84)
1294 #define MUX_PC20F_TCC0_WO4 _L_(5)
1295 #define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4)
1296 #define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20)
1297 #define PIN_PD11F_TCC0_WO4 _L_(107)
1298 #define MUX_PD11F_TCC0_WO4 _L_(5)
1299 #define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4)
1300 #define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11)
1301 #define PIN_PA17G_TCC0_WO5 _L_(17)
1302 #define MUX_PA17G_TCC0_WO5 _L_(6)
1303 #define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5)
1304 #define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17)
1305 #define PIN_PB17G_TCC0_WO5 _L_(49)
1306 #define MUX_PB17G_TCC0_WO5 _L_(6)
1307 #define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5)
1308 #define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17)
1309 #define PIN_PB11F_TCC0_WO5 _L_(43)
1310 #define MUX_PB11F_TCC0_WO5 _L_(5)
1311 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5)
1312 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11)
1313 #define PIN_PC15F_TCC0_WO5 _L_(79)
1314 #define MUX_PC15F_TCC0_WO5 _L_(5)
1315 #define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5)
1316 #define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15)
1317 #define PIN_PC21F_TCC0_WO5 _L_(85)
1318 #define MUX_PC21F_TCC0_WO5 _L_(5)
1319 #define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5)
1320 #define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21)
1321 #define PIN_PD12F_TCC0_WO5 _L_(108)
1322 #define MUX_PD12F_TCC0_WO5 _L_(5)
1323 #define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5)
1324 #define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12)
1325 #define PIN_PA18G_TCC0_WO6 _L_(18)
1326 #define MUX_PA18G_TCC0_WO6 _L_(6)
1327 #define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6)
1328 #define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18)
1329 #define PIN_PB30G_TCC0_WO6 _L_(62)
1330 #define MUX_PB30G_TCC0_WO6 _L_(6)
1331 #define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6)
1332 #define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30)
1333 #define PIN_PA12F_TCC0_WO6 _L_(12)
1334 #define MUX_PA12F_TCC0_WO6 _L_(5)
1335 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6)
1336 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12)
1337 #define PIN_PC22F_TCC0_WO6 _L_(86)
1338 #define MUX_PC22F_TCC0_WO6 _L_(5)
1339 #define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6)
1340 #define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22)
1341 #define PIN_PA19G_TCC0_WO7 _L_(19)
1342 #define MUX_PA19G_TCC0_WO7 _L_(6)
1343 #define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7)
1344 #define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19)
1345 #define PIN_PB31G_TCC0_WO7 _L_(63)
1346 #define MUX_PB31G_TCC0_WO7 _L_(6)
1347 #define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7)
1348 #define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31)
1349 #define PIN_PA13F_TCC0_WO7 _L_(13)
1350 #define MUX_PA13F_TCC0_WO7 _L_(5)
1351 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7)
1352 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13)
1353 #define PIN_PC23F_TCC0_WO7 _L_(87)
1354 #define MUX_PC23F_TCC0_WO7 _L_(5)
1355 #define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7)
1356 #define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23)
1358 #define PIN_PB10G_TCC1_WO0 _L_(42)
1359 #define MUX_PB10G_TCC1_WO0 _L_(6)
1360 #define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0)
1361 #define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10)
1362 #define PIN_PC14G_TCC1_WO0 _L_(78)
1363 #define MUX_PC14G_TCC1_WO0 _L_(6)
1364 #define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0)
1365 #define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14)
1366 #define PIN_PA16F_TCC1_WO0 _L_(16)
1367 #define MUX_PA16F_TCC1_WO0 _L_(5)
1368 #define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0)
1369 #define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16)
1370 #define PIN_PB18F_TCC1_WO0 _L_(50)
1371 #define MUX_PB18F_TCC1_WO0 _L_(5)
1372 #define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0)
1373 #define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18)
1374 #define PIN_PD20F_TCC1_WO0 _L_(116)
1375 #define MUX_PD20F_TCC1_WO0 _L_(5)
1376 #define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0)
1377 #define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20)
1378 #define PIN_PB11G_TCC1_WO1 _L_(43)
1379 #define MUX_PB11G_TCC1_WO1 _L_(6)
1380 #define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1)
1381 #define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11)
1382 #define PIN_PC15G_TCC1_WO1 _L_(79)
1383 #define MUX_PC15G_TCC1_WO1 _L_(6)
1384 #define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1)
1385 #define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15)
1386 #define PIN_PA17F_TCC1_WO1 _L_(17)
1387 #define MUX_PA17F_TCC1_WO1 _L_(5)
1388 #define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1)
1389 #define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17)
1390 #define PIN_PB19F_TCC1_WO1 _L_(51)
1391 #define MUX_PB19F_TCC1_WO1 _L_(5)
1392 #define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1)
1393 #define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19)
1394 #define PIN_PD21F_TCC1_WO1 _L_(117)
1395 #define MUX_PD21F_TCC1_WO1 _L_(5)
1396 #define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1)
1397 #define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21)
1398 #define PIN_PA12G_TCC1_WO2 _L_(12)
1399 #define MUX_PA12G_TCC1_WO2 _L_(6)
1400 #define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2)
1401 #define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12)
1402 #define PIN_PA14G_TCC1_WO2 _L_(14)
1403 #define MUX_PA14G_TCC1_WO2 _L_(6)
1404 #define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2)
1405 #define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14)
1406 #define PIN_PA18F_TCC1_WO2 _L_(18)
1407 #define MUX_PA18F_TCC1_WO2 _L_(5)
1408 #define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2)
1409 #define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18)
1410 #define PIN_PB20F_TCC1_WO2 _L_(52)
1411 #define MUX_PB20F_TCC1_WO2 _L_(5)
1412 #define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2)
1413 #define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20)
1414 #define PIN_PB26F_TCC1_WO2 _L_(58)
1415 #define MUX_PB26F_TCC1_WO2 _L_(5)
1416 #define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2)
1417 #define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26)
1418 #define PIN_PA13G_TCC1_WO3 _L_(13)
1419 #define MUX_PA13G_TCC1_WO3 _L_(6)
1420 #define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3)
1421 #define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13)
1422 #define PIN_PA15G_TCC1_WO3 _L_(15)
1423 #define MUX_PA15G_TCC1_WO3 _L_(6)
1424 #define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3)
1425 #define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15)
1426 #define PIN_PA19F_TCC1_WO3 _L_(19)
1427 #define MUX_PA19F_TCC1_WO3 _L_(5)
1428 #define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3)
1429 #define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19)
1430 #define PIN_PB21F_TCC1_WO3 _L_(53)
1431 #define MUX_PB21F_TCC1_WO3 _L_(5)
1432 #define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3)
1433 #define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21)
1434 #define PIN_PB27F_TCC1_WO3 _L_(59)
1435 #define MUX_PB27F_TCC1_WO3 _L_(5)
1436 #define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3)
1437 #define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27)
1438 #define PIN_PA08G_TCC1_WO4 _L_(8)
1439 #define MUX_PA08G_TCC1_WO4 _L_(6)
1440 #define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4)
1441 #define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8)
1442 #define PIN_PC10G_TCC1_WO4 _L_(74)
1443 #define MUX_PC10G_TCC1_WO4 _L_(6)
1444 #define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4)
1445 #define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10)
1446 #define PIN_PA20F_TCC1_WO4 _L_(20)
1447 #define MUX_PA20F_TCC1_WO4 _L_(5)
1448 #define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4)
1449 #define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20)
1450 #define PIN_PB28F_TCC1_WO4 _L_(60)
1451 #define MUX_PB28F_TCC1_WO4 _L_(5)
1452 #define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4)
1453 #define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28)
1454 #define PIN_PA09G_TCC1_WO5 _L_(9)
1455 #define MUX_PA09G_TCC1_WO5 _L_(6)
1456 #define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5)
1457 #define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9)
1458 #define PIN_PC11G_TCC1_WO5 _L_(75)
1459 #define MUX_PC11G_TCC1_WO5 _L_(6)
1460 #define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5)
1461 #define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11)
1462 #define PIN_PA21F_TCC1_WO5 _L_(21)
1463 #define MUX_PA21F_TCC1_WO5 _L_(5)
1464 #define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5)
1465 #define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21)
1466 #define PIN_PB29F_TCC1_WO5 _L_(61)
1467 #define MUX_PB29F_TCC1_WO5 _L_(5)
1468 #define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5)
1469 #define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29)
1470 #define PIN_PA10G_TCC1_WO6 _L_(10)
1471 #define MUX_PA10G_TCC1_WO6 _L_(6)
1472 #define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6)
1473 #define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10)
1474 #define PIN_PC12G_TCC1_WO6 _L_(76)
1475 #define MUX_PC12G_TCC1_WO6 _L_(6)
1476 #define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6)
1477 #define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12)
1478 #define PIN_PA22F_TCC1_WO6 _L_(22)
1479 #define MUX_PA22F_TCC1_WO6 _L_(5)
1480 #define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6)
1481 #define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22)
1482 #define PIN_PA11G_TCC1_WO7 _L_(11)
1483 #define MUX_PA11G_TCC1_WO7 _L_(6)
1484 #define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7)
1485 #define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11)
1486 #define PIN_PC13G_TCC1_WO7 _L_(77)
1487 #define MUX_PC13G_TCC1_WO7 _L_(6)
1488 #define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7)
1489 #define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13)
1490 #define PIN_PA23F_TCC1_WO7 _L_(23)
1491 #define MUX_PA23F_TCC1_WO7 _L_(5)
1492 #define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7)
1493 #define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23)
1495 #define PIN_PA12E_TC2_WO0 _L_(12)
1496 #define MUX_PA12E_TC2_WO0 _L_(4)
1497 #define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0)
1498 #define PORT_PA12E_TC2_WO0 (_UL_(1) << 12)
1499 #define PIN_PA16E_TC2_WO0 _L_(16)
1500 #define MUX_PA16E_TC2_WO0 _L_(4)
1501 #define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0)
1502 #define PORT_PA16E_TC2_WO0 (_UL_(1) << 16)
1503 #define PIN_PA00E_TC2_WO0 _L_(0)
1504 #define MUX_PA00E_TC2_WO0 _L_(4)
1505 #define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0)
1506 #define PORT_PA00E_TC2_WO0 (_UL_(1) << 0)
1507 #define PIN_PA01E_TC2_WO1 _L_(1)
1508 #define MUX_PA01E_TC2_WO1 _L_(4)
1509 #define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1)
1510 #define PORT_PA01E_TC2_WO1 (_UL_(1) << 1)
1511 #define PIN_PA13E_TC2_WO1 _L_(13)
1512 #define MUX_PA13E_TC2_WO1 _L_(4)
1513 #define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1)
1514 #define PORT_PA13E_TC2_WO1 (_UL_(1) << 13)
1515 #define PIN_PA17E_TC2_WO1 _L_(17)
1516 #define MUX_PA17E_TC2_WO1 _L_(4)
1517 #define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1)
1518 #define PORT_PA17E_TC2_WO1 (_UL_(1) << 17)
1520 #define PIN_PA18E_TC3_WO0 _L_(18)
1521 #define MUX_PA18E_TC3_WO0 _L_(4)
1522 #define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0)
1523 #define PORT_PA18E_TC3_WO0 (_UL_(1) << 18)
1524 #define PIN_PA14E_TC3_WO0 _L_(14)
1525 #define MUX_PA14E_TC3_WO0 _L_(4)
1526 #define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0)
1527 #define PORT_PA14E_TC3_WO0 (_UL_(1) << 14)
1528 #define PIN_PA15E_TC3_WO1 _L_(15)
1529 #define MUX_PA15E_TC3_WO1 _L_(4)
1530 #define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1)
1531 #define PORT_PA15E_TC3_WO1 (_UL_(1) << 15)
1532 #define PIN_PA19E_TC3_WO1 _L_(19)
1533 #define MUX_PA19E_TC3_WO1 _L_(4)
1534 #define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1)
1535 #define PORT_PA19E_TC3_WO1 (_UL_(1) << 19)
1537 #define PIN_PA23I_CAN0_RX _L_(23)
1538 #define MUX_PA23I_CAN0_RX _L_(8)
1539 #define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX)
1540 #define PORT_PA23I_CAN0_RX (_UL_(1) << 23)
1541 #define PIN_PA25I_CAN0_RX _L_(25)
1542 #define MUX_PA25I_CAN0_RX _L_(8)
1543 #define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX)
1544 #define PORT_PA25I_CAN0_RX (_UL_(1) << 25)
1545 #define PIN_PA22I_CAN0_TX _L_(22)
1546 #define MUX_PA22I_CAN0_TX _L_(8)
1547 #define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX)
1548 #define PORT_PA22I_CAN0_TX (_UL_(1) << 22)
1549 #define PIN_PA24I_CAN0_TX _L_(24)
1550 #define MUX_PA24I_CAN0_TX _L_(8)
1551 #define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX)
1552 #define PORT_PA24I_CAN0_TX (_UL_(1) << 24)
1554 #define PIN_PB13H_CAN1_RX _L_(45)
1555 #define MUX_PB13H_CAN1_RX _L_(7)
1556 #define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX)
1557 #define PORT_PB13H_CAN1_RX (_UL_(1) << 13)
1558 #define PIN_PB15H_CAN1_RX _L_(47)
1559 #define MUX_PB15H_CAN1_RX _L_(7)
1560 #define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX)
1561 #define PORT_PB15H_CAN1_RX (_UL_(1) << 15)
1562 #define PIN_PB12H_CAN1_TX _L_(44)
1563 #define MUX_PB12H_CAN1_TX _L_(7)
1564 #define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX)
1565 #define PORT_PB12H_CAN1_TX (_UL_(1) << 12)
1566 #define PIN_PB14H_CAN1_TX _L_(46)
1567 #define MUX_PB14H_CAN1_TX _L_(7)
1568 #define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX)
1569 #define PORT_PB14H_CAN1_TX (_UL_(1) << 14)
1571 #define PIN_PC21L_GMAC_GCOL _L_(85)
1572 #define MUX_PC21L_GMAC_GCOL _L_(11)
1573 #define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL)
1574 #define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21)
1575 #define PIN_PA16L_GMAC_GCRS _L_(16)
1576 #define MUX_PA16L_GMAC_GCRS _L_(11)
1577 #define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS)
1578 #define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16)
1579 #define PIN_PA20L_GMAC_GMDC _L_(20)
1580 #define MUX_PA20L_GMAC_GMDC _L_(11)
1581 #define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC)
1582 #define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20)
1583 #define PIN_PB14L_GMAC_GMDC _L_(46)
1584 #define MUX_PB14L_GMAC_GMDC _L_(11)
1585 #define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC)
1586 #define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14)
1587 #define PIN_PC11L_GMAC_GMDC _L_(75)
1588 #define MUX_PC11L_GMAC_GMDC _L_(11)
1589 #define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC)
1590 #define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11)
1591 #define PIN_PC22L_GMAC_GMDC _L_(86)
1592 #define MUX_PC22L_GMAC_GMDC _L_(11)
1593 #define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC)
1594 #define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22)
1595 #define PIN_PA21L_GMAC_GMDIO _L_(21)
1596 #define MUX_PA21L_GMAC_GMDIO _L_(11)
1597 #define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO)
1598 #define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21)
1599 #define PIN_PB15L_GMAC_GMDIO _L_(47)
1600 #define MUX_PB15L_GMAC_GMDIO _L_(11)
1601 #define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO)
1602 #define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15)
1603 #define PIN_PC12L_GMAC_GMDIO _L_(76)
1604 #define MUX_PC12L_GMAC_GMDIO _L_(11)
1605 #define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO)
1606 #define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12)
1607 #define PIN_PC23L_GMAC_GMDIO _L_(87)
1608 #define MUX_PC23L_GMAC_GMDIO _L_(11)
1609 #define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO)
1610 #define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23)
1611 #define PIN_PA13L_GMAC_GRX0 _L_(13)
1612 #define MUX_PA13L_GMAC_GRX0 _L_(11)
1613 #define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0)
1614 #define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13)
1615 #define PIN_PA12L_GMAC_GRX1 _L_(12)
1616 #define MUX_PA12L_GMAC_GRX1 _L_(11)
1617 #define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1)
1618 #define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12)
1619 #define PIN_PC15L_GMAC_GRX2 _L_(79)
1620 #define MUX_PC15L_GMAC_GRX2 _L_(11)
1621 #define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2)
1622 #define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15)
1623 #define PIN_PC14L_GMAC_GRX3 _L_(78)
1624 #define MUX_PC14L_GMAC_GRX3 _L_(11)
1625 #define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3)
1626 #define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14)
1627 #define PIN_PC18L_GMAC_GRXCK _L_(82)
1628 #define MUX_PC18L_GMAC_GRXCK _L_(11)
1629 #define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK)
1630 #define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18)
1631 #define PIN_PC20L_GMAC_GRXDV _L_(84)
1632 #define MUX_PC20L_GMAC_GRXDV _L_(11)
1633 #define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV)
1634 #define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20)
1635 #define PIN_PA15L_GMAC_GRXER _L_(15)
1636 #define MUX_PA15L_GMAC_GRXER _L_(11)
1637 #define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER)
1638 #define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15)
1639 #define PIN_PA18L_GMAC_GTX0 _L_(18)
1640 #define MUX_PA18L_GMAC_GTX0 _L_(11)
1641 #define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0)
1642 #define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18)
1643 #define PIN_PA19L_GMAC_GTX1 _L_(19)
1644 #define MUX_PA19L_GMAC_GTX1 _L_(11)
1645 #define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1)
1646 #define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19)
1647 #define PIN_PC16L_GMAC_GTX2 _L_(80)
1648 #define MUX_PC16L_GMAC_GTX2 _L_(11)
1649 #define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2)
1650 #define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16)
1651 #define PIN_PC17L_GMAC_GTX3 _L_(81)
1652 #define MUX_PC17L_GMAC_GTX3 _L_(11)
1653 #define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3)
1654 #define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17)
1655 #define PIN_PA14L_GMAC_GTXCK _L_(14)
1656 #define MUX_PA14L_GMAC_GTXCK _L_(11)
1657 #define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK)
1658 #define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14)
1659 #define PIN_PA17L_GMAC_GTXEN _L_(17)
1660 #define MUX_PA17L_GMAC_GTXEN _L_(11)
1661 #define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN)
1662 #define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17)
1663 #define PIN_PC19L_GMAC_GTXER _L_(83)
1664 #define MUX_PC19L_GMAC_GTXER _L_(11)
1665 #define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER)
1666 #define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19)
1668 #define PIN_PA14F_TCC2_WO0 _L_(14)
1669 #define MUX_PA14F_TCC2_WO0 _L_(5)
1670 #define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0)
1671 #define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14)
1672 #define PIN_PA30F_TCC2_WO0 _L_(30)
1673 #define MUX_PA30F_TCC2_WO0 _L_(5)
1674 #define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0)
1675 #define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30)
1676 #define PIN_PA15F_TCC2_WO1 _L_(15)
1677 #define MUX_PA15F_TCC2_WO1 _L_(5)
1678 #define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1)
1679 #define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15)
1680 #define PIN_PA31F_TCC2_WO1 _L_(31)
1681 #define MUX_PA31F_TCC2_WO1 _L_(5)
1682 #define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1)
1683 #define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31)
1684 #define PIN_PA24F_TCC2_WO2 _L_(24)
1685 #define MUX_PA24F_TCC2_WO2 _L_(5)
1686 #define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2)
1687 #define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24)
1688 #define PIN_PB02F_TCC2_WO2 _L_(34)
1689 #define MUX_PB02F_TCC2_WO2 _L_(5)
1690 #define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2)
1691 #define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2)
1693 #define PIN_PB12F_TCC3_WO0 _L_(44)
1694 #define MUX_PB12F_TCC3_WO0 _L_(5)
1695 #define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0)
1696 #define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12)
1697 #define PIN_PB16F_TCC3_WO0 _L_(48)
1698 #define MUX_PB16F_TCC3_WO0 _L_(5)
1699 #define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0)
1700 #define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16)
1701 #define PIN_PB13F_TCC3_WO1 _L_(45)
1702 #define MUX_PB13F_TCC3_WO1 _L_(5)
1703 #define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1)
1704 #define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13)
1705 #define PIN_PB17F_TCC3_WO1 _L_(49)
1706 #define MUX_PB17F_TCC3_WO1 _L_(5)
1707 #define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1)
1708 #define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17)
1710 #define PIN_PA22E_TC4_WO0 _L_(22)
1711 #define MUX_PA22E_TC4_WO0 _L_(4)
1712 #define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0)
1713 #define PORT_PA22E_TC4_WO0 (_UL_(1) << 22)
1714 #define PIN_PB08E_TC4_WO0 _L_(40)
1715 #define MUX_PB08E_TC4_WO0 _L_(4)
1716 #define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0)
1717 #define PORT_PB08E_TC4_WO0 (_UL_(1) << 8)
1718 #define PIN_PB12E_TC4_WO0 _L_(44)
1719 #define MUX_PB12E_TC4_WO0 _L_(4)
1720 #define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0)
1721 #define PORT_PB12E_TC4_WO0 (_UL_(1) << 12)
1722 #define PIN_PA23E_TC4_WO1 _L_(23)
1723 #define MUX_PA23E_TC4_WO1 _L_(4)
1724 #define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1)
1725 #define PORT_PA23E_TC4_WO1 (_UL_(1) << 23)
1726 #define PIN_PB09E_TC4_WO1 _L_(41)
1727 #define MUX_PB09E_TC4_WO1 _L_(4)
1728 #define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1)
1729 #define PORT_PB09E_TC4_WO1 (_UL_(1) << 9)
1730 #define PIN_PB13E_TC4_WO1 _L_(45)
1731 #define MUX_PB13E_TC4_WO1 _L_(4)
1732 #define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1)
1733 #define PORT_PB13E_TC4_WO1 (_UL_(1) << 13)
1735 #define PIN_PA24E_TC5_WO0 _L_(24)
1736 #define MUX_PA24E_TC5_WO0 _L_(4)
1737 #define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0)
1738 #define PORT_PA24E_TC5_WO0 (_UL_(1) << 24)
1739 #define PIN_PB10E_TC5_WO0 _L_(42)
1740 #define MUX_PB10E_TC5_WO0 _L_(4)
1741 #define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0)
1742 #define PORT_PB10E_TC5_WO0 (_UL_(1) << 10)
1743 #define PIN_PB14E_TC5_WO0 _L_(46)
1744 #define MUX_PB14E_TC5_WO0 _L_(4)
1745 #define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0)
1746 #define PORT_PB14E_TC5_WO0 (_UL_(1) << 14)
1747 #define PIN_PA25E_TC5_WO1 _L_(25)
1748 #define MUX_PA25E_TC5_WO1 _L_(4)
1749 #define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1)
1750 #define PORT_PA25E_TC5_WO1 (_UL_(1) << 25)
1751 #define PIN_PB11E_TC5_WO1 _L_(43)
1752 #define MUX_PB11E_TC5_WO1 _L_(4)
1753 #define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1)
1754 #define PORT_PB11E_TC5_WO1 (_UL_(1) << 11)
1755 #define PIN_PB15E_TC5_WO1 _L_(47)
1756 #define MUX_PB15E_TC5_WO1 _L_(4)
1757 #define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1)
1758 #define PORT_PB15E_TC5_WO1 (_UL_(1) << 15)
1760 #define PIN_PB18G_PDEC_QDI0 _L_(50)
1761 #define MUX_PB18G_PDEC_QDI0 _L_(6)
1762 #define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0)
1763 #define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18)
1764 #define PIN_PB23G_PDEC_QDI0 _L_(55)
1765 #define MUX_PB23G_PDEC_QDI0 _L_(6)
1766 #define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0)
1767 #define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23)
1768 #define PIN_PC16G_PDEC_QDI0 _L_(80)
1769 #define MUX_PC16G_PDEC_QDI0 _L_(6)
1770 #define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0)
1771 #define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16)
1772 #define PIN_PA24G_PDEC_QDI0 _L_(24)
1773 #define MUX_PA24G_PDEC_QDI0 _L_(6)
1774 #define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0)
1775 #define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24)
1776 #define PIN_PB19G_PDEC_QDI1 _L_(51)
1777 #define MUX_PB19G_PDEC_QDI1 _L_(6)
1778 #define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1)
1779 #define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19)
1780 #define PIN_PB24G_PDEC_QDI1 _L_(56)
1781 #define MUX_PB24G_PDEC_QDI1 _L_(6)
1782 #define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1)
1783 #define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24)
1784 #define PIN_PC17G_PDEC_QDI1 _L_(81)
1785 #define MUX_PC17G_PDEC_QDI1 _L_(6)
1786 #define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1)
1787 #define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17)
1788 #define PIN_PA25G_PDEC_QDI1 _L_(25)
1789 #define MUX_PA25G_PDEC_QDI1 _L_(6)
1790 #define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1)
1791 #define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25)
1792 #define PIN_PB20G_PDEC_QDI2 _L_(52)
1793 #define MUX_PB20G_PDEC_QDI2 _L_(6)
1794 #define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2)
1795 #define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20)
1796 #define PIN_PB25G_PDEC_QDI2 _L_(57)
1797 #define MUX_PB25G_PDEC_QDI2 _L_(6)
1798 #define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2)
1799 #define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25)
1800 #define PIN_PC18G_PDEC_QDI2 _L_(82)
1801 #define MUX_PC18G_PDEC_QDI2 _L_(6)
1802 #define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2)
1803 #define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18)
1804 #define PIN_PB22G_PDEC_QDI2 _L_(54)
1805 #define MUX_PB22G_PDEC_QDI2 _L_(6)
1806 #define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2)
1807 #define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22)
1809 #define PIN_PA04B_AC_AIN0 _L_(4)
1810 #define MUX_PA04B_AC_AIN0 _L_(1)
1811 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
1812 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
1813 #define PIN_PA05B_AC_AIN1 _L_(5)
1814 #define MUX_PA05B_AC_AIN1 _L_(1)
1815 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
1816 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
1817 #define PIN_PA06B_AC_AIN2 _L_(6)
1818 #define MUX_PA06B_AC_AIN2 _L_(1)
1819 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
1820 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
1821 #define PIN_PA07B_AC_AIN3 _L_(7)
1822 #define MUX_PA07B_AC_AIN3 _L_(1)
1823 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
1824 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
1825 #define PIN_PA12M_AC_CMP0 _L_(12)
1826 #define MUX_PA12M_AC_CMP0 _L_(12)
1827 #define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0)
1828 #define PORT_PA12M_AC_CMP0 (_UL_(1) << 12)
1829 #define PIN_PA18M_AC_CMP0 _L_(18)
1830 #define MUX_PA18M_AC_CMP0 _L_(12)
1831 #define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0)
1832 #define PORT_PA18M_AC_CMP0 (_UL_(1) << 18)
1833 #define PIN_PB24M_AC_CMP0 _L_(56)
1834 #define MUX_PB24M_AC_CMP0 _L_(12)
1835 #define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0)
1836 #define PORT_PB24M_AC_CMP0 (_UL_(1) << 24)
1837 #define PIN_PA13M_AC_CMP1 _L_(13)
1838 #define MUX_PA13M_AC_CMP1 _L_(12)
1839 #define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1)
1840 #define PORT_PA13M_AC_CMP1 (_UL_(1) << 13)
1841 #define PIN_PA19M_AC_CMP1 _L_(19)
1842 #define MUX_PA19M_AC_CMP1 _L_(12)
1843 #define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1)
1844 #define PORT_PA19M_AC_CMP1 (_UL_(1) << 19)
1845 #define PIN_PB25M_AC_CMP1 _L_(57)
1846 #define MUX_PB25M_AC_CMP1 _L_(12)
1847 #define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1)
1848 #define PORT_PB25M_AC_CMP1 (_UL_(1) << 25)
1850 #define PIN_PB11H_QSPI_CS _L_(43)
1851 #define MUX_PB11H_QSPI_CS _L_(7)
1852 #define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS)
1853 #define PORT_PB11H_QSPI_CS (_UL_(1) << 11)
1854 #define PIN_PA08H_QSPI_DATA0 _L_(8)
1855 #define MUX_PA08H_QSPI_DATA0 _L_(7)
1856 #define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0)
1857 #define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8)
1858 #define PIN_PA09H_QSPI_DATA1 _L_(9)
1859 #define MUX_PA09H_QSPI_DATA1 _L_(7)
1860 #define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1)
1861 #define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9)
1862 #define PIN_PA10H_QSPI_DATA2 _L_(10)
1863 #define MUX_PA10H_QSPI_DATA2 _L_(7)
1864 #define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2)
1865 #define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10)
1866 #define PIN_PA11H_QSPI_DATA3 _L_(11)
1867 #define MUX_PA11H_QSPI_DATA3 _L_(7)
1868 #define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3)
1869 #define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11)
1870 #define PIN_PB10H_QSPI_SCK _L_(42)
1871 #define MUX_PB10H_QSPI_SCK _L_(7)
1872 #define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK)
1873 #define PORT_PB10H_QSPI_SCK (_UL_(1) << 10)
1875 #define PIN_PA04N_CCL_IN0 _L_(4)
1876 #define MUX_PA04N_CCL_IN0 _L_(13)
1877 #define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0)
1878 #define PORT_PA04N_CCL_IN0 (_UL_(1) << 4)
1879 #define PIN_PA16N_CCL_IN0 _L_(16)
1880 #define MUX_PA16N_CCL_IN0 _L_(13)
1881 #define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0)
1882 #define PORT_PA16N_CCL_IN0 (_UL_(1) << 16)
1883 #define PIN_PB22N_CCL_IN0 _L_(54)
1884 #define MUX_PB22N_CCL_IN0 _L_(13)
1885 #define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0)
1886 #define PORT_PB22N_CCL_IN0 (_UL_(1) << 22)
1887 #define PIN_PA05N_CCL_IN1 _L_(5)
1888 #define MUX_PA05N_CCL_IN1 _L_(13)
1889 #define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1)
1890 #define PORT_PA05N_CCL_IN1 (_UL_(1) << 5)
1891 #define PIN_PA17N_CCL_IN1 _L_(17)
1892 #define MUX_PA17N_CCL_IN1 _L_(13)
1893 #define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1)
1894 #define PORT_PA17N_CCL_IN1 (_UL_(1) << 17)
1895 #define PIN_PB00N_CCL_IN1 _L_(32)
1896 #define MUX_PB00N_CCL_IN1 _L_(13)
1897 #define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1)
1898 #define PORT_PB00N_CCL_IN1 (_UL_(1) << 0)
1899 #define PIN_PA06N_CCL_IN2 _L_(6)
1900 #define MUX_PA06N_CCL_IN2 _L_(13)
1901 #define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2)
1902 #define PORT_PA06N_CCL_IN2 (_UL_(1) << 6)
1903 #define PIN_PA18N_CCL_IN2 _L_(18)
1904 #define MUX_PA18N_CCL_IN2 _L_(13)
1905 #define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2)
1906 #define PORT_PA18N_CCL_IN2 (_UL_(1) << 18)
1907 #define PIN_PB01N_CCL_IN2 _L_(33)
1908 #define MUX_PB01N_CCL_IN2 _L_(13)
1909 #define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2)
1910 #define PORT_PB01N_CCL_IN2 (_UL_(1) << 1)
1911 #define PIN_PA08N_CCL_IN3 _L_(8)
1912 #define MUX_PA08N_CCL_IN3 _L_(13)
1913 #define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3)
1914 #define PORT_PA08N_CCL_IN3 (_UL_(1) << 8)
1915 #define PIN_PA30N_CCL_IN3 _L_(30)
1916 #define MUX_PA30N_CCL_IN3 _L_(13)
1917 #define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3)
1918 #define PORT_PA30N_CCL_IN3 (_UL_(1) << 30)
1919 #define PIN_PA09N_CCL_IN4 _L_(9)
1920 #define MUX_PA09N_CCL_IN4 _L_(13)
1921 #define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4)
1922 #define PORT_PA09N_CCL_IN4 (_UL_(1) << 9)
1923 #define PIN_PC27N_CCL_IN4 _L_(91)
1924 #define MUX_PC27N_CCL_IN4 _L_(13)
1925 #define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4)
1926 #define PORT_PC27N_CCL_IN4 (_UL_(1) << 27)
1927 #define PIN_PA10N_CCL_IN5 _L_(10)
1928 #define MUX_PA10N_CCL_IN5 _L_(13)
1929 #define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5)
1930 #define PORT_PA10N_CCL_IN5 (_UL_(1) << 10)
1931 #define PIN_PC28N_CCL_IN5 _L_(92)
1932 #define MUX_PC28N_CCL_IN5 _L_(13)
1933 #define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5)
1934 #define PORT_PC28N_CCL_IN5 (_UL_(1) << 28)
1935 #define PIN_PA22N_CCL_IN6 _L_(22)
1936 #define MUX_PA22N_CCL_IN6 _L_(13)
1937 #define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6)
1938 #define PORT_PA22N_CCL_IN6 (_UL_(1) << 22)
1939 #define PIN_PB06N_CCL_IN6 _L_(38)
1940 #define MUX_PB06N_CCL_IN6 _L_(13)
1941 #define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6)
1942 #define PORT_PB06N_CCL_IN6 (_UL_(1) << 6)
1943 #define PIN_PA23N_CCL_IN7 _L_(23)
1944 #define MUX_PA23N_CCL_IN7 _L_(13)
1945 #define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7)
1946 #define PORT_PA23N_CCL_IN7 (_UL_(1) << 23)
1947 #define PIN_PB07N_CCL_IN7 _L_(39)
1948 #define MUX_PB07N_CCL_IN7 _L_(13)
1949 #define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7)
1950 #define PORT_PB07N_CCL_IN7 (_UL_(1) << 7)
1951 #define PIN_PA24N_CCL_IN8 _L_(24)
1952 #define MUX_PA24N_CCL_IN8 _L_(13)
1953 #define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8)
1954 #define PORT_PA24N_CCL_IN8 (_UL_(1) << 24)
1955 #define PIN_PB08N_CCL_IN8 _L_(40)
1956 #define MUX_PB08N_CCL_IN8 _L_(13)
1957 #define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8)
1958 #define PORT_PB08N_CCL_IN8 (_UL_(1) << 8)
1959 #define PIN_PB14N_CCL_IN9 _L_(46)
1960 #define MUX_PB14N_CCL_IN9 _L_(13)
1961 #define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9)
1962 #define PORT_PB14N_CCL_IN9 (_UL_(1) << 14)
1963 #define PIN_PC20N_CCL_IN9 _L_(84)
1964 #define MUX_PC20N_CCL_IN9 _L_(13)
1965 #define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9)
1966 #define PORT_PC20N_CCL_IN9 (_UL_(1) << 20)
1967 #define PIN_PB15N_CCL_IN10 _L_(47)
1968 #define MUX_PB15N_CCL_IN10 _L_(13)
1969 #define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10)
1970 #define PORT_PB15N_CCL_IN10 (_UL_(1) << 15)
1971 #define PIN_PC21N_CCL_IN10 _L_(85)
1972 #define MUX_PC21N_CCL_IN10 _L_(13)
1973 #define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10)
1974 #define PORT_PC21N_CCL_IN10 (_UL_(1) << 21)
1975 #define PIN_PB10N_CCL_IN11 _L_(42)
1976 #define MUX_PB10N_CCL_IN11 _L_(13)
1977 #define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11)
1978 #define PORT_PB10N_CCL_IN11 (_UL_(1) << 10)
1979 #define PIN_PB16N_CCL_IN11 _L_(48)
1980 #define MUX_PB16N_CCL_IN11 _L_(13)
1981 #define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11)
1982 #define PORT_PB16N_CCL_IN11 (_UL_(1) << 16)
1983 #define PIN_PA07N_CCL_OUT0 _L_(7)
1984 #define MUX_PA07N_CCL_OUT0 _L_(13)
1985 #define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0)
1986 #define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7)
1987 #define PIN_PA19N_CCL_OUT0 _L_(19)
1988 #define MUX_PA19N_CCL_OUT0 _L_(13)
1989 #define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0)
1990 #define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19)
1991 #define PIN_PB02N_CCL_OUT0 _L_(34)
1992 #define MUX_PB02N_CCL_OUT0 _L_(13)
1993 #define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0)
1994 #define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2)
1995 #define PIN_PB23N_CCL_OUT0 _L_(55)
1996 #define MUX_PB23N_CCL_OUT0 _L_(13)
1997 #define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0)
1998 #define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23)
1999 #define PIN_PA11N_CCL_OUT1 _L_(11)
2000 #define MUX_PA11N_CCL_OUT1 _L_(13)
2001 #define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1)
2002 #define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11)
2003 #define PIN_PA31N_CCL_OUT1 _L_(31)
2004 #define MUX_PA31N_CCL_OUT1 _L_(13)
2005 #define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1)
2006 #define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31)
2007 #define PIN_PB11N_CCL_OUT1 _L_(43)
2008 #define MUX_PB11N_CCL_OUT1 _L_(13)
2009 #define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1)
2010 #define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11)
2011 #define PIN_PA25N_CCL_OUT2 _L_(25)
2012 #define MUX_PA25N_CCL_OUT2 _L_(13)
2013 #define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2)
2014 #define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25)
2015 #define PIN_PB09N_CCL_OUT2 _L_(41)
2016 #define MUX_PB09N_CCL_OUT2 _L_(13)
2017 #define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2)
2018 #define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9)
2019 #define PIN_PB17N_CCL_OUT3 _L_(49)
2020 #define MUX_PB17N_CCL_OUT3 _L_(13)
2021 #define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3)
2022 #define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17)
2024 #define PIN_PA13D_SERCOM4_PAD0 _L_(13)
2025 #define MUX_PA13D_SERCOM4_PAD0 _L_(3)
2026 #define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0)
2027 #define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13)
2028 #define PIN_PB08D_SERCOM4_PAD0 _L_(40)
2029 #define MUX_PB08D_SERCOM4_PAD0 _L_(3)
2030 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0)
2031 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8)
2032 #define PIN_PB27D_SERCOM4_PAD0 _L_(59)
2033 #define MUX_PB27D_SERCOM4_PAD0 _L_(3)
2034 #define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0)
2035 #define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27)
2036 #define PIN_PB12C_SERCOM4_PAD0 _L_(44)
2037 #define MUX_PB12C_SERCOM4_PAD0 _L_(2)
2038 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0)
2039 #define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12)
2040 #define PIN_PA12D_SERCOM4_PAD1 _L_(12)
2041 #define MUX_PA12D_SERCOM4_PAD1 _L_(3)
2042 #define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1)
2043 #define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12)
2044 #define PIN_PB09D_SERCOM4_PAD1 _L_(41)
2045 #define MUX_PB09D_SERCOM4_PAD1 _L_(3)
2046 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1)
2047 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9)
2048 #define PIN_PB26D_SERCOM4_PAD1 _L_(58)
2049 #define MUX_PB26D_SERCOM4_PAD1 _L_(3)
2050 #define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1)
2051 #define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26)
2052 #define PIN_PB13C_SERCOM4_PAD1 _L_(45)
2053 #define MUX_PB13C_SERCOM4_PAD1 _L_(2)
2054 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1)
2055 #define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13)
2056 #define PIN_PA14D_SERCOM4_PAD2 _L_(14)
2057 #define MUX_PA14D_SERCOM4_PAD2 _L_(3)
2058 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2)
2059 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14)
2060 #define PIN_PB10D_SERCOM4_PAD2 _L_(42)
2061 #define MUX_PB10D_SERCOM4_PAD2 _L_(3)
2062 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2)
2063 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10)
2064 #define PIN_PB28D_SERCOM4_PAD2 _L_(60)
2065 #define MUX_PB28D_SERCOM4_PAD2 _L_(3)
2066 #define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2)
2067 #define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28)
2068 #define PIN_PB14C_SERCOM4_PAD2 _L_(46)
2069 #define MUX_PB14C_SERCOM4_PAD2 _L_(2)
2070 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2)
2071 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14)
2072 #define PIN_PB11D_SERCOM4_PAD3 _L_(43)
2073 #define MUX_PB11D_SERCOM4_PAD3 _L_(3)
2074 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3)
2075 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11)
2076 #define PIN_PB29D_SERCOM4_PAD3 _L_(61)
2077 #define MUX_PB29D_SERCOM4_PAD3 _L_(3)
2078 #define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3)
2079 #define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29)
2080 #define PIN_PA15D_SERCOM4_PAD3 _L_(15)
2081 #define MUX_PA15D_SERCOM4_PAD3 _L_(3)
2082 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3)
2083 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15)
2084 #define PIN_PB15C_SERCOM4_PAD3 _L_(47)
2085 #define MUX_PB15C_SERCOM4_PAD3 _L_(2)
2086 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3)
2087 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15)
2089 #define PIN_PA23D_SERCOM5_PAD0 _L_(23)
2090 #define MUX_PA23D_SERCOM5_PAD0 _L_(3)
2091 #define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0)
2092 #define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23)
2093 #define PIN_PB02D_SERCOM5_PAD0 _L_(34)
2094 #define MUX_PB02D_SERCOM5_PAD0 _L_(3)
2095 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0)
2096 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2)
2097 #define PIN_PB31D_SERCOM5_PAD0 _L_(63)
2098 #define MUX_PB31D_SERCOM5_PAD0 _L_(3)
2099 #define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0)
2100 #define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31)
2101 #define PIN_PB16C_SERCOM5_PAD0 _L_(48)
2102 #define MUX_PB16C_SERCOM5_PAD0 _L_(2)
2103 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0)
2104 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16)
2105 #define PIN_PA22D_SERCOM5_PAD1 _L_(22)
2106 #define MUX_PA22D_SERCOM5_PAD1 _L_(3)
2107 #define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1)
2108 #define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22)
2109 #define PIN_PB03D_SERCOM5_PAD1 _L_(35)
2110 #define MUX_PB03D_SERCOM5_PAD1 _L_(3)
2111 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1)
2112 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3)
2113 #define PIN_PB30D_SERCOM5_PAD1 _L_(62)
2114 #define MUX_PB30D_SERCOM5_PAD1 _L_(3)
2115 #define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1)
2116 #define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30)
2117 #define PIN_PB17C_SERCOM5_PAD1 _L_(49)
2118 #define MUX_PB17C_SERCOM5_PAD1 _L_(2)
2119 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1)
2120 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17)
2121 #define PIN_PA24D_SERCOM5_PAD2 _L_(24)
2122 #define MUX_PA24D_SERCOM5_PAD2 _L_(3)
2123 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2)
2124 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24)
2125 #define PIN_PB00D_SERCOM5_PAD2 _L_(32)
2126 #define MUX_PB00D_SERCOM5_PAD2 _L_(3)
2127 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2)
2128 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0)
2129 #define PIN_PB22D_SERCOM5_PAD2 _L_(54)
2130 #define MUX_PB22D_SERCOM5_PAD2 _L_(3)
2131 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2)
2132 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22)
2133 #define PIN_PA20C_SERCOM5_PAD2 _L_(20)
2134 #define MUX_PA20C_SERCOM5_PAD2 _L_(2)
2135 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2)
2136 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20)
2137 #define PIN_PB18C_SERCOM5_PAD2 _L_(50)
2138 #define MUX_PB18C_SERCOM5_PAD2 _L_(2)
2139 #define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2)
2140 #define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18)
2141 #define PIN_PA25D_SERCOM5_PAD3 _L_(25)
2142 #define MUX_PA25D_SERCOM5_PAD3 _L_(3)
2143 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3)
2144 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25)
2145 #define PIN_PB01D_SERCOM5_PAD3 _L_(33)
2146 #define MUX_PB01D_SERCOM5_PAD3 _L_(3)
2147 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3)
2148 #define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1)
2149 #define PIN_PB23D_SERCOM5_PAD3 _L_(55)
2150 #define MUX_PB23D_SERCOM5_PAD3 _L_(3)
2151 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3)
2152 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23)
2153 #define PIN_PA21C_SERCOM5_PAD3 _L_(21)
2154 #define MUX_PA21C_SERCOM5_PAD3 _L_(2)
2155 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3)
2156 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21)
2157 #define PIN_PB19C_SERCOM5_PAD3 _L_(51)
2158 #define MUX_PB19C_SERCOM5_PAD3 _L_(2)
2159 #define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3)
2160 #define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19)
2162 #define PIN_PD09D_SERCOM6_PAD0 _L_(105)
2163 #define MUX_PD09D_SERCOM6_PAD0 _L_(3)
2164 #define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0)
2165 #define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9)
2166 #define PIN_PC13D_SERCOM6_PAD0 _L_(77)
2167 #define MUX_PC13D_SERCOM6_PAD0 _L_(3)
2168 #define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0)
2169 #define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13)
2170 #define PIN_PC04C_SERCOM6_PAD0 _L_(68)
2171 #define MUX_PC04C_SERCOM6_PAD0 _L_(2)
2172 #define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0)
2173 #define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4)
2174 #define PIN_PC16C_SERCOM6_PAD0 _L_(80)
2175 #define MUX_PC16C_SERCOM6_PAD0 _L_(2)
2176 #define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0)
2177 #define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16)
2178 #define PIN_PD08D_SERCOM6_PAD1 _L_(104)
2179 #define MUX_PD08D_SERCOM6_PAD1 _L_(3)
2180 #define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1)
2181 #define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8)
2182 #define PIN_PC12D_SERCOM6_PAD1 _L_(76)
2183 #define MUX_PC12D_SERCOM6_PAD1 _L_(3)
2184 #define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1)
2185 #define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12)
2186 #define PIN_PC05C_SERCOM6_PAD1 _L_(69)
2187 #define MUX_PC05C_SERCOM6_PAD1 _L_(2)
2188 #define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1)
2189 #define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5)
2190 #define PIN_PC17C_SERCOM6_PAD1 _L_(81)
2191 #define MUX_PC17C_SERCOM6_PAD1 _L_(2)
2192 #define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1)
2193 #define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17)
2194 #define PIN_PC14D_SERCOM6_PAD2 _L_(78)
2195 #define MUX_PC14D_SERCOM6_PAD2 _L_(3)
2196 #define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2)
2197 #define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14)
2198 #define PIN_PD10D_SERCOM6_PAD2 _L_(106)
2199 #define MUX_PD10D_SERCOM6_PAD2 _L_(3)
2200 #define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2)
2201 #define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10)
2202 #define PIN_PC06C_SERCOM6_PAD2 _L_(70)
2203 #define MUX_PC06C_SERCOM6_PAD2 _L_(2)
2204 #define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2)
2205 #define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6)
2206 #define PIN_PC10C_SERCOM6_PAD2 _L_(74)
2207 #define MUX_PC10C_SERCOM6_PAD2 _L_(2)
2208 #define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2)
2209 #define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10)
2210 #define PIN_PC18C_SERCOM6_PAD2 _L_(82)
2211 #define MUX_PC18C_SERCOM6_PAD2 _L_(2)
2212 #define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2)
2213 #define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18)
2214 #define PIN_PC15D_SERCOM6_PAD3 _L_(79)
2215 #define MUX_PC15D_SERCOM6_PAD3 _L_(3)
2216 #define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3)
2217 #define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15)
2218 #define PIN_PD11D_SERCOM6_PAD3 _L_(107)
2219 #define MUX_PD11D_SERCOM6_PAD3 _L_(3)
2220 #define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3)
2221 #define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11)
2222 #define PIN_PC07C_SERCOM6_PAD3 _L_(71)
2223 #define MUX_PC07C_SERCOM6_PAD3 _L_(2)
2224 #define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3)
2225 #define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7)
2226 #define PIN_PC11C_SERCOM6_PAD3 _L_(75)
2227 #define MUX_PC11C_SERCOM6_PAD3 _L_(2)
2228 #define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3)
2229 #define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11)
2230 #define PIN_PC19C_SERCOM6_PAD3 _L_(83)
2231 #define MUX_PC19C_SERCOM6_PAD3 _L_(2)
2232 #define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3)
2233 #define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19)
2235 #define PIN_PB21D_SERCOM7_PAD0 _L_(53)
2236 #define MUX_PB21D_SERCOM7_PAD0 _L_(3)
2237 #define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0)
2238 #define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21)
2239 #define PIN_PD08C_SERCOM7_PAD0 _L_(104)
2240 #define MUX_PD08C_SERCOM7_PAD0 _L_(2)
2241 #define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0)
2242 #define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8)
2243 #define PIN_PB30C_SERCOM7_PAD0 _L_(62)
2244 #define MUX_PB30C_SERCOM7_PAD0 _L_(2)
2245 #define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0)
2246 #define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30)
2247 #define PIN_PC12C_SERCOM7_PAD0 _L_(76)
2248 #define MUX_PC12C_SERCOM7_PAD0 _L_(2)
2249 #define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0)
2250 #define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12)
2251 #define PIN_PB20D_SERCOM7_PAD1 _L_(52)
2252 #define MUX_PB20D_SERCOM7_PAD1 _L_(3)
2253 #define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1)
2254 #define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20)
2255 #define PIN_PD09C_SERCOM7_PAD1 _L_(105)
2256 #define MUX_PD09C_SERCOM7_PAD1 _L_(2)
2257 #define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1)
2258 #define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9)
2259 #define PIN_PB31C_SERCOM7_PAD1 _L_(63)
2260 #define MUX_PB31C_SERCOM7_PAD1 _L_(2)
2261 #define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1)
2262 #define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31)
2263 #define PIN_PC13C_SERCOM7_PAD1 _L_(77)
2264 #define MUX_PC13C_SERCOM7_PAD1 _L_(2)
2265 #define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1)
2266 #define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13)
2267 #define PIN_PB18D_SERCOM7_PAD2 _L_(50)
2268 #define MUX_PB18D_SERCOM7_PAD2 _L_(3)
2269 #define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2)
2270 #define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18)
2271 #define PIN_PC10D_SERCOM7_PAD2 _L_(74)
2272 #define MUX_PC10D_SERCOM7_PAD2 _L_(3)
2273 #define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2)
2274 #define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10)
2275 #define PIN_PC14C_SERCOM7_PAD2 _L_(78)
2276 #define MUX_PC14C_SERCOM7_PAD2 _L_(2)
2277 #define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2)
2278 #define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14)
2279 #define PIN_PD10C_SERCOM7_PAD2 _L_(106)
2280 #define MUX_PD10C_SERCOM7_PAD2 _L_(2)
2281 #define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2)
2282 #define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10)
2283 #define PIN_PA30C_SERCOM7_PAD2 _L_(30)
2284 #define MUX_PA30C_SERCOM7_PAD2 _L_(2)
2285 #define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2)
2286 #define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30)
2287 #define PIN_PB19D_SERCOM7_PAD3 _L_(51)
2288 #define MUX_PB19D_SERCOM7_PAD3 _L_(3)
2289 #define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3)
2290 #define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19)
2291 #define PIN_PC11D_SERCOM7_PAD3 _L_(75)
2292 #define MUX_PC11D_SERCOM7_PAD3 _L_(3)
2293 #define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3)
2294 #define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11)
2295 #define PIN_PC15C_SERCOM7_PAD3 _L_(79)
2296 #define MUX_PC15C_SERCOM7_PAD3 _L_(2)
2297 #define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3)
2298 #define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15)
2299 #define PIN_PD11C_SERCOM7_PAD3 _L_(107)
2300 #define MUX_PD11C_SERCOM7_PAD3 _L_(2)
2301 #define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3)
2302 #define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11)
2303 #define PIN_PA31C_SERCOM7_PAD3 _L_(31)
2304 #define MUX_PA31C_SERCOM7_PAD3 _L_(2)
2305 #define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3)
2306 #define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31)
2308 #define PIN_PB14F_TCC4_WO0 _L_(46)
2309 #define MUX_PB14F_TCC4_WO0 _L_(5)
2310 #define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0)
2311 #define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14)
2312 #define PIN_PB30F_TCC4_WO0 _L_(62)
2313 #define MUX_PB30F_TCC4_WO0 _L_(5)
2314 #define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0)
2315 #define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30)
2316 #define PIN_PB15F_TCC4_WO1 _L_(47)
2317 #define MUX_PB15F_TCC4_WO1 _L_(5)
2318 #define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1)
2319 #define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15)
2320 #define PIN_PB31F_TCC4_WO1 _L_(63)
2321 #define MUX_PB31F_TCC4_WO1 _L_(5)
2322 #define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1)
2323 #define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31)
2325 #define PIN_PA30E_TC6_WO0 _L_(30)
2326 #define MUX_PA30E_TC6_WO0 _L_(4)
2327 #define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0)
2328 #define PORT_PA30E_TC6_WO0 (_UL_(1) << 30)
2329 #define PIN_PB02E_TC6_WO0 _L_(34)
2330 #define MUX_PB02E_TC6_WO0 _L_(4)
2331 #define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0)
2332 #define PORT_PB02E_TC6_WO0 (_UL_(1) << 2)
2333 #define PIN_PB16E_TC6_WO0 _L_(48)
2334 #define MUX_PB16E_TC6_WO0 _L_(4)
2335 #define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0)
2336 #define PORT_PB16E_TC6_WO0 (_UL_(1) << 16)
2337 #define PIN_PA31E_TC6_WO1 _L_(31)
2338 #define MUX_PA31E_TC6_WO1 _L_(4)
2339 #define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1)
2340 #define PORT_PA31E_TC6_WO1 (_UL_(1) << 31)
2341 #define PIN_PB03E_TC6_WO1 _L_(35)
2342 #define MUX_PB03E_TC6_WO1 _L_(4)
2343 #define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1)
2344 #define PORT_PB03E_TC6_WO1 (_UL_(1) << 3)
2345 #define PIN_PB17E_TC6_WO1 _L_(49)
2346 #define MUX_PB17E_TC6_WO1 _L_(4)
2347 #define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1)
2348 #define PORT_PB17E_TC6_WO1 (_UL_(1) << 17)
2350 #define PIN_PA20E_TC7_WO0 _L_(20)
2351 #define MUX_PA20E_TC7_WO0 _L_(4)
2352 #define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0)
2353 #define PORT_PA20E_TC7_WO0 (_UL_(1) << 20)
2354 #define PIN_PB00E_TC7_WO0 _L_(32)
2355 #define MUX_PB00E_TC7_WO0 _L_(4)
2356 #define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0)
2357 #define PORT_PB00E_TC7_WO0 (_UL_(1) << 0)
2358 #define PIN_PB22E_TC7_WO0 _L_(54)
2359 #define MUX_PB22E_TC7_WO0 _L_(4)
2360 #define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0)
2361 #define PORT_PB22E_TC7_WO0 (_UL_(1) << 22)
2362 #define PIN_PA21E_TC7_WO1 _L_(21)
2363 #define MUX_PA21E_TC7_WO1 _L_(4)
2364 #define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1)
2365 #define PORT_PA21E_TC7_WO1 (_UL_(1) << 21)
2366 #define PIN_PB01E_TC7_WO1 _L_(33)
2367 #define MUX_PB01E_TC7_WO1 _L_(4)
2368 #define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1)
2369 #define PORT_PB01E_TC7_WO1 (_UL_(1) << 1)
2370 #define PIN_PB23E_TC7_WO1 _L_(55)
2371 #define MUX_PB23E_TC7_WO1 _L_(4)
2372 #define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1)
2373 #define PORT_PB23E_TC7_WO1 (_UL_(1) << 23)
2375 #define PIN_PA02B_ADC0_AIN0 _L_(2)
2376 #define MUX_PA02B_ADC0_AIN0 _L_(1)
2377 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
2378 #define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
2379 #define PIN_PA03B_ADC0_AIN1 _L_(3)
2380 #define MUX_PA03B_ADC0_AIN1 _L_(1)
2381 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
2382 #define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
2383 #define PIN_PB08B_ADC0_AIN2 _L_(40)
2384 #define MUX_PB08B_ADC0_AIN2 _L_(1)
2385 #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2)
2386 #define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8)
2387 #define PIN_PB09B_ADC0_AIN3 _L_(41)
2388 #define MUX_PB09B_ADC0_AIN3 _L_(1)
2389 #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3)
2390 #define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9)
2391 #define PIN_PA04B_ADC0_AIN4 _L_(4)
2392 #define MUX_PA04B_ADC0_AIN4 _L_(1)
2393 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
2394 #define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
2395 #define PIN_PA05B_ADC0_AIN5 _L_(5)
2396 #define MUX_PA05B_ADC0_AIN5 _L_(1)
2397 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
2398 #define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
2399 #define PIN_PA06B_ADC0_AIN6 _L_(6)
2400 #define MUX_PA06B_ADC0_AIN6 _L_(1)
2401 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
2402 #define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
2403 #define PIN_PA07B_ADC0_AIN7 _L_(7)
2404 #define MUX_PA07B_ADC0_AIN7 _L_(1)
2405 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
2406 #define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
2407 #define PIN_PA08B_ADC0_AIN8 _L_(8)
2408 #define MUX_PA08B_ADC0_AIN8 _L_(1)
2409 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
2410 #define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
2411 #define PIN_PA09B_ADC0_AIN9 _L_(9)
2412 #define MUX_PA09B_ADC0_AIN9 _L_(1)
2413 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
2414 #define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
2415 #define PIN_PA10B_ADC0_AIN10 _L_(10)
2416 #define MUX_PA10B_ADC0_AIN10 _L_(1)
2417 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
2418 #define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
2419 #define PIN_PA11B_ADC0_AIN11 _L_(11)
2420 #define MUX_PA11B_ADC0_AIN11 _L_(1)
2421 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
2422 #define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
2423 #define PIN_PB00B_ADC0_AIN12 _L_(32)
2424 #define MUX_PB00B_ADC0_AIN12 _L_(1)
2425 #define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12)
2426 #define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0)
2427 #define PIN_PB01B_ADC0_AIN13 _L_(33)
2428 #define MUX_PB01B_ADC0_AIN13 _L_(1)
2429 #define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13)
2430 #define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1)
2431 #define PIN_PB02B_ADC0_AIN14 _L_(34)
2432 #define MUX_PB02B_ADC0_AIN14 _L_(1)
2433 #define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14)
2434 #define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2)
2435 #define PIN_PB03B_ADC0_AIN15 _L_(35)
2436 #define MUX_PB03B_ADC0_AIN15 _L_(1)
2437 #define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15)
2438 #define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3)
2439 #define PIN_PA03O_ADC0_DRV0 _L_(3)
2440 #define MUX_PA03O_ADC0_DRV0 _L_(14)
2441 #define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0)
2442 #define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3)
2443 #define PIN_PB08O_ADC0_DRV1 _L_(40)
2444 #define MUX_PB08O_ADC0_DRV1 _L_(14)
2445 #define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1)
2446 #define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8)
2447 #define PIN_PB09O_ADC0_DRV2 _L_(41)
2448 #define MUX_PB09O_ADC0_DRV2 _L_(14)
2449 #define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2)
2450 #define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9)
2451 #define PIN_PA04O_ADC0_DRV3 _L_(4)
2452 #define MUX_PA04O_ADC0_DRV3 _L_(14)
2453 #define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3)
2454 #define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4)
2455 #define PIN_PA06O_ADC0_DRV4 _L_(6)
2456 #define MUX_PA06O_ADC0_DRV4 _L_(14)
2457 #define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4)
2458 #define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6)
2459 #define PIN_PA07O_ADC0_DRV5 _L_(7)
2460 #define MUX_PA07O_ADC0_DRV5 _L_(14)
2461 #define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5)
2462 #define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7)
2463 #define PIN_PA08O_ADC0_DRV6 _L_(8)
2464 #define MUX_PA08O_ADC0_DRV6 _L_(14)
2465 #define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6)
2466 #define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8)
2467 #define PIN_PA09O_ADC0_DRV7 _L_(9)
2468 #define MUX_PA09O_ADC0_DRV7 _L_(14)
2469 #define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7)
2470 #define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9)
2471 #define PIN_PA10O_ADC0_DRV8 _L_(10)
2472 #define MUX_PA10O_ADC0_DRV8 _L_(14)
2473 #define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8)
2474 #define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10)
2475 #define PIN_PA11O_ADC0_DRV9 _L_(11)
2476 #define MUX_PA11O_ADC0_DRV9 _L_(14)
2477 #define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9)
2478 #define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11)
2479 #define PIN_PA16O_ADC0_DRV10 _L_(16)
2480 #define MUX_PA16O_ADC0_DRV10 _L_(14)
2481 #define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10)
2482 #define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16)
2483 #define PIN_PA17O_ADC0_DRV11 _L_(17)
2484 #define MUX_PA17O_ADC0_DRV11 _L_(14)
2485 #define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11)
2486 #define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17)
2487 #define PIN_PA18O_ADC0_DRV12 _L_(18)
2488 #define MUX_PA18O_ADC0_DRV12 _L_(14)
2489 #define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12)
2490 #define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18)
2491 #define PIN_PA19O_ADC0_DRV13 _L_(19)
2492 #define MUX_PA19O_ADC0_DRV13 _L_(14)
2493 #define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13)
2494 #define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19)
2495 #define PIN_PA20O_ADC0_DRV14 _L_(20)
2496 #define MUX_PA20O_ADC0_DRV14 _L_(14)
2497 #define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14)
2498 #define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20)
2499 #define PIN_PA21O_ADC0_DRV15 _L_(21)
2500 #define MUX_PA21O_ADC0_DRV15 _L_(14)
2501 #define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15)
2502 #define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21)
2503 #define PIN_PA22O_ADC0_DRV16 _L_(22)
2504 #define MUX_PA22O_ADC0_DRV16 _L_(14)
2505 #define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16)
2506 #define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22)
2507 #define PIN_PA23O_ADC0_DRV17 _L_(23)
2508 #define MUX_PA23O_ADC0_DRV17 _L_(14)
2509 #define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17)
2510 #define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23)
2511 #define PIN_PA27O_ADC0_DRV18 _L_(27)
2512 #define MUX_PA27O_ADC0_DRV18 _L_(14)
2513 #define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18)
2514 #define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27)
2515 #define PIN_PA30O_ADC0_DRV19 _L_(30)
2516 #define MUX_PA30O_ADC0_DRV19 _L_(14)
2517 #define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19)
2518 #define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30)
2519 #define PIN_PB02O_ADC0_DRV20 _L_(34)
2520 #define MUX_PB02O_ADC0_DRV20 _L_(14)
2521 #define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20)
2522 #define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2)
2523 #define PIN_PB03O_ADC0_DRV21 _L_(35)
2524 #define MUX_PB03O_ADC0_DRV21 _L_(14)
2525 #define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21)
2526 #define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3)
2527 #define PIN_PB04O_ADC0_DRV22 _L_(36)
2528 #define MUX_PB04O_ADC0_DRV22 _L_(14)
2529 #define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22)
2530 #define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4)
2531 #define PIN_PB05O_ADC0_DRV23 _L_(37)
2532 #define MUX_PB05O_ADC0_DRV23 _L_(14)
2533 #define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23)
2534 #define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5)
2535 #define PIN_PB06O_ADC0_DRV24 _L_(38)
2536 #define MUX_PB06O_ADC0_DRV24 _L_(14)
2537 #define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24)
2538 #define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6)
2539 #define PIN_PB07O_ADC0_DRV25 _L_(39)
2540 #define MUX_PB07O_ADC0_DRV25 _L_(14)
2541 #define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25)
2542 #define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7)
2543 #define PIN_PB12O_ADC0_DRV26 _L_(44)
2544 #define MUX_PB12O_ADC0_DRV26 _L_(14)
2545 #define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26)
2546 #define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12)
2547 #define PIN_PB13O_ADC0_DRV27 _L_(45)
2548 #define MUX_PB13O_ADC0_DRV27 _L_(14)
2549 #define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27)
2550 #define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13)
2551 #define PIN_PB14O_ADC0_DRV28 _L_(46)
2552 #define MUX_PB14O_ADC0_DRV28 _L_(14)
2553 #define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28)
2554 #define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14)
2555 #define PIN_PB15O_ADC0_DRV29 _L_(47)
2556 #define MUX_PB15O_ADC0_DRV29 _L_(14)
2557 #define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29)
2558 #define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15)
2559 #define PIN_PB00O_ADC0_DRV30 _L_(32)
2560 #define MUX_PB00O_ADC0_DRV30 _L_(14)
2561 #define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30)
2562 #define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0)
2563 #define PIN_PB01O_ADC0_DRV31 _L_(33)
2564 #define MUX_PB01O_ADC0_DRV31 _L_(14)
2565 #define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31)
2566 #define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1)
2567 #define PIN_PA03B_ADC0_PTCXY0 _L_(3)
2568 #define MUX_PA03B_ADC0_PTCXY0 _L_(1)
2569 #define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0)
2570 #define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3)
2571 #define PIN_PB08B_ADC0_PTCXY1 _L_(40)
2572 #define MUX_PB08B_ADC0_PTCXY1 _L_(1)
2573 #define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1)
2574 #define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8)
2575 #define PIN_PB09B_ADC0_PTCXY2 _L_(41)
2576 #define MUX_PB09B_ADC0_PTCXY2 _L_(1)
2577 #define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2)
2578 #define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9)
2579 #define PIN_PA04B_ADC0_PTCXY3 _L_(4)
2580 #define MUX_PA04B_ADC0_PTCXY3 _L_(1)
2581 #define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3)
2582 #define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4)
2583 #define PIN_PA06B_ADC0_PTCXY4 _L_(6)
2584 #define MUX_PA06B_ADC0_PTCXY4 _L_(1)
2585 #define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4)
2586 #define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6)
2587 #define PIN_PA07B_ADC0_PTCXY5 _L_(7)
2588 #define MUX_PA07B_ADC0_PTCXY5 _L_(1)
2589 #define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5)
2590 #define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7)
2591 #define PIN_PA08B_ADC0_PTCXY6 _L_(8)
2592 #define MUX_PA08B_ADC0_PTCXY6 _L_(1)
2593 #define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6)
2594 #define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8)
2595 #define PIN_PA09B_ADC0_PTCXY7 _L_(9)
2596 #define MUX_PA09B_ADC0_PTCXY7 _L_(1)
2597 #define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7)
2598 #define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9)
2599 #define PIN_PA10B_ADC0_PTCXY8 _L_(10)
2600 #define MUX_PA10B_ADC0_PTCXY8 _L_(1)
2601 #define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8)
2602 #define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10)
2603 #define PIN_PA11B_ADC0_PTCXY9 _L_(11)
2604 #define MUX_PA11B_ADC0_PTCXY9 _L_(1)
2605 #define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9)
2606 #define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11)
2607 #define PIN_PA16B_ADC0_PTCXY10 _L_(16)
2608 #define MUX_PA16B_ADC0_PTCXY10 _L_(1)
2609 #define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10)
2610 #define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16)
2611 #define PIN_PA17B_ADC0_PTCXY11 _L_(17)
2612 #define MUX_PA17B_ADC0_PTCXY11 _L_(1)
2613 #define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11)
2614 #define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17)
2615 #define PIN_PA18B_ADC0_PTCXY12 _L_(18)
2616 #define MUX_PA18B_ADC0_PTCXY12 _L_(1)
2617 #define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12)
2618 #define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18)
2619 #define PIN_PA19B_ADC0_PTCXY13 _L_(19)
2620 #define MUX_PA19B_ADC0_PTCXY13 _L_(1)
2621 #define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13)
2622 #define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19)
2623 #define PIN_PA20B_ADC0_PTCXY14 _L_(20)
2624 #define MUX_PA20B_ADC0_PTCXY14 _L_(1)
2625 #define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14)
2626 #define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20)
2627 #define PIN_PA21B_ADC0_PTCXY15 _L_(21)
2628 #define MUX_PA21B_ADC0_PTCXY15 _L_(1)
2629 #define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15)
2630 #define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21)
2631 #define PIN_PA22B_ADC0_PTCXY16 _L_(22)
2632 #define MUX_PA22B_ADC0_PTCXY16 _L_(1)
2633 #define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16)
2634 #define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22)
2635 #define PIN_PA23B_ADC0_PTCXY17 _L_(23)
2636 #define MUX_PA23B_ADC0_PTCXY17 _L_(1)
2637 #define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17)
2638 #define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23)
2639 #define PIN_PA27B_ADC0_PTCXY18 _L_(27)
2640 #define MUX_PA27B_ADC0_PTCXY18 _L_(1)
2641 #define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18)
2642 #define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27)
2643 #define PIN_PA30B_ADC0_PTCXY19 _L_(30)
2644 #define MUX_PA30B_ADC0_PTCXY19 _L_(1)
2645 #define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19)
2646 #define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30)
2647 #define PIN_PB02B_ADC0_PTCXY20 _L_(34)
2648 #define MUX_PB02B_ADC0_PTCXY20 _L_(1)
2649 #define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20)
2650 #define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2)
2651 #define PIN_PB03B_ADC0_PTCXY21 _L_(35)
2652 #define MUX_PB03B_ADC0_PTCXY21 _L_(1)
2653 #define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21)
2654 #define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3)
2655 #define PIN_PB04B_ADC0_PTCXY22 _L_(36)
2656 #define MUX_PB04B_ADC0_PTCXY22 _L_(1)
2657 #define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22)
2658 #define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4)
2659 #define PIN_PB05B_ADC0_PTCXY23 _L_(37)
2660 #define MUX_PB05B_ADC0_PTCXY23 _L_(1)
2661 #define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23)
2662 #define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5)
2663 #define PIN_PB06B_ADC0_PTCXY24 _L_(38)
2664 #define MUX_PB06B_ADC0_PTCXY24 _L_(1)
2665 #define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24)
2666 #define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6)
2667 #define PIN_PB07B_ADC0_PTCXY25 _L_(39)
2668 #define MUX_PB07B_ADC0_PTCXY25 _L_(1)
2669 #define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25)
2670 #define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7)
2671 #define PIN_PB12B_ADC0_PTCXY26 _L_(44)
2672 #define MUX_PB12B_ADC0_PTCXY26 _L_(1)
2673 #define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26)
2674 #define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12)
2675 #define PIN_PB13B_ADC0_PTCXY27 _L_(45)
2676 #define MUX_PB13B_ADC0_PTCXY27 _L_(1)
2677 #define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27)
2678 #define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13)
2679 #define PIN_PB14B_ADC0_PTCXY28 _L_(46)
2680 #define MUX_PB14B_ADC0_PTCXY28 _L_(1)
2681 #define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28)
2682 #define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14)
2683 #define PIN_PB15B_ADC0_PTCXY29 _L_(47)
2684 #define MUX_PB15B_ADC0_PTCXY29 _L_(1)
2685 #define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29)
2686 #define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15)
2687 #define PIN_PB00B_ADC0_PTCXY30 _L_(32)
2688 #define MUX_PB00B_ADC0_PTCXY30 _L_(1)
2689 #define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30)
2690 #define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0)
2691 #define PIN_PB01B_ADC0_PTCXY31 _L_(33)
2692 #define MUX_PB01B_ADC0_PTCXY31 _L_(1)
2693 #define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31)
2694 #define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1)
2696 #define PIN_PB08B_ADC1_AIN0 _L_(40)
2697 #define MUX_PB08B_ADC1_AIN0 _L_(1)
2698 #define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0)
2699 #define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8)
2700 #define PIN_PB09B_ADC1_AIN1 _L_(41)
2701 #define MUX_PB09B_ADC1_AIN1 _L_(1)
2702 #define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1)
2703 #define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9)
2704 #define PIN_PA08B_ADC1_AIN2 _L_(8)
2705 #define MUX_PA08B_ADC1_AIN2 _L_(1)
2706 #define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2)
2707 #define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8)
2708 #define PIN_PA09B_ADC1_AIN3 _L_(9)
2709 #define MUX_PA09B_ADC1_AIN3 _L_(1)
2710 #define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3)
2711 #define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9)
2712 #define PIN_PC02B_ADC1_AIN4 _L_(66)
2713 #define MUX_PC02B_ADC1_AIN4 _L_(1)
2714 #define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4)
2715 #define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2)
2716 #define PIN_PC03B_ADC1_AIN5 _L_(67)
2717 #define MUX_PC03B_ADC1_AIN5 _L_(1)
2718 #define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5)
2719 #define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3)
2720 #define PIN_PB04B_ADC1_AIN6 _L_(36)
2721 #define MUX_PB04B_ADC1_AIN6 _L_(1)
2722 #define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6)
2723 #define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4)
2724 #define PIN_PB05B_ADC1_AIN7 _L_(37)
2725 #define MUX_PB05B_ADC1_AIN7 _L_(1)
2726 #define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7)
2727 #define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5)
2728 #define PIN_PB06B_ADC1_AIN8 _L_(38)
2729 #define MUX_PB06B_ADC1_AIN8 _L_(1)
2730 #define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8)
2731 #define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6)
2732 #define PIN_PB07B_ADC1_AIN9 _L_(39)
2733 #define MUX_PB07B_ADC1_AIN9 _L_(1)
2734 #define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9)
2735 #define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7)
2736 #define PIN_PC00B_ADC1_AIN10 _L_(64)
2737 #define MUX_PC00B_ADC1_AIN10 _L_(1)
2738 #define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10)
2739 #define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0)
2740 #define PIN_PC01B_ADC1_AIN11 _L_(65)
2741 #define MUX_PC01B_ADC1_AIN11 _L_(1)
2742 #define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11)
2743 #define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1)
2744 #define PIN_PC30B_ADC1_AIN12 _L_(94)
2745 #define MUX_PC30B_ADC1_AIN12 _L_(1)
2746 #define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12)
2747 #define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30)
2748 #define PIN_PC31B_ADC1_AIN13 _L_(95)
2749 #define MUX_PC31B_ADC1_AIN13 _L_(1)
2750 #define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13)
2751 #define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31)
2752 #define PIN_PD00B_ADC1_AIN14 _L_(96)
2753 #define MUX_PD00B_ADC1_AIN14 _L_(1)
2754 #define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14)
2755 #define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0)
2756 #define PIN_PD01B_ADC1_AIN15 _L_(97)
2757 #define MUX_PD01B_ADC1_AIN15 _L_(1)
2758 #define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15)
2759 #define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1)
2761 #define PIN_PA02B_DAC_VOUT0 _L_(2)
2762 #define MUX_PA02B_DAC_VOUT0 _L_(1)
2763 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0)
2764 #define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2)
2765 #define PIN_PA05B_DAC_VOUT1 _L_(5)
2766 #define MUX_PA05B_DAC_VOUT1 _L_(1)
2767 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1)
2768 #define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5)
2770 #define PIN_PA09J_I2S_FS0 _L_(9)
2771 #define MUX_PA09J_I2S_FS0 _L_(9)
2772 #define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0)
2773 #define PORT_PA09J_I2S_FS0 (_UL_(1) << 9)
2774 #define PIN_PA20J_I2S_FS0 _L_(20)
2775 #define MUX_PA20J_I2S_FS0 _L_(9)
2776 #define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0)
2777 #define PORT_PA20J_I2S_FS0 (_UL_(1) << 20)
2778 #define PIN_PA23J_I2S_FS1 _L_(23)
2779 #define MUX_PA23J_I2S_FS1 _L_(9)
2780 #define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1)
2781 #define PORT_PA23J_I2S_FS1 (_UL_(1) << 23)
2782 #define PIN_PB11J_I2S_FS1 _L_(43)
2783 #define MUX_PB11J_I2S_FS1 _L_(9)
2784 #define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1)
2785 #define PORT_PB11J_I2S_FS1 (_UL_(1) << 11)
2786 #define PIN_PA08J_I2S_MCK0 _L_(8)
2787 #define MUX_PA08J_I2S_MCK0 _L_(9)
2788 #define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0)
2789 #define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8)
2790 #define PIN_PB17J_I2S_MCK0 _L_(49)
2791 #define MUX_PB17J_I2S_MCK0 _L_(9)
2792 #define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0)
2793 #define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17)
2794 #define PIN_PB29J_I2S_MCK1 _L_(61)
2795 #define MUX_PB29J_I2S_MCK1 _L_(9)
2796 #define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1)
2797 #define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29)
2798 #define PIN_PB13J_I2S_MCK1 _L_(45)
2799 #define MUX_PB13J_I2S_MCK1 _L_(9)
2800 #define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1)
2801 #define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13)
2802 #define PIN_PA10J_I2S_SCK0 _L_(10)
2803 #define MUX_PA10J_I2S_SCK0 _L_(9)
2804 #define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0)
2805 #define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10)
2806 #define PIN_PB16J_I2S_SCK0 _L_(48)
2807 #define MUX_PB16J_I2S_SCK0 _L_(9)
2808 #define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0)
2809 #define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16)
2810 #define PIN_PB28J_I2S_SCK1 _L_(60)
2811 #define MUX_PB28J_I2S_SCK1 _L_(9)
2812 #define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1)
2813 #define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28)
2814 #define PIN_PB12J_I2S_SCK1 _L_(44)
2815 #define MUX_PB12J_I2S_SCK1 _L_(9)
2816 #define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1)
2817 #define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12)
2818 #define PIN_PA22J_I2S_SDI _L_(22)
2819 #define MUX_PA22J_I2S_SDI _L_(9)
2820 #define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI)
2821 #define PORT_PA22J_I2S_SDI (_UL_(1) << 22)
2822 #define PIN_PB10J_I2S_SDI _L_(42)
2823 #define MUX_PB10J_I2S_SDI _L_(9)
2824 #define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI)
2825 #define PORT_PB10J_I2S_SDI (_UL_(1) << 10)
2826 #define PIN_PA11J_I2S_SDO _L_(11)
2827 #define MUX_PA11J_I2S_SDO _L_(9)
2828 #define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO)
2829 #define PORT_PA11J_I2S_SDO (_UL_(1) << 11)
2830 #define PIN_PA21J_I2S_SDO _L_(21)
2831 #define MUX_PA21J_I2S_SDO _L_(9)
2832 #define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO)
2833 #define PORT_PA21J_I2S_SDO (_UL_(1) << 21)
2835 #define PIN_PA14K_PCC_CLK _L_(14)
2836 #define MUX_PA14K_PCC_CLK _L_(10)
2837 #define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK)
2838 #define PORT_PA14K_PCC_CLK (_UL_(1) << 14)
2839 #define PIN_PA16K_PCC_DATA0 _L_(16)
2840 #define MUX_PA16K_PCC_DATA0 _L_(10)
2841 #define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0)
2842 #define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16)
2843 #define PIN_PA17K_PCC_DATA1 _L_(17)
2844 #define MUX_PA17K_PCC_DATA1 _L_(10)
2845 #define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1)
2846 #define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17)
2847 #define PIN_PA18K_PCC_DATA2 _L_(18)
2848 #define MUX_PA18K_PCC_DATA2 _L_(10)
2849 #define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2)
2850 #define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18)
2851 #define PIN_PA19K_PCC_DATA3 _L_(19)
2852 #define MUX_PA19K_PCC_DATA3 _L_(10)
2853 #define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3)
2854 #define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19)
2855 #define PIN_PA20K_PCC_DATA4 _L_(20)
2856 #define MUX_PA20K_PCC_DATA4 _L_(10)
2857 #define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4)
2858 #define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20)
2859 #define PIN_PA21K_PCC_DATA5 _L_(21)
2860 #define MUX_PA21K_PCC_DATA5 _L_(10)
2861 #define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5)
2862 #define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21)
2863 #define PIN_PA22K_PCC_DATA6 _L_(22)
2864 #define MUX_PA22K_PCC_DATA6 _L_(10)
2865 #define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6)
2866 #define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22)
2867 #define PIN_PA23K_PCC_DATA7 _L_(23)
2868 #define MUX_PA23K_PCC_DATA7 _L_(10)
2869 #define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7)
2870 #define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23)
2871 #define PIN_PB14K_PCC_DATA8 _L_(46)
2872 #define MUX_PB14K_PCC_DATA8 _L_(10)
2873 #define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8)
2874 #define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14)
2875 #define PIN_PB15K_PCC_DATA9 _L_(47)
2876 #define MUX_PB15K_PCC_DATA9 _L_(10)
2877 #define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9)
2878 #define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15)
2879 #define PIN_PC12K_PCC_DATA10 _L_(76)
2880 #define MUX_PC12K_PCC_DATA10 _L_(10)
2881 #define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10)
2882 #define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12)
2883 #define PIN_PC13K_PCC_DATA11 _L_(77)
2884 #define MUX_PC13K_PCC_DATA11 _L_(10)
2885 #define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11)
2886 #define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13)
2887 #define PIN_PC14K_PCC_DATA12 _L_(78)
2888 #define MUX_PC14K_PCC_DATA12 _L_(10)
2889 #define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12)
2890 #define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14)
2891 #define PIN_PC15K_PCC_DATA13 _L_(79)
2892 #define MUX_PC15K_PCC_DATA13 _L_(10)
2893 #define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13)
2894 #define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15)
2895 #define PIN_PA12K_PCC_DEN1 _L_(12)
2896 #define MUX_PA12K_PCC_DEN1 _L_(10)
2897 #define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1)
2898 #define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12)
2899 #define PIN_PA13K_PCC_DEN2 _L_(13)
2900 #define MUX_PA13K_PCC_DEN2 _L_(10)
2901 #define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2)
2902 #define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13)
2904 #define PIN_PA06I_SDHC0_SDCD _L_(6)
2905 #define MUX_PA06I_SDHC0_SDCD _L_(8)
2906 #define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD)
2907 #define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6)
2908 #define PIN_PA12I_SDHC0_SDCD _L_(12)
2909 #define MUX_PA12I_SDHC0_SDCD _L_(8)
2910 #define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD)
2911 #define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12)
2912 #define PIN_PB12I_SDHC0_SDCD _L_(44)
2913 #define MUX_PB12I_SDHC0_SDCD _L_(8)
2914 #define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD)
2915 #define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12)
2916 #define PIN_PC06I_SDHC0_SDCD _L_(70)
2917 #define MUX_PC06I_SDHC0_SDCD _L_(8)
2918 #define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD)
2919 #define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6)
2920 #define PIN_PB11I_SDHC0_SDCK _L_(43)
2921 #define MUX_PB11I_SDHC0_SDCK _L_(8)
2922 #define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK)
2923 #define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11)
2924 #define PIN_PA08I_SDHC0_SDCMD _L_(8)
2925 #define MUX_PA08I_SDHC0_SDCMD _L_(8)
2926 #define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD)
2927 #define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8)
2928 #define PIN_PA09I_SDHC0_SDDAT0 _L_(9)
2929 #define MUX_PA09I_SDHC0_SDDAT0 _L_(8)
2930 #define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0)
2931 #define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9)
2932 #define PIN_PA10I_SDHC0_SDDAT1 _L_(10)
2933 #define MUX_PA10I_SDHC0_SDDAT1 _L_(8)
2934 #define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1)
2935 #define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10)
2936 #define PIN_PA11I_SDHC0_SDDAT2 _L_(11)
2937 #define MUX_PA11I_SDHC0_SDDAT2 _L_(8)
2938 #define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2)
2939 #define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11)
2940 #define PIN_PB10I_SDHC0_SDDAT3 _L_(42)
2941 #define MUX_PB10I_SDHC0_SDDAT3 _L_(8)
2942 #define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3)
2943 #define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10)
2944 #define PIN_PA07I_SDHC0_SDWP _L_(7)
2945 #define MUX_PA07I_SDHC0_SDWP _L_(8)
2946 #define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP)
2947 #define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7)
2948 #define PIN_PA13I_SDHC0_SDWP _L_(13)
2949 #define MUX_PA13I_SDHC0_SDWP _L_(8)
2950 #define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP)
2951 #define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13)
2952 #define PIN_PB13I_SDHC0_SDWP _L_(45)
2953 #define MUX_PB13I_SDHC0_SDWP _L_(8)
2954 #define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP)
2955 #define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13)
2956 #define PIN_PC07I_SDHC0_SDWP _L_(71)
2957 #define MUX_PC07I_SDHC0_SDWP _L_(8)
2958 #define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP)
2959 #define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7)
2961 #define PIN_PB16I_SDHC1_SDCD _L_(48)
2962 #define MUX_PB16I_SDHC1_SDCD _L_(8)
2963 #define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD)
2964 #define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16)
2965 #define PIN_PC20I_SDHC1_SDCD _L_(84)
2966 #define MUX_PC20I_SDHC1_SDCD _L_(8)
2967 #define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD)
2968 #define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20)
2969 #define PIN_PD20I_SDHC1_SDCD _L_(116)
2970 #define MUX_PD20I_SDHC1_SDCD _L_(8)
2971 #define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD)
2972 #define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20)
2973 #define PIN_PA21I_SDHC1_SDCK _L_(21)
2974 #define MUX_PA21I_SDHC1_SDCK _L_(8)
2975 #define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK)
2976 #define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21)
2977 #define PIN_PA20I_SDHC1_SDCMD _L_(20)
2978 #define MUX_PA20I_SDHC1_SDCMD _L_(8)
2979 #define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD)
2980 #define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20)
2981 #define PIN_PB18I_SDHC1_SDDAT0 _L_(50)
2982 #define MUX_PB18I_SDHC1_SDDAT0 _L_(8)
2983 #define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0)
2984 #define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18)
2985 #define PIN_PB19I_SDHC1_SDDAT1 _L_(51)
2986 #define MUX_PB19I_SDHC1_SDDAT1 _L_(8)
2987 #define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1)
2988 #define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19)
2989 #define PIN_PB20I_SDHC1_SDDAT2 _L_(52)
2990 #define MUX_PB20I_SDHC1_SDDAT2 _L_(8)
2991 #define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2)
2992 #define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20)
2993 #define PIN_PB21I_SDHC1_SDDAT3 _L_(53)
2994 #define MUX_PB21I_SDHC1_SDDAT3 _L_(8)
2995 #define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3)
2996 #define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21)
2997 #define PIN_PB17I_SDHC1_SDWP _L_(49)
2998 #define MUX_PB17I_SDHC1_SDWP _L_(8)
2999 #define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP)
3000 #define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17)
3001 #define PIN_PC21I_SDHC1_SDWP _L_(85)
3002 #define MUX_PC21I_SDHC1_SDWP _L_(8)
3003 #define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP)
3004 #define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21)
3005 #define PIN_PD21I_SDHC1_SDWP _L_(117)
3006 #define MUX_PD21I_SDHC1_SDWP _L_(8)
3007 #define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP)
3008 #define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21)