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30 #ifndef _SAME54_I2S_INSTANCE_
31 #define _SAME54_I2S_INSTANCE_
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_I2S_CTRLA (0x43002800)
36 #define REG_I2S_CLKCTRL0 (0x43002804)
37 #define REG_I2S_CLKCTRL1 (0x43002808)
38 #define REG_I2S_INTENCLR (0x4300280C)
39 #define REG_I2S_INTENSET (0x43002810)
40 #define REG_I2S_INTFLAG (0x43002814)
41 #define REG_I2S_SYNCBUSY (0x43002818)
42 #define REG_I2S_TXCTRL (0x43002820)
43 #define REG_I2S_RXCTRL (0x43002824)
44 #define REG_I2S_TXDATA (0x43002830)
45 #define REG_I2S_RXDATA (0x43002834)
47 #define REG_I2S_CTRLA (*(RwReg8 *)0x43002800UL)
48 #define REG_I2S_CLKCTRL0 (*(RwReg *)0x43002804UL)
49 #define REG_I2S_CLKCTRL1 (*(RwReg *)0x43002808UL)
50 #define REG_I2S_INTENCLR (*(RwReg16*)0x4300280CUL)
51 #define REG_I2S_INTENSET (*(RwReg16*)0x43002810UL)
52 #define REG_I2S_INTFLAG (*(RwReg16*)0x43002814UL)
53 #define REG_I2S_SYNCBUSY (*(RoReg16*)0x43002818UL)
54 #define REG_I2S_TXCTRL (*(RwReg *)0x43002820UL)
55 #define REG_I2S_RXCTRL (*(RwReg *)0x43002824UL)
56 #define REG_I2S_TXDATA (*(WoReg *)0x43002830UL)
57 #define REG_I2S_RXDATA (*(RoReg *)0x43002834UL)
61 #define I2S_CLK_NUM 2 // Number of clock units
62 #define I2S_DMAC_ID_RX_0 76
63 #define I2S_DMAC_ID_RX_1 77
64 #define I2S_DMAC_ID_RX_LSB 76
65 #define I2S_DMAC_ID_RX_MSB 77
66 #define I2S_DMAC_ID_RX_SIZE 2
67 #define I2S_DMAC_ID_TX_0 78
68 #define I2S_DMAC_ID_TX_1 79
69 #define I2S_DMAC_ID_TX_LSB 78
70 #define I2S_DMAC_ID_TX_MSB 79
71 #define I2S_DMAC_ID_TX_SIZE 2
72 #define I2S_GCLK_ID_0 43
73 #define I2S_GCLK_ID_1 44
74 #define I2S_GCLK_ID_LSB 43
75 #define I2S_GCLK_ID_MSB 44
76 #define I2S_GCLK_ID_SIZE 2
77 #define I2S_MAX_SLOTS 8 // Max number of data slots in frame
78 #define I2S_MAX_WL_BITS 32 // Max number of bits in data samples
79 #define I2S_SER_NUM 2 // Number of serializers