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30 #ifndef _SAME54_CMCC_COMPONENT_
31 #define _SAME54_CMCC_COMPONENT_
40 #define REV_CMCC 0x600
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
60 #define CMCC_TYPE_OFFSET 0x00
61 #define CMCC_TYPE_RESETVALUE _U_(0x000012D2)
63 #define CMCC_TYPE_GCLK_Pos 1
64 #define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
65 #define CMCC_TYPE_RRP_Pos 4
66 #define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
67 #define CMCC_TYPE_WAYNUM_Pos 5
68 #define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
69 #define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
70 #define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0)
71 #define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1)
72 #define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2)
73 #define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
74 #define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
75 #define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
76 #define CMCC_TYPE_LCKDOWN_Pos 7
77 #define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
78 #define CMCC_TYPE_CSIZE_Pos 8
79 #define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
80 #define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
81 #define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0)
82 #define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1)
83 #define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2)
84 #define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3)
85 #define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4)
86 #define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5)
87 #define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6)
88 #define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
89 #define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
90 #define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
91 #define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
92 #define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
93 #define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
94 #define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
95 #define CMCC_TYPE_CLSIZE_Pos 11
96 #define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
97 #define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
98 #define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0)
99 #define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1)
100 #define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2)
101 #define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3)
102 #define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4)
103 #define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5)
104 #define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
105 #define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
106 #define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
107 #define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
108 #define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
109 #define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
110 #define CMCC_TYPE_MASK _U_(0x00003FF2)
113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
127 #define CMCC_CFG_OFFSET 0x04
128 #define CMCC_CFG_RESETVALUE _U_(0x00000020)
130 #define CMCC_CFG_ICDIS_Pos 1
131 #define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
132 #define CMCC_CFG_DCDIS_Pos 2
133 #define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
134 #define CMCC_CFG_CSIZESW_Pos 4
135 #define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
136 #define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
137 #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0)
138 #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1)
139 #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2)
140 #define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3)
141 #define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4)
142 #define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5)
143 #define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6)
144 #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
145 #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
146 #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
147 #define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
148 #define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
149 #define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
150 #define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
151 #define CMCC_CFG_MASK _U_(0x00000076)
154 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
164 #define CMCC_CTRL_OFFSET 0x08
165 #define CMCC_CTRL_RESETVALUE _U_(0x00000000)
167 #define CMCC_CTRL_CEN_Pos 0
168 #define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
169 #define CMCC_CTRL_MASK _U_(0x00000001)
172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
182 #define CMCC_SR_OFFSET 0x0C
183 #define CMCC_SR_RESETVALUE _U_(0x00000000)
185 #define CMCC_SR_CSTS_Pos 0
186 #define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
187 #define CMCC_SR_MASK _U_(0x00000001)
190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
200 #define CMCC_LCKWAY_OFFSET 0x10
201 #define CMCC_LCKWAY_RESETVALUE _U_(0x00000000)
203 #define CMCC_LCKWAY_LCKWAY_Pos 0
204 #define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
205 #define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
206 #define CMCC_LCKWAY_MASK _U_(0x0000000F)
209 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
219 #define CMCC_MAINT0_OFFSET 0x20
220 #define CMCC_MAINT0_RESETVALUE _U_(0x00000000)
222 #define CMCC_MAINT0_INVALL_Pos 0
223 #define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
224 #define CMCC_MAINT0_MASK _U_(0x00000001)
227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
239 #define CMCC_MAINT1_OFFSET 0x24
240 #define CMCC_MAINT1_RESETVALUE _U_(0x00000000)
242 #define CMCC_MAINT1_INDEX_Pos 4
243 #define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
244 #define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
245 #define CMCC_MAINT1_WAY_Pos 28
246 #define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
247 #define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
248 #define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0)
249 #define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1)
250 #define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2)
251 #define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3)
252 #define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
253 #define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
254 #define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
255 #define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
256 #define CMCC_MAINT1_MASK _U_(0xF0000FF0)
259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
269 #define CMCC_MCFG_OFFSET 0x28
270 #define CMCC_MCFG_RESETVALUE _U_(0x00000000)
272 #define CMCC_MCFG_MODE_Pos 0
273 #define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
274 #define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
275 #define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0)
276 #define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1)
277 #define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2)
278 #define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
279 #define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
280 #define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
281 #define CMCC_MCFG_MASK _U_(0x00000003)
284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
294 #define CMCC_MEN_OFFSET 0x2C
295 #define CMCC_MEN_RESETVALUE _U_(0x00000000)
297 #define CMCC_MEN_MENABLE_Pos 0
298 #define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
299 #define CMCC_MEN_MASK _U_(0x00000001)
302 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
312 #define CMCC_MCTRL_OFFSET 0x30
313 #define CMCC_MCTRL_RESETVALUE _U_(0x00000000)
315 #define CMCC_MCTRL_SWRST_Pos 0
316 #define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
317 #define CMCC_MCTRL_MASK _U_(0x00000001)
320 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
329 #define CMCC_MSR_OFFSET 0x34
330 #define CMCC_MSR_RESETVALUE _U_(0x00000000)
332 #define CMCC_MSR_EVENT_CNT_Pos 0
333 #define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
334 #define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
335 #define CMCC_MSR_MASK _U_(0xFFFFFFFF)
338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO CMCC_MCFG_Type MCFG
Offset: 0x28 (R/W 32) Cache Monitor Configuration Register.
__I CMCC_TYPE_Type TYPE
Offset: 0x00 (R/ 32) Cache Type Register.
__IO CMCC_CFG_Type CFG
Offset: 0x04 (R/W 32) Cache Configuration Register.
__O CMCC_MAINT0_Type MAINT0
Offset: 0x20 ( /W 32) Cache Maintenance Register 0.
__O CMCC_MAINT1_Type MAINT1
Offset: 0x24 ( /W 32) Cache Maintenance Register 1.
__O CMCC_CTRL_Type CTRL
Offset: 0x08 ( /W 32) Cache Control Register.
__I CMCC_MSR_Type MSR
Offset: 0x34 (R/ 32) Cache Monitor Status Register.
__O CMCC_MCTRL_Type MCTRL
Offset: 0x30 ( /W 32) Cache Monitor Control Register.
__I CMCC_SR_Type SR
Offset: 0x0C (R/ 32) Cache Status Register.
CMCC APB hardware registers.
__IO CMCC_LCKWAY_Type LCKWAY
Offset: 0x10 (R/W 32) Cache Lock per Way Register.
volatile const uint8_t RoReg8
__IO CMCC_MEN_Type MEN
Offset: 0x2C (R/W 32) Cache Monitor Enable Register.