SAME54P20A Test Project
Data Fields
TCC_INTENSET_Type Union Reference

Data Fields

struct {
   uint32_t   OVF:1
 
   uint32_t   TRG:1
 
   uint32_t   CNT:1
 
   uint32_t   ERR:1
 
   uint32_t   __pad0__:6
 
   uint32_t   UFS:1
 
   uint32_t   DFS:1
 
   uint32_t   FAULTA:1
 
   uint32_t   FAULTB:1
 
   uint32_t   FAULT0:1
 
   uint32_t   FAULT1:1
 
   uint32_t   MC0:1
 
   uint32_t   MC1:1
 
   uint32_t   MC2:1
 
   uint32_t   MC3:1
 
   uint32_t   MC4:1
 
   uint32_t   MC5:1
 
   uint32_t   __pad1__:10
 
bit
 
struct {
   uint32_t   __pad0__:16
 
   uint32_t   MC:6
 
   uint32_t   __pad1__:10
 
vec
 
uint32_t reg
 

Detailed Description

Definition at line 921 of file tcc.h.

Field Documentation

◆ __pad0__

uint32_t TCC_INTENSET_Type::__pad0__

bit: 4.. 9 Reserved

bit: 0..15 Reserved

Definition at line 927 of file tcc.h.

◆ __pad1__

uint32_t TCC_INTENSET_Type::__pad1__

bit: 22..31 Reserved

Definition at line 940 of file tcc.h.

◆ bit

struct { ... } TCC_INTENSET_Type::bit

Structure used for bit access

◆ CNT

uint32_t TCC_INTENSET_Type::CNT

bit: 2 Counter Interrupt Enable

Definition at line 925 of file tcc.h.

◆ DFS

uint32_t TCC_INTENSET_Type::DFS

bit: 11 Non-Recoverable Debug Fault Interrupt Enable

Definition at line 929 of file tcc.h.

◆ ERR

uint32_t TCC_INTENSET_Type::ERR

bit: 3 Error Interrupt Enable

Definition at line 926 of file tcc.h.

◆ FAULT0

uint32_t TCC_INTENSET_Type::FAULT0

bit: 14 Non-Recoverable Fault 0 Interrupt Enable

Definition at line 932 of file tcc.h.

◆ FAULT1

uint32_t TCC_INTENSET_Type::FAULT1

bit: 15 Non-Recoverable Fault 1 Interrupt Enable

Definition at line 933 of file tcc.h.

◆ FAULTA

uint32_t TCC_INTENSET_Type::FAULTA

bit: 12 Recoverable Fault A Interrupt Enable

Definition at line 930 of file tcc.h.

◆ FAULTB

uint32_t TCC_INTENSET_Type::FAULTB

bit: 13 Recoverable Fault B Interrupt Enable

Definition at line 931 of file tcc.h.

◆ MC

uint32_t TCC_INTENSET_Type::MC

bit: 16..21 Match or Capture Channel x Interrupt Enable

Definition at line 944 of file tcc.h.

◆ MC0

uint32_t TCC_INTENSET_Type::MC0

bit: 16 Match or Capture Channel 0 Interrupt Enable

Definition at line 934 of file tcc.h.

◆ MC1

uint32_t TCC_INTENSET_Type::MC1

bit: 17 Match or Capture Channel 1 Interrupt Enable

Definition at line 935 of file tcc.h.

◆ MC2

uint32_t TCC_INTENSET_Type::MC2

bit: 18 Match or Capture Channel 2 Interrupt Enable

Definition at line 936 of file tcc.h.

◆ MC3

uint32_t TCC_INTENSET_Type::MC3

bit: 19 Match or Capture Channel 3 Interrupt Enable

Definition at line 937 of file tcc.h.

◆ MC4

uint32_t TCC_INTENSET_Type::MC4

bit: 20 Match or Capture Channel 4 Interrupt Enable

Definition at line 938 of file tcc.h.

◆ MC5

uint32_t TCC_INTENSET_Type::MC5

bit: 21 Match or Capture Channel 5 Interrupt Enable

Definition at line 939 of file tcc.h.

◆ OVF

uint32_t TCC_INTENSET_Type::OVF

bit: 0 Overflow Interrupt Enable

Definition at line 923 of file tcc.h.

◆ reg

uint32_t TCC_INTENSET_Type::reg

Type used for register access

Definition at line 947 of file tcc.h.

◆ TRG

uint32_t TCC_INTENSET_Type::TRG

bit: 1 Retrigger Interrupt Enable

Definition at line 924 of file tcc.h.

◆ UFS

uint32_t TCC_INTENSET_Type::UFS

bit: 10 Non-Recoverable Update Fault Interrupt Enable

Definition at line 928 of file tcc.h.

◆ vec

struct { ... } TCC_INTENSET_Type::vec

Structure used for vec access


The documentation for this union was generated from the following file: