Definition at line 244 of file qspi.h.
◆ __pad0__
uint32_t QSPI_INTENSET_Type::__pad0__ |
bit: 4.. 7 Reserved
Definition at line 250 of file qspi.h.
◆ __pad1__
uint32_t QSPI_INTENSET_Type::__pad1__ |
bit: 9 Reserved
Definition at line 252 of file qspi.h.
◆ __pad2__
uint32_t QSPI_INTENSET_Type::__pad2__ |
bit: 11..31 Reserved
Definition at line 254 of file qspi.h.
◆ bit
struct { ... } QSPI_INTENSET_Type::bit |
Structure used for bit access
◆ CSRISE
uint32_t QSPI_INTENSET_Type::CSRISE |
bit: 8 Chip Select Rise Interrupt Enable
Definition at line 251 of file qspi.h.
◆ DRE
uint32_t QSPI_INTENSET_Type::DRE |
bit: 1 Transmit Data Register Empty Interrupt Enable
Definition at line 247 of file qspi.h.
◆ ERROR
uint32_t QSPI_INTENSET_Type::ERROR |
bit: 3 Overrun Error Interrupt Enable
Definition at line 249 of file qspi.h.
◆ INSTREND
uint32_t QSPI_INTENSET_Type::INSTREND |
bit: 10 Instruction End Interrupt Enable
Definition at line 253 of file qspi.h.
◆ reg
uint32_t QSPI_INTENSET_Type::reg |
Type used for register access
Definition at line 256 of file qspi.h.
◆ RXC
uint32_t QSPI_INTENSET_Type::RXC |
bit: 0 Receive Data Register Full Interrupt Enable
Definition at line 246 of file qspi.h.
◆ TXC
uint32_t QSPI_INTENSET_Type::TXC |
bit: 2 Transmission Complete Interrupt Enable
Definition at line 248 of file qspi.h.
The documentation for this union was generated from the following file:
- /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/qspi.h