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30 #ifndef _SAME54_EVSYS_COMPONENT_
31 #define _SAME54_EVSYS_COMPONENT_
40 #define REV_EVSYS 0x100
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
53 #define EVSYS_CTRLA_OFFSET 0x000
54 #define EVSYS_CTRLA_RESETVALUE _U_(0x00)
56 #define EVSYS_CTRLA_SWRST_Pos 0
57 #define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
58 #define EVSYS_CTRLA_MASK _U_(0x01)
61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
104 #define EVSYS_SWEVT_OFFSET 0x004
105 #define EVSYS_SWEVT_RESETVALUE _U_(0x00000000)
107 #define EVSYS_SWEVT_CHANNEL0_Pos 0
108 #define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
109 #define EVSYS_SWEVT_CHANNEL1_Pos 1
110 #define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
111 #define EVSYS_SWEVT_CHANNEL2_Pos 2
112 #define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
113 #define EVSYS_SWEVT_CHANNEL3_Pos 3
114 #define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
115 #define EVSYS_SWEVT_CHANNEL4_Pos 4
116 #define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
117 #define EVSYS_SWEVT_CHANNEL5_Pos 5
118 #define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
119 #define EVSYS_SWEVT_CHANNEL6_Pos 6
120 #define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
121 #define EVSYS_SWEVT_CHANNEL7_Pos 7
122 #define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
123 #define EVSYS_SWEVT_CHANNEL8_Pos 8
124 #define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
125 #define EVSYS_SWEVT_CHANNEL9_Pos 9
126 #define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
127 #define EVSYS_SWEVT_CHANNEL10_Pos 10
128 #define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
129 #define EVSYS_SWEVT_CHANNEL11_Pos 11
130 #define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
131 #define EVSYS_SWEVT_CHANNEL12_Pos 12
132 #define EVSYS_SWEVT_CHANNEL12 (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
133 #define EVSYS_SWEVT_CHANNEL13_Pos 13
134 #define EVSYS_SWEVT_CHANNEL13 (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
135 #define EVSYS_SWEVT_CHANNEL14_Pos 14
136 #define EVSYS_SWEVT_CHANNEL14 (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
137 #define EVSYS_SWEVT_CHANNEL15_Pos 15
138 #define EVSYS_SWEVT_CHANNEL15 (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
139 #define EVSYS_SWEVT_CHANNEL16_Pos 16
140 #define EVSYS_SWEVT_CHANNEL16 (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
141 #define EVSYS_SWEVT_CHANNEL17_Pos 17
142 #define EVSYS_SWEVT_CHANNEL17 (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
143 #define EVSYS_SWEVT_CHANNEL18_Pos 18
144 #define EVSYS_SWEVT_CHANNEL18 (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
145 #define EVSYS_SWEVT_CHANNEL19_Pos 19
146 #define EVSYS_SWEVT_CHANNEL19 (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
147 #define EVSYS_SWEVT_CHANNEL20_Pos 20
148 #define EVSYS_SWEVT_CHANNEL20 (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
149 #define EVSYS_SWEVT_CHANNEL21_Pos 21
150 #define EVSYS_SWEVT_CHANNEL21 (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
151 #define EVSYS_SWEVT_CHANNEL22_Pos 22
152 #define EVSYS_SWEVT_CHANNEL22 (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
153 #define EVSYS_SWEVT_CHANNEL23_Pos 23
154 #define EVSYS_SWEVT_CHANNEL23 (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
155 #define EVSYS_SWEVT_CHANNEL24_Pos 24
156 #define EVSYS_SWEVT_CHANNEL24 (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
157 #define EVSYS_SWEVT_CHANNEL25_Pos 25
158 #define EVSYS_SWEVT_CHANNEL25 (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
159 #define EVSYS_SWEVT_CHANNEL26_Pos 26
160 #define EVSYS_SWEVT_CHANNEL26 (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
161 #define EVSYS_SWEVT_CHANNEL27_Pos 27
162 #define EVSYS_SWEVT_CHANNEL27 (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
163 #define EVSYS_SWEVT_CHANNEL28_Pos 28
164 #define EVSYS_SWEVT_CHANNEL28 (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
165 #define EVSYS_SWEVT_CHANNEL29_Pos 29
166 #define EVSYS_SWEVT_CHANNEL29 (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
167 #define EVSYS_SWEVT_CHANNEL30_Pos 30
168 #define EVSYS_SWEVT_CHANNEL30 (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
169 #define EVSYS_SWEVT_CHANNEL31_Pos 31
170 #define EVSYS_SWEVT_CHANNEL31 (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
171 #define EVSYS_SWEVT_CHANNEL_Pos 0
172 #define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
173 #define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
174 #define EVSYS_SWEVT_MASK _U_(0xFFFFFFFF)
177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
188 #define EVSYS_PRICTRL_OFFSET 0x008
189 #define EVSYS_PRICTRL_RESETVALUE _U_(0x00)
191 #define EVSYS_PRICTRL_PRI_Pos 0
192 #define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
193 #define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
194 #define EVSYS_PRICTRL_RREN_Pos 7
195 #define EVSYS_PRICTRL_RREN (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
196 #define EVSYS_PRICTRL_MASK _U_(0x8F)
199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
214 #define EVSYS_INTPEND_OFFSET 0x010
215 #define EVSYS_INTPEND_RESETVALUE _U_(0x4000)
217 #define EVSYS_INTPEND_ID_Pos 0
218 #define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
219 #define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
220 #define EVSYS_INTPEND_OVR_Pos 8
221 #define EVSYS_INTPEND_OVR (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
222 #define EVSYS_INTPEND_EVD_Pos 9
223 #define EVSYS_INTPEND_EVD (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
224 #define EVSYS_INTPEND_READY_Pos 14
225 #define EVSYS_INTPEND_READY (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
226 #define EVSYS_INTPEND_BUSY_Pos 15
227 #define EVSYS_INTPEND_BUSY (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
228 #define EVSYS_INTPEND_MASK _U_(0xC30F)
231 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
256 #define EVSYS_INTSTATUS_OFFSET 0x014
257 #define EVSYS_INTSTATUS_RESETVALUE _U_(0x00000000)
259 #define EVSYS_INTSTATUS_CHINT0_Pos 0
260 #define EVSYS_INTSTATUS_CHINT0 (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
261 #define EVSYS_INTSTATUS_CHINT1_Pos 1
262 #define EVSYS_INTSTATUS_CHINT1 (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
263 #define EVSYS_INTSTATUS_CHINT2_Pos 2
264 #define EVSYS_INTSTATUS_CHINT2 (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
265 #define EVSYS_INTSTATUS_CHINT3_Pos 3
266 #define EVSYS_INTSTATUS_CHINT3 (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
267 #define EVSYS_INTSTATUS_CHINT4_Pos 4
268 #define EVSYS_INTSTATUS_CHINT4 (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
269 #define EVSYS_INTSTATUS_CHINT5_Pos 5
270 #define EVSYS_INTSTATUS_CHINT5 (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
271 #define EVSYS_INTSTATUS_CHINT6_Pos 6
272 #define EVSYS_INTSTATUS_CHINT6 (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
273 #define EVSYS_INTSTATUS_CHINT7_Pos 7
274 #define EVSYS_INTSTATUS_CHINT7 (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
275 #define EVSYS_INTSTATUS_CHINT8_Pos 8
276 #define EVSYS_INTSTATUS_CHINT8 (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
277 #define EVSYS_INTSTATUS_CHINT9_Pos 9
278 #define EVSYS_INTSTATUS_CHINT9 (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
279 #define EVSYS_INTSTATUS_CHINT10_Pos 10
280 #define EVSYS_INTSTATUS_CHINT10 (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
281 #define EVSYS_INTSTATUS_CHINT11_Pos 11
282 #define EVSYS_INTSTATUS_CHINT11 (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
283 #define EVSYS_INTSTATUS_CHINT_Pos 0
284 #define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
285 #define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
286 #define EVSYS_INTSTATUS_MASK _U_(0x00000FFF)
289 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
314 #define EVSYS_BUSYCH_OFFSET 0x018
315 #define EVSYS_BUSYCH_RESETVALUE _U_(0x00000000)
317 #define EVSYS_BUSYCH_BUSYCH0_Pos 0
318 #define EVSYS_BUSYCH_BUSYCH0 (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
319 #define EVSYS_BUSYCH_BUSYCH1_Pos 1
320 #define EVSYS_BUSYCH_BUSYCH1 (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
321 #define EVSYS_BUSYCH_BUSYCH2_Pos 2
322 #define EVSYS_BUSYCH_BUSYCH2 (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
323 #define EVSYS_BUSYCH_BUSYCH3_Pos 3
324 #define EVSYS_BUSYCH_BUSYCH3 (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
325 #define EVSYS_BUSYCH_BUSYCH4_Pos 4
326 #define EVSYS_BUSYCH_BUSYCH4 (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
327 #define EVSYS_BUSYCH_BUSYCH5_Pos 5
328 #define EVSYS_BUSYCH_BUSYCH5 (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
329 #define EVSYS_BUSYCH_BUSYCH6_Pos 6
330 #define EVSYS_BUSYCH_BUSYCH6 (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
331 #define EVSYS_BUSYCH_BUSYCH7_Pos 7
332 #define EVSYS_BUSYCH_BUSYCH7 (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
333 #define EVSYS_BUSYCH_BUSYCH8_Pos 8
334 #define EVSYS_BUSYCH_BUSYCH8 (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
335 #define EVSYS_BUSYCH_BUSYCH9_Pos 9
336 #define EVSYS_BUSYCH_BUSYCH9 (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
337 #define EVSYS_BUSYCH_BUSYCH10_Pos 10
338 #define EVSYS_BUSYCH_BUSYCH10 (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
339 #define EVSYS_BUSYCH_BUSYCH11_Pos 11
340 #define EVSYS_BUSYCH_BUSYCH11 (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
341 #define EVSYS_BUSYCH_BUSYCH_Pos 0
342 #define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
343 #define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
344 #define EVSYS_BUSYCH_MASK _U_(0x00000FFF)
347 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
372 #define EVSYS_READYUSR_OFFSET 0x01C
373 #define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF)
375 #define EVSYS_READYUSR_READYUSR0_Pos 0
376 #define EVSYS_READYUSR_READYUSR0 (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
377 #define EVSYS_READYUSR_READYUSR1_Pos 1
378 #define EVSYS_READYUSR_READYUSR1 (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
379 #define EVSYS_READYUSR_READYUSR2_Pos 2
380 #define EVSYS_READYUSR_READYUSR2 (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
381 #define EVSYS_READYUSR_READYUSR3_Pos 3
382 #define EVSYS_READYUSR_READYUSR3 (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
383 #define EVSYS_READYUSR_READYUSR4_Pos 4
384 #define EVSYS_READYUSR_READYUSR4 (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
385 #define EVSYS_READYUSR_READYUSR5_Pos 5
386 #define EVSYS_READYUSR_READYUSR5 (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
387 #define EVSYS_READYUSR_READYUSR6_Pos 6
388 #define EVSYS_READYUSR_READYUSR6 (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
389 #define EVSYS_READYUSR_READYUSR7_Pos 7
390 #define EVSYS_READYUSR_READYUSR7 (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
391 #define EVSYS_READYUSR_READYUSR8_Pos 8
392 #define EVSYS_READYUSR_READYUSR8 (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
393 #define EVSYS_READYUSR_READYUSR9_Pos 9
394 #define EVSYS_READYUSR_READYUSR9 (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
395 #define EVSYS_READYUSR_READYUSR10_Pos 10
396 #define EVSYS_READYUSR_READYUSR10 (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
397 #define EVSYS_READYUSR_READYUSR11_Pos 11
398 #define EVSYS_READYUSR_READYUSR11 (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
399 #define EVSYS_READYUSR_READYUSR_Pos 0
400 #define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
401 #define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
402 #define EVSYS_READYUSR_MASK _U_(0x00000FFF)
405 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
421 #define EVSYS_CHANNEL_OFFSET 0x020
422 #define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000)
424 #define EVSYS_CHANNEL_EVGEN_Pos 0
425 #define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
426 #define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
427 #define EVSYS_CHANNEL_PATH_Pos 8
428 #define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
429 #define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
430 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0)
431 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1)
432 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2)
433 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
434 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
435 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
436 #define EVSYS_CHANNEL_EDGSEL_Pos 10
437 #define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
438 #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
439 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0)
440 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1)
441 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2)
442 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3)
443 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
444 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
445 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
446 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
447 #define EVSYS_CHANNEL_RUNSTDBY_Pos 14
448 #define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
449 #define EVSYS_CHANNEL_ONDEMAND_Pos 15
450 #define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
451 #define EVSYS_CHANNEL_MASK _U_(0x0000CF7F)
454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
465 #define EVSYS_CHINTENCLR_OFFSET 0x024
466 #define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00)
468 #define EVSYS_CHINTENCLR_OVR_Pos 0
469 #define EVSYS_CHINTENCLR_OVR (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
470 #define EVSYS_CHINTENCLR_EVD_Pos 1
471 #define EVSYS_CHINTENCLR_EVD (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
472 #define EVSYS_CHINTENCLR_MASK _U_(0x03)
475 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
486 #define EVSYS_CHINTENSET_OFFSET 0x025
487 #define EVSYS_CHINTENSET_RESETVALUE _U_(0x00)
489 #define EVSYS_CHINTENSET_OVR_Pos 0
490 #define EVSYS_CHINTENSET_OVR (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
491 #define EVSYS_CHINTENSET_EVD_Pos 1
492 #define EVSYS_CHINTENSET_EVD (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
493 #define EVSYS_CHINTENSET_MASK _U_(0x03)
496 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
507 #define EVSYS_CHINTFLAG_OFFSET 0x026
508 #define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00)
510 #define EVSYS_CHINTFLAG_OVR_Pos 0
511 #define EVSYS_CHINTFLAG_OVR (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
512 #define EVSYS_CHINTFLAG_EVD_Pos 1
513 #define EVSYS_CHINTFLAG_EVD (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
514 #define EVSYS_CHINTFLAG_MASK _U_(0x03)
517 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
528 #define EVSYS_CHSTATUS_OFFSET 0x027
529 #define EVSYS_CHSTATUS_RESETVALUE _U_(0x01)
531 #define EVSYS_CHSTATUS_RDYUSR_Pos 0
532 #define EVSYS_CHSTATUS_RDYUSR (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
533 #define EVSYS_CHSTATUS_BUSYCH_Pos 1
534 #define EVSYS_CHSTATUS_BUSYCH (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
535 #define EVSYS_CHSTATUS_MASK _U_(0x03)
538 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
548 #define EVSYS_USER_OFFSET 0x120
549 #define EVSYS_USER_RESETVALUE _U_(0x00000000)
551 #define EVSYS_USER_CHANNEL_Pos 0
552 #define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
553 #define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
554 #define EVSYS_USER_MASK _U_(0x0000003F)
557 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
568 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO EVSYS_CHINTENCLR_Type CHINTENCLR
Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear.
__I EVSYS_CHSTATUS_Type CHSTATUS
Offset: 0x007 (R/ 8) Channel n Status.
__I EVSYS_BUSYCH_Type BUSYCH
Offset: 0x018 (R/ 32) Busy Channels.
__IO EVSYS_CTRLA_Type CTRLA
Offset: 0x000 (R/W 8) Control.
EvsysChannel hardware registers.
__I EVSYS_READYUSR_Type READYUSR
Offset: 0x01C (R/ 32) Ready Users.
__IO EVSYS_INTPEND_Type INTPEND
Offset: 0x010 (R/W 16) Channel Pending Interrupt.
__IO EVSYS_CHINTENSET_Type CHINTENSET
Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set.
__IO EVSYS_CHINTFLAG_Type CHINTFLAG
Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear.
__I EVSYS_INTSTATUS_Type INTSTATUS
Offset: 0x014 (R/ 32) Interrupt Status.
EVSYS hardware registers.
volatile const uint8_t RoReg8
__O EVSYS_SWEVT_Type SWEVT
Offset: 0x004 ( /W 32) Software Event.
__IO EVSYS_CHANNEL_Type CHANNEL
Offset: 0x000 (R/W 32) Channel n Control.
__IO EVSYS_PRICTRL_Type PRICTRL
Offset: 0x008 (R/W 8) Priority Control.