SAME54P20A Test Project
aes.h
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1 
30 #ifndef _SAME54_AES_COMPONENT_
31 #define _SAME54_AES_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define AES_U2238
40 #define REV_AES 0x220
41 
42 /* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t SWRST:1;
47  uint32_t ENABLE:1;
48  uint32_t AESMODE:3;
49  uint32_t CFBS:3;
50  uint32_t KEYSIZE:2;
51  uint32_t CIPHER:1;
52  uint32_t STARTMODE:1;
53  uint32_t LOD:1;
54  uint32_t KEYGEN:1;
55  uint32_t XORKEY:1;
56  uint32_t :1;
57  uint32_t CTYPE:4;
58  uint32_t :12;
59  } bit;
60  uint32_t reg;
62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
63 
64 #define AES_CTRLA_OFFSET 0x00
65 #define AES_CTRLA_RESETVALUE _U_(0x00000000)
67 #define AES_CTRLA_SWRST_Pos 0
68 #define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
69 #define AES_CTRLA_ENABLE_Pos 1
70 #define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
71 #define AES_CTRLA_AESMODE_Pos 2
72 #define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
73 #define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
74 #define AES_CTRLA_AESMODE_ECB_Val _U_(0x0)
75 #define AES_CTRLA_AESMODE_CBC_Val _U_(0x1)
76 #define AES_CTRLA_AESMODE_OFB_Val _U_(0x2)
77 #define AES_CTRLA_AESMODE_CFB_Val _U_(0x3)
78 #define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4)
79 #define AES_CTRLA_AESMODE_CCM_Val _U_(0x5)
80 #define AES_CTRLA_AESMODE_GCM_Val _U_(0x6)
81 #define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
82 #define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
83 #define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
84 #define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
85 #define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
86 #define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
87 #define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
88 #define AES_CTRLA_CFBS_Pos 5
89 #define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
90 #define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
91 #define AES_CTRLA_CFBS_128BIT_Val _U_(0x0)
92 #define AES_CTRLA_CFBS_64BIT_Val _U_(0x1)
93 #define AES_CTRLA_CFBS_32BIT_Val _U_(0x2)
94 #define AES_CTRLA_CFBS_16BIT_Val _U_(0x3)
95 #define AES_CTRLA_CFBS_8BIT_Val _U_(0x4)
96 #define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
97 #define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
98 #define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
99 #define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
100 #define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
101 #define AES_CTRLA_KEYSIZE_Pos 8
102 #define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
103 #define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
104 #define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0)
105 #define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1)
106 #define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2)
107 #define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
108 #define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
109 #define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
110 #define AES_CTRLA_CIPHER_Pos 10
111 #define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
112 #define AES_CTRLA_CIPHER_DEC_Val _U_(0x0)
113 #define AES_CTRLA_CIPHER_ENC_Val _U_(0x1)
114 #define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
115 #define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
116 #define AES_CTRLA_STARTMODE_Pos 11
117 #define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
118 #define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0)
119 #define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1)
120 #define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
121 #define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
122 #define AES_CTRLA_LOD_Pos 12
123 #define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
124 #define AES_CTRLA_LOD_NONE_Val _U_(0x0)
125 #define AES_CTRLA_LOD_LAST_Val _U_(0x1)
126 #define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
127 #define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
128 #define AES_CTRLA_KEYGEN_Pos 13
129 #define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
130 #define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0)
131 #define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1)
132 #define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
133 #define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
134 #define AES_CTRLA_XORKEY_Pos 14
135 #define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
136 #define AES_CTRLA_XORKEY_NONE_Val _U_(0x0)
137 #define AES_CTRLA_XORKEY_XOR_Val _U_(0x1)
138 #define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
139 #define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
140 #define AES_CTRLA_CTYPE_Pos 16
141 #define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
142 #define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
143 #define AES_CTRLA_MASK _U_(0x000F7FFF)
145 /* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
146 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
147 typedef union {
148  struct {
149  uint8_t START:1;
150  uint8_t NEWMSG:1;
151  uint8_t EOM:1;
152  uint8_t GFMUL:1;
153  uint8_t :4;
154  } bit;
155  uint8_t reg;
157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
158 
159 #define AES_CTRLB_OFFSET 0x04
160 #define AES_CTRLB_RESETVALUE _U_(0x00)
162 #define AES_CTRLB_START_Pos 0
163 #define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
164 #define AES_CTRLB_NEWMSG_Pos 1
165 #define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
166 #define AES_CTRLB_EOM_Pos 2
167 #define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
168 #define AES_CTRLB_GFMUL_Pos 3
169 #define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
170 #define AES_CTRLB_MASK _U_(0x0F)
172 /* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
173 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
174 typedef union {
175  struct {
176  uint8_t ENCCMP:1;
177  uint8_t GFMCMP:1;
178  uint8_t :6;
179  } bit;
180  uint8_t reg;
182 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
183 
184 #define AES_INTENCLR_OFFSET 0x05
185 #define AES_INTENCLR_RESETVALUE _U_(0x00)
187 #define AES_INTENCLR_ENCCMP_Pos 0
188 #define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
189 #define AES_INTENCLR_GFMCMP_Pos 1
190 #define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
191 #define AES_INTENCLR_MASK _U_(0x03)
193 /* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
195 typedef union {
196  struct {
197  uint8_t ENCCMP:1;
198  uint8_t GFMCMP:1;
199  uint8_t :6;
200  } bit;
201  uint8_t reg;
203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
204 
205 #define AES_INTENSET_OFFSET 0x06
206 #define AES_INTENSET_RESETVALUE _U_(0x00)
208 #define AES_INTENSET_ENCCMP_Pos 0
209 #define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
210 #define AES_INTENSET_GFMCMP_Pos 1
211 #define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
212 #define AES_INTENSET_MASK _U_(0x03)
214 /* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
216 typedef union { // __I to avoid read-modify-write on write-to-clear register
217  struct {
218  __I uint8_t ENCCMP:1;
219  __I uint8_t GFMCMP:1;
220  __I uint8_t :6;
221  } bit;
222  uint8_t reg;
224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
225 
226 #define AES_INTFLAG_OFFSET 0x07
227 #define AES_INTFLAG_RESETVALUE _U_(0x00)
229 #define AES_INTFLAG_ENCCMP_Pos 0
230 #define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
231 #define AES_INTFLAG_GFMCMP_Pos 1
232 #define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
233 #define AES_INTFLAG_MASK _U_(0x03)
235 /* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
236 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
237 typedef union {
238  struct {
239  uint8_t INDATAPTR:2;
240  uint8_t :6;
241  } bit;
242  uint8_t reg;
244 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
245 
246 #define AES_DATABUFPTR_OFFSET 0x08
247 #define AES_DATABUFPTR_RESETVALUE _U_(0x00)
249 #define AES_DATABUFPTR_INDATAPTR_Pos 0
250 #define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
251 #define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
252 #define AES_DATABUFPTR_MASK _U_(0x03)
254 /* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
256 typedef union {
257  struct {
258  uint8_t DBGRUN:1;
259  uint8_t :7;
260  } bit;
261  uint8_t reg;
263 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
264 
265 #define AES_DBGCTRL_OFFSET 0x09
266 #define AES_DBGCTRL_RESETVALUE _U_(0x00)
268 #define AES_DBGCTRL_DBGRUN_Pos 0
269 #define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
270 #define AES_DBGCTRL_MASK _U_(0x01)
272 /* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
274 typedef union {
275  uint32_t reg;
277 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
278 
279 #define AES_KEYWORD_OFFSET 0x0C
280 #define AES_KEYWORD_RESETVALUE _U_(0x00000000)
281 #define AES_KEYWORD_MASK _U_(0xFFFFFFFF)
283 /* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
285 typedef union {
286  uint32_t reg;
288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
289 
290 #define AES_INDATA_OFFSET 0x38
291 #define AES_INDATA_RESETVALUE _U_(0x00000000)
292 #define AES_INDATA_MASK _U_(0xFFFFFFFF)
294 /* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
296 typedef union {
297  uint32_t reg;
299 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
300 
301 #define AES_INTVECTV_OFFSET 0x3C
302 #define AES_INTVECTV_RESETVALUE _U_(0x00000000)
303 #define AES_INTVECTV_MASK _U_(0xFFFFFFFF)
305 /* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
307 typedef union {
308  uint32_t reg;
310 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
311 
312 #define AES_HASHKEY_OFFSET 0x5C
313 #define AES_HASHKEY_RESETVALUE _U_(0x00000000)
314 #define AES_HASHKEY_MASK _U_(0xFFFFFFFF)
316 /* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
318 typedef union {
319  uint32_t reg;
321 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
322 
323 #define AES_GHASH_OFFSET 0x6C
324 #define AES_GHASH_RESETVALUE _U_(0x00000000)
325 #define AES_GHASH_MASK _U_(0xFFFFFFFF)
327 /* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
328 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
329 typedef union {
330  uint32_t reg;
332 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
333 
334 #define AES_CIPLEN_OFFSET 0x80
335 #define AES_CIPLEN_RESETVALUE _U_(0x00000000)
336 #define AES_CIPLEN_MASK _U_(0xFFFFFFFF)
338 /* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
339 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
340 typedef union {
341  uint32_t reg;
343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
344 
345 #define AES_RANDSEED_OFFSET 0x84
346 #define AES_RANDSEED_RESETVALUE _U_(0x00000000)
347 #define AES_RANDSEED_MASK _U_(0xFFFFFFFF)
350 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
351 typedef struct {
359  RoReg8 Reserved1[0x2];
360  __O AES_KEYWORD_Type KEYWORD[8];
361  RoReg8 Reserved2[0xC];
363  __O AES_INTVECTV_Type INTVECTV[4];
364  RoReg8 Reserved3[0x10];
365  __IO AES_HASHKEY_Type HASHKEY[4];
366  __IO AES_GHASH_Type GHASH[4];
367  RoReg8 Reserved4[0x4];
370 } Aes;
371 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
372 
375 #endif /* _SAME54_AES_COMPONENT_ */
AES_INTENSET_Type::ENCCMP
uint8_t ENCCMP
Definition: aes.h:197
AES_DATABUFPTR_Type
Definition: aes.h:237
AES_INTENCLR_Type
Definition: aes.h:174
AES_CTRLA_Type::KEYGEN
uint32_t KEYGEN
Definition: aes.h:54
AES_CTRLA_Type::KEYSIZE
uint32_t KEYSIZE
Definition: aes.h:50
AES_KEYWORD_Type::reg
uint32_t reg
Definition: aes.h:275
AES_INTVECTV_Type
Definition: aes.h:296
AES_DATABUFPTR_Type::reg
uint8_t reg
Definition: aes.h:242
AES_INTFLAG_Type::reg
uint8_t reg
Definition: aes.h:222
Aes::RANDSEED
__IO AES_RANDSEED_Type RANDSEED
Offset: 0x84 (R/W 32) Random Seed.
Definition: aes.h:369
AES_DBGCTRL_Type
Definition: aes.h:256
AES_HASHKEY_Type
Definition: aes.h:307
AES_INTFLAG_Type
Definition: aes.h:216
Aes::INTFLAG
__IO AES_INTFLAG_Type INTFLAG
Offset: 0x07 (R/W 8) Interrupt Flag Status.
Definition: aes.h:356
AES_CTRLA_Type::reg
uint32_t reg
Definition: aes.h:60
AES_CTRLB_Type::NEWMSG
uint8_t NEWMSG
Definition: aes.h:150
AES_INTENCLR_Type::ENCCMP
uint8_t ENCCMP
Definition: aes.h:176
AES_CTRLB_Type::EOM
uint8_t EOM
Definition: aes.h:151
AES_HASHKEY_Type::reg
uint32_t reg
Definition: aes.h:308
AES_DATABUFPTR_Type::INDATAPTR
uint8_t INDATAPTR
Definition: aes.h:239
AES_INDATA_Type
Definition: aes.h:285
AES_CTRLA_Type::AESMODE
uint32_t AESMODE
Definition: aes.h:48
Aes::CTRLB
__IO AES_CTRLB_Type CTRLB
Offset: 0x04 (R/W 8) Control B.
Definition: aes.h:353
AES_CTRLB_Type::reg
uint8_t reg
Definition: aes.h:155
AES_INTFLAG_Type::GFMCMP
__I uint8_t GFMCMP
Definition: aes.h:219
AES_CTRLA_Type::LOD
uint32_t LOD
Definition: aes.h:53
Aes::CTRLA
__IO AES_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
Definition: aes.h:352
AES_CTRLA_Type::STARTMODE
uint32_t STARTMODE
Definition: aes.h:52
Aes::INTENCLR
__IO AES_INTENCLR_Type INTENCLR
Offset: 0x05 (R/W 8) Interrupt Enable Clear.
Definition: aes.h:354
AES_INTFLAG_Type::ENCCMP
__I uint8_t ENCCMP
Definition: aes.h:218
Aes::CIPLEN
__IO AES_CIPLEN_Type CIPLEN
Offset: 0x80 (R/W 32) Cipher Length.
Definition: aes.h:368
AES_INTVECTV_Type::reg
uint32_t reg
Definition: aes.h:297
AES_KEYWORD_Type
Definition: aes.h:274
AES_INTENSET_Type::GFMCMP
uint8_t GFMCMP
Definition: aes.h:198
AES_CIPLEN_Type
Definition: aes.h:329
AES_INDATA_Type::reg
uint32_t reg
Definition: aes.h:286
AES_INTENCLR_Type::reg
uint8_t reg
Definition: aes.h:180
AES_CTRLA_Type::CTYPE
uint32_t CTYPE
Definition: aes.h:57
AES_CTRLA_Type::CFBS
uint32_t CFBS
Definition: aes.h:49
Aes::DATABUFPTR
__IO AES_DATABUFPTR_Type DATABUFPTR
Offset: 0x08 (R/W 8) Data buffer pointer.
Definition: aes.h:357
Aes
AES hardware registers.
Definition: aes.h:351
AES_INTENSET_Type::reg
uint8_t reg
Definition: aes.h:201
AES_RANDSEED_Type
Definition: aes.h:340
AES_INTENSET_Type
Definition: aes.h:195
AES_RANDSEED_Type::reg
uint32_t reg
Definition: aes.h:341
AES_GHASH_Type::reg
uint32_t reg
Definition: aes.h:319
AES_CTRLA_Type
Definition: aes.h:44
AES_DBGCTRL_Type::DBGRUN
uint8_t DBGRUN
Definition: aes.h:258
AES_CTRLA_Type::CIPHER
uint32_t CIPHER
Definition: aes.h:51
AES_DBGCTRL_Type::reg
uint8_t reg
Definition: aes.h:261
AES_INTFLAG_Type::uint8_t
__I uint8_t
Definition: aes.h:220
AES_CTRLB_Type
Definition: aes.h:147
AES_CTRLB_Type::START
uint8_t START
Definition: aes.h:149
Aes::INTENSET
__IO AES_INTENSET_Type INTENSET
Offset: 0x06 (R/W 8) Interrupt Enable Set.
Definition: aes.h:355
AES_CTRLB_Type::GFMUL
uint8_t GFMUL
Definition: aes.h:152
Aes::INDATA
__IO AES_INDATA_Type INDATA
Offset: 0x38 (R/W 32) Indata.
Definition: aes.h:362
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
AES_INTENCLR_Type::GFMCMP
uint8_t GFMCMP
Definition: aes.h:177
AES_CTRLA_Type::XORKEY
uint32_t XORKEY
Definition: aes.h:55
AES_CTRLA_Type::ENABLE
uint32_t ENABLE
Definition: aes.h:47
AES_GHASH_Type
Definition: aes.h:318
AES_CIPLEN_Type::reg
uint32_t reg
Definition: aes.h:330
AES_CTRLA_Type::SWRST
uint32_t SWRST
Definition: aes.h:46
Aes::DBGCTRL
__IO AES_DBGCTRL_Type DBGCTRL
Offset: 0x09 (R/W 8) Debug control.
Definition: aes.h:358