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30 #ifndef _SAME54_QSPI_COMPONENT_
31 #define _SAME54_QSPI_COMPONENT_
40 #define REV_QSPI 0x163
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
56 #define QSPI_CTRLA_OFFSET 0x00
57 #define QSPI_CTRLA_RESETVALUE _U_(0x00000000)
59 #define QSPI_CTRLA_SWRST_Pos 0
60 #define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
61 #define QSPI_CTRLA_ENABLE_Pos 1
62 #define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
63 #define QSPI_CTRLA_LASTXFER_Pos 24
64 #define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
65 #define QSPI_CTRLA_MASK _U_(0x01000003)
68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
86 #define QSPI_CTRLB_OFFSET 0x04
87 #define QSPI_CTRLB_RESETVALUE _U_(0x00000000)
89 #define QSPI_CTRLB_MODE_Pos 0
90 #define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
91 #define QSPI_CTRLB_MODE_SPI_Val _U_(0x0)
92 #define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1)
93 #define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
94 #define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
95 #define QSPI_CTRLB_LOOPEN_Pos 1
96 #define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
97 #define QSPI_CTRLB_WDRBT_Pos 2
98 #define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
99 #define QSPI_CTRLB_SMEMREG_Pos 3
100 #define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
101 #define QSPI_CTRLB_CSMODE_Pos 4
102 #define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
103 #define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
104 #define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0)
105 #define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1)
106 #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2)
107 #define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
108 #define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
109 #define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
110 #define QSPI_CTRLB_DATALEN_Pos 8
111 #define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
112 #define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
113 #define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0)
114 #define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1)
115 #define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2)
116 #define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3)
117 #define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4)
118 #define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5)
119 #define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6)
120 #define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7)
121 #define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8)
122 #define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
123 #define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
124 #define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
125 #define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
126 #define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
127 #define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
128 #define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
129 #define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
130 #define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
131 #define QSPI_CTRLB_DLYBCT_Pos 16
132 #define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
133 #define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
134 #define QSPI_CTRLB_DLYCS_Pos 24
135 #define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
136 #define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
137 #define QSPI_CTRLB_MASK _U_(0xFFFF0F3F)
140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
154 #define QSPI_BAUD_OFFSET 0x08
155 #define QSPI_BAUD_RESETVALUE _U_(0x00000000)
157 #define QSPI_BAUD_CPOL_Pos 0
158 #define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
159 #define QSPI_BAUD_CPHA_Pos 1
160 #define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
161 #define QSPI_BAUD_BAUD_Pos 8
162 #define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
163 #define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
164 #define QSPI_BAUD_DLYBS_Pos 16
165 #define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
166 #define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
167 #define QSPI_BAUD_MASK _U_(0x00FFFF03)
170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
180 #define QSPI_RXDATA_OFFSET 0x0C
181 #define QSPI_RXDATA_RESETVALUE _U_(0x00000000)
183 #define QSPI_RXDATA_DATA_Pos 0
184 #define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
185 #define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
186 #define QSPI_RXDATA_MASK _U_(0x0000FFFF)
189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
199 #define QSPI_TXDATA_OFFSET 0x10
200 #define QSPI_TXDATA_RESETVALUE _U_(0x00000000)
202 #define QSPI_TXDATA_DATA_Pos 0
203 #define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
204 #define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
205 #define QSPI_TXDATA_MASK _U_(0x0000FFFF)
208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
225 #define QSPI_INTENCLR_OFFSET 0x14
226 #define QSPI_INTENCLR_RESETVALUE _U_(0x00000000)
228 #define QSPI_INTENCLR_RXC_Pos 0
229 #define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
230 #define QSPI_INTENCLR_DRE_Pos 1
231 #define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
232 #define QSPI_INTENCLR_TXC_Pos 2
233 #define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
234 #define QSPI_INTENCLR_ERROR_Pos 3
235 #define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
236 #define QSPI_INTENCLR_CSRISE_Pos 8
237 #define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
238 #define QSPI_INTENCLR_INSTREND_Pos 10
239 #define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
240 #define QSPI_INTENCLR_MASK _U_(0x0000050F)
243 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
260 #define QSPI_INTENSET_OFFSET 0x18
261 #define QSPI_INTENSET_RESETVALUE _U_(0x00000000)
263 #define QSPI_INTENSET_RXC_Pos 0
264 #define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
265 #define QSPI_INTENSET_DRE_Pos 1
266 #define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
267 #define QSPI_INTENSET_TXC_Pos 2
268 #define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
269 #define QSPI_INTENSET_ERROR_Pos 3
270 #define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
271 #define QSPI_INTENSET_CSRISE_Pos 8
272 #define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
273 #define QSPI_INTENSET_INSTREND_Pos 10
274 #define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
275 #define QSPI_INTENSET_MASK _U_(0x0000050F)
278 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
295 #define QSPI_INTFLAG_OFFSET 0x1C
296 #define QSPI_INTFLAG_RESETVALUE _U_(0x00000000)
298 #define QSPI_INTFLAG_RXC_Pos 0
299 #define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
300 #define QSPI_INTFLAG_DRE_Pos 1
301 #define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
302 #define QSPI_INTFLAG_TXC_Pos 2
303 #define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
304 #define QSPI_INTFLAG_ERROR_Pos 3
305 #define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
306 #define QSPI_INTFLAG_CSRISE_Pos 8
307 #define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
308 #define QSPI_INTFLAG_INSTREND_Pos 10
309 #define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
310 #define QSPI_INTFLAG_MASK _U_(0x0000050F)
313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
326 #define QSPI_STATUS_OFFSET 0x20
327 #define QSPI_STATUS_RESETVALUE _U_(0x00000200)
329 #define QSPI_STATUS_ENABLE_Pos 1
330 #define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
331 #define QSPI_STATUS_CSSTATUS_Pos 9
332 #define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
333 #define QSPI_STATUS_MASK _U_(0x00000202)
336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
345 #define QSPI_INSTRADDR_OFFSET 0x30
346 #define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000)
348 #define QSPI_INSTRADDR_ADDR_Pos 0
349 #define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
350 #define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
351 #define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF)
354 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
366 #define QSPI_INSTRCTRL_OFFSET 0x34
367 #define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000)
369 #define QSPI_INSTRCTRL_INSTR_Pos 0
370 #define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
371 #define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
372 #define QSPI_INSTRCTRL_OPTCODE_Pos 16
373 #define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
374 #define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
375 #define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF)
378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
400 #define QSPI_INSTRFRAME_OFFSET 0x38
401 #define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000)
403 #define QSPI_INSTRFRAME_WIDTH_Pos 0
404 #define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
405 #define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
406 #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0)
407 #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1)
408 #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2)
409 #define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3)
410 #define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4)
411 #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5)
412 #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6)
413 #define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
414 #define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
415 #define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
416 #define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
417 #define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
418 #define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
419 #define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
420 #define QSPI_INSTRFRAME_INSTREN_Pos 4
421 #define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
422 #define QSPI_INSTRFRAME_ADDREN_Pos 5
423 #define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
424 #define QSPI_INSTRFRAME_OPTCODEEN_Pos 6
425 #define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
426 #define QSPI_INSTRFRAME_DATAEN_Pos 7
427 #define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
428 #define QSPI_INSTRFRAME_OPTCODELEN_Pos 8
429 #define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
430 #define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
431 #define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0)
432 #define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1)
433 #define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2)
434 #define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3)
435 #define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
436 #define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
437 #define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
438 #define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
439 #define QSPI_INSTRFRAME_ADDRLEN_Pos 10
440 #define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
441 #define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0)
442 #define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1)
443 #define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
444 #define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
445 #define QSPI_INSTRFRAME_TFRTYPE_Pos 12
446 #define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
447 #define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
448 #define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0)
449 #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1)
450 #define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2)
451 #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3)
452 #define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
453 #define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
454 #define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
455 #define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
456 #define QSPI_INSTRFRAME_CRMODE_Pos 14
457 #define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
458 #define QSPI_INSTRFRAME_DDREN_Pos 15
459 #define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
460 #define QSPI_INSTRFRAME_DUMMYLEN_Pos 16
461 #define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
462 #define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
463 #define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7)
466 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
477 #define QSPI_SCRAMBCTRL_OFFSET 0x40
478 #define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000)
480 #define QSPI_SCRAMBCTRL_ENABLE_Pos 0
481 #define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
482 #define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1
483 #define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
484 #define QSPI_SCRAMBCTRL_MASK _U_(0x00000003)
487 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
496 #define QSPI_SCRAMBKEY_OFFSET 0x44
497 #define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000)
499 #define QSPI_SCRAMBKEY_KEY_Pos 0
500 #define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
501 #define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
502 #define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF)
505 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO QSPI_INTENSET_Type INTENSET
Offset: 0x18 (R/W 32) Interrupt Enable Set.
__IO QSPI_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
__IO QSPI_INSTRFRAME_Type INSTRFRAME
Offset: 0x38 (R/W 32) Instruction Frame.
__IO QSPI_INTENCLR_Type INTENCLR
Offset: 0x14 (R/W 32) Interrupt Enable Clear.
__I QSPI_RXDATA_Type RXDATA
Offset: 0x0C (R/ 32) Receive Data.
__IO QSPI_INSTRADDR_Type INSTRADDR
Offset: 0x30 (R/W 32) Instruction Address.
__O QSPI_TXDATA_Type TXDATA
Offset: 0x10 ( /W 32) Transmit Data.
__IO QSPI_BAUD_Type BAUD
Offset: 0x08 (R/W 32) Baud Rate.
__IO QSPI_INSTRCTRL_Type INSTRCTRL
Offset: 0x34 (R/W 32) Instruction Code.
__IO QSPI_CTRLB_Type CTRLB
Offset: 0x04 (R/W 32) Control B.
__O QSPI_SCRAMBKEY_Type SCRAMBKEY
Offset: 0x44 ( /W 32) Scrambling Key.
__IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL
Offset: 0x40 (R/W 32) Scrambling Mode.
__I QSPI_STATUS_Type STATUS
Offset: 0x20 (R/ 32) Status Register.
QSPI APB hardware registers.
volatile const uint8_t RoReg8
__IO QSPI_INTFLAG_Type INTFLAG
Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear.