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10 #ifndef _CONF_CLOCKS_H_
11 #define _CONF_CLOCKS_H_
18 #define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5
31 #define CONF_CORE_MCLK_CPUDIV 0x1
38 #define CONF_CORE_DMA_ENABLE (0)
45 #define CONF_CORE_CMCC_ENABLE (0)
47 #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
48 #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
49 #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
51 #define CONF_CORE_CLK_XOSC0_ENABLE (1)
52 #define CONF_CORE_CLK_XOSC0_XTALEN (1)
53 #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
54 #define CONF_CORE_CLK_XOSC0_ONDEMAND (0)
55 #define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)
56 #define CONF_CORE_CLK_XOSC0_ENALC (1)
57 #define CONF_CORE_CLK_XOSC0_CFDEN (1)
58 #define CONF_CORE_CLK_XOSC0_SWBEN (0)
59 #define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
60 #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
63 #define CONF_CORE_CLK_XOSC1_ENABLE (0)
64 #define CONF_CORE_CLK_XOSC1_XTALEN (0)
65 #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
66 #define CONF_CORE_CLK_XOSC1_ONDEMAND (0)
67 #define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)
68 #define CONF_CORE_CLK_XOSC1_ENALC (0)
69 #define CONF_CORE_CLK_XOSC1_CFDEN (0)
70 #define CONF_CORE_CLK_XOSC1_SWBEN (0)
71 #define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
72 #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
75 #define CONF_CORE_CLK_XOSC32K_ENABLE (1)
76 #define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
77 #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
78 #define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)
79 #define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)
80 #define CONF_CORE_CLK_XOSC32K_EN1K (0)
81 #define CONF_CORE_CLK_XOSC32K_EN32K (1)
82 #define CONF_CORE_CLK_XOSC32K_XTALEN (1)
83 #define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)
84 #define CONF_CORE_CLK_XOSC32K_CFDEN (0)
85 #define CONF_CORE_CLK_XOSC32K_SWBACK (0)
86 #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
99 #define CONF_CORE_CLK_DFLL_ENABLE (1)
107 #define CONF_CORE_CLK_DFLL_ONDEMAND (0)
115 #define CONF_CORE_CLK_DFLL_RUNSTDBY (0)
124 #define CONF_CORE_CLK_DFLL_WAITLOCK (0)
125 #define CONF_CORE_CLK_DFLL_BPLKC (0)
126 #define CONF_CORE_CLK_DFLL_QLDIS (0)
127 #define CONF_CORE_CLK_DFLL_CCDIS (1)
128 #define CONF_CORE_CLK_DFLL_USBCRM (1)
129 #define CONF_CORE_CLK_DFLL_LLAW (0)
130 #define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
131 #define CONF_CORE_CLK_DFLL_MODE 0x01
132 #define CONF_CORE_CLK_DFLL_DIFF_VAL 0
133 #define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)
134 #define CONF_CORE_CLK_DFLL_FINE_VAL 128
135 #define CONF_CORE_CLK_DFLL_CSTEP_VAL 1
136 #define CONF_CORE_CLK_DFLL_FSTEP_VAL 1
137 #define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)
154 #define CONF_CORE_CLK_DFLL_GCLK_SRC 3
155 #define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0
159 #define CONF_CORE_CLK_DPLL0_ENABLE (1)
160 #define CONF_CORE_CLK_DPLL0_ONDEMAND (0)
161 #define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)
162 #define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0
163 #define CONF_CORE_CLK_DPLL0_LDR_VAL (119)
164 #define CONF_CORE_CLK_DPLL0_DIV_VAL (5)
165 #define CONF_CORE_CLK_DPLL0_DCOEN 0
166 #define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
167 #define CONF_CORE_CLK_DPLL0_LBYPASS 1
168 #define CONF_CORE_CLK_DPLL0_LTIME 0
169 #define CONF_CORE_CLK_DPLL0_WUF 0
170 #define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
171 #define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
194 #define CONF_CORE_CLK_DPLL0_FILTER 0x0
197 #define CONF_CORE_CLK_DPLL1_ENABLE (0)
198 #define CONF_CORE_CLK_DPLL1_ONDEMAND (0)
199 #define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)
200 #define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0
201 #define CONF_CORE_CLK_DPLL1_LDR_VAL (0)
202 #define CONF_CORE_CLK_DPLL1_DIV_VAL (0)
203 #define CONF_CORE_CLK_DPLL1_DCOEN 0
204 #define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
205 #define CONF_CORE_CLK_DPLL1_LBYPASS 0
206 #define CONF_CORE_CLK_DPLL1_LTIME 0
207 #define CONF_CORE_CLK_DPLL1_WUF 0
208 #define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
209 #define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
234 #define CONF_CORE_CLK_DPLL1_FILTER 0x0
237 #define CONF_CORE_GCLK_0_ENABLE 1
238 #define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1
239 #define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
240 #define CONF_CORE_GCLK_0_DIV_VAL 1
241 #define CONF_CORE_GCLK_0_DIVSEL 0
242 #define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1
243 #define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1
244 #define CONF_CORE_GCLK_0_IDC 1
246 #define CONF_CORE_GCLK_1_ENABLE 0
247 #define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0
248 #define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
249 #define CONF_CORE_GCLK_1_DIV_VAL 1
250 #define CONF_CORE_GCLK_1_DIVSEL 0
251 #define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0
252 #define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0
253 #define CONF_CORE_GCLK_1_IDC 0
255 #define CONF_CORE_GCLK_2_ENABLE 0
256 #define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0
257 #define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
258 #define CONF_CORE_GCLK_2_DIV_VAL 1
259 #define CONF_CORE_GCLK_2_DIVSEL 0
260 #define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0
261 #define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0
262 #define CONF_CORE_GCLK_2_IDC 0
264 #define CONF_CORE_GCLK_3_ENABLE 1
265 #define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0
266 #define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
267 #define CONF_CORE_GCLK_3_DIV_VAL 1
268 #define CONF_CORE_GCLK_3_DIVSEL 0
269 #define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0
270 #define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0
271 #define CONF_CORE_GCLK_3_IDC 0
273 #define CONF_CORE_GCLK_4_ENABLE 0
274 #define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0
275 #define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
276 #define CONF_CORE_GCLK_4_DIV_VAL 1
277 #define CONF_CORE_GCLK_4_DIVSEL 1
278 #define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0
279 #define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0
280 #define CONF_CORE_GCLK_4_IDC 0
282 #define CONF_CORE_GCLK_5_ENABLE 0
283 #define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0
284 #define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
285 #define CONF_CORE_GCLK_5_DIV_VAL 1
286 #define CONF_CORE_GCLK_5_DIVSEL 0
287 #define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0
288 #define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0
289 #define CONF_CORE_GCLK_5_IDC 0
291 #define CONF_CORE_GCLK_6_ENABLE 0
292 #define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0
293 #define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
294 #define CONF_CORE_GCLK_6_DIV_VAL 1
295 #define CONF_CORE_GCLK_6_DIVSEL 0
296 #define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0
297 #define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0
298 #define CONF_CORE_GCLK_6_IDC 0
300 #define CONF_CORE_GCLK_7_ENABLE 0
301 #define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0
302 #define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
303 #define CONF_CORE_GCLK_7_DIV_VAL 1
304 #define CONF_CORE_GCLK_7_DIVSEL 0
305 #define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0
306 #define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0
307 #define CONF_CORE_GCLK_7_IDC 0
309 #define CONF_CORE_GCLK_8_ENABLE 0
310 #define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0
311 #define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
312 #define CONF_CORE_GCLK_8_DIV_VAL 1
313 #define CONF_CORE_GCLK_8_DIVSEL 0
314 #define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0
315 #define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0
316 #define CONF_CORE_GCLK_8_IDC 0
318 #define CONF_CORE_GCLK_9_ENABLE 0
319 #define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0
320 #define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
321 #define CONF_CORE_GCLK_9_DIV_VAL 1
322 #define CONF_CORE_GCLK_9_DIVSEL 0
323 #define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0
324 #define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0
325 #define CONF_CORE_GCLK_9_IDC 0
327 #define CONF_CORE_GCLK_10_ENABLE 0
328 #define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0
329 #define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
330 #define CONF_CORE_GCLK_10_DIV_VAL 1
331 #define CONF_CORE_GCLK_10_DIVSEL 0
332 #define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0
333 #define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0
334 #define CONF_CORE_GCLK_10_IDC 0
336 #define CONF_CORE_GCLK_11_ENABLE 0
337 #define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0
338 #define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
339 #define CONF_CORE_GCLK_11_DIV_VAL 1
340 #define CONF_CORE_GCLK_11_DIVSEL 0
341 #define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0
342 #define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0
343 #define CONF_CORE_GCLK_11_IDC 0