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30 #ifndef _SAME54_NVMCTRL_COMPONENT_
31 #define _SAME54_NVMCTRL_COMPONENT_
40 #define REV_NVMCTRL 0x100
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
61 #define NVMCTRL_CTRLA_OFFSET 0x00
62 #define NVMCTRL_CTRLA_RESETVALUE _U_(0x0004)
64 #define NVMCTRL_CTRLA_AUTOWS_Pos 2
65 #define NVMCTRL_CTRLA_AUTOWS (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos)
66 #define NVMCTRL_CTRLA_SUSPEN_Pos 3
67 #define NVMCTRL_CTRLA_SUSPEN (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos)
68 #define NVMCTRL_CTRLA_WMODE_Pos 4
69 #define NVMCTRL_CTRLA_WMODE_Msk (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos)
70 #define NVMCTRL_CTRLA_WMODE(value) (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos))
71 #define NVMCTRL_CTRLA_WMODE_MAN_Val _U_(0x0)
72 #define NVMCTRL_CTRLA_WMODE_ADW_Val _U_(0x1)
73 #define NVMCTRL_CTRLA_WMODE_AQW_Val _U_(0x2)
74 #define NVMCTRL_CTRLA_WMODE_AP_Val _U_(0x3)
75 #define NVMCTRL_CTRLA_WMODE_MAN (NVMCTRL_CTRLA_WMODE_MAN_Val << NVMCTRL_CTRLA_WMODE_Pos)
76 #define NVMCTRL_CTRLA_WMODE_ADW (NVMCTRL_CTRLA_WMODE_ADW_Val << NVMCTRL_CTRLA_WMODE_Pos)
77 #define NVMCTRL_CTRLA_WMODE_AQW (NVMCTRL_CTRLA_WMODE_AQW_Val << NVMCTRL_CTRLA_WMODE_Pos)
78 #define NVMCTRL_CTRLA_WMODE_AP (NVMCTRL_CTRLA_WMODE_AP_Val << NVMCTRL_CTRLA_WMODE_Pos)
79 #define NVMCTRL_CTRLA_PRM_Pos 6
80 #define NVMCTRL_CTRLA_PRM_Msk (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos)
81 #define NVMCTRL_CTRLA_PRM(value) (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos))
82 #define NVMCTRL_CTRLA_PRM_SEMIAUTO_Val _U_(0x0)
83 #define NVMCTRL_CTRLA_PRM_FULLAUTO_Val _U_(0x1)
84 #define NVMCTRL_CTRLA_PRM_MANUAL_Val _U_(0x3)
85 #define NVMCTRL_CTRLA_PRM_SEMIAUTO (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
86 #define NVMCTRL_CTRLA_PRM_FULLAUTO (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
87 #define NVMCTRL_CTRLA_PRM_MANUAL (NVMCTRL_CTRLA_PRM_MANUAL_Val << NVMCTRL_CTRLA_PRM_Pos)
88 #define NVMCTRL_CTRLA_RWS_Pos 8
89 #define NVMCTRL_CTRLA_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos)
90 #define NVMCTRL_CTRLA_RWS(value) (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos))
91 #define NVMCTRL_CTRLA_AHBNS0_Pos 12
92 #define NVMCTRL_CTRLA_AHBNS0 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos)
93 #define NVMCTRL_CTRLA_AHBNS1_Pos 13
94 #define NVMCTRL_CTRLA_AHBNS1 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos)
95 #define NVMCTRL_CTRLA_CACHEDIS0_Pos 14
96 #define NVMCTRL_CTRLA_CACHEDIS0 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos)
97 #define NVMCTRL_CTRLA_CACHEDIS1_Pos 15
98 #define NVMCTRL_CTRLA_CACHEDIS1 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos)
99 #define NVMCTRL_CTRLA_MASK _U_(0xFFFC)
102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
113 #define NVMCTRL_CTRLB_OFFSET 0x04
114 #define NVMCTRL_CTRLB_RESETVALUE _U_(0x0000)
116 #define NVMCTRL_CTRLB_CMD_Pos 0
117 #define NVMCTRL_CTRLB_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos)
118 #define NVMCTRL_CTRLB_CMD(value) (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos))
119 #define NVMCTRL_CTRLB_CMD_EP_Val _U_(0x0)
120 #define NVMCTRL_CTRLB_CMD_EB_Val _U_(0x1)
121 #define NVMCTRL_CTRLB_CMD_WP_Val _U_(0x3)
122 #define NVMCTRL_CTRLB_CMD_WQW_Val _U_(0x4)
123 #define NVMCTRL_CTRLB_CMD_SWRST_Val _U_(0x10)
124 #define NVMCTRL_CTRLB_CMD_LR_Val _U_(0x11)
125 #define NVMCTRL_CTRLB_CMD_UR_Val _U_(0x12)
126 #define NVMCTRL_CTRLB_CMD_SPRM_Val _U_(0x13)
127 #define NVMCTRL_CTRLB_CMD_CPRM_Val _U_(0x14)
128 #define NVMCTRL_CTRLB_CMD_PBC_Val _U_(0x15)
129 #define NVMCTRL_CTRLB_CMD_SSB_Val _U_(0x16)
130 #define NVMCTRL_CTRLB_CMD_BKSWRST_Val _U_(0x17)
131 #define NVMCTRL_CTRLB_CMD_CELCK_Val _U_(0x18)
132 #define NVMCTRL_CTRLB_CMD_CEULCK_Val _U_(0x19)
133 #define NVMCTRL_CTRLB_CMD_SBPDIS_Val _U_(0x1A)
134 #define NVMCTRL_CTRLB_CMD_CBPDIS_Val _U_(0x1B)
135 #define NVMCTRL_CTRLB_CMD_ASEES0_Val _U_(0x30)
136 #define NVMCTRL_CTRLB_CMD_ASEES1_Val _U_(0x31)
137 #define NVMCTRL_CTRLB_CMD_SEERALOC_Val _U_(0x32)
138 #define NVMCTRL_CTRLB_CMD_SEEFLUSH_Val _U_(0x33)
139 #define NVMCTRL_CTRLB_CMD_LSEE_Val _U_(0x34)
140 #define NVMCTRL_CTRLB_CMD_USEE_Val _U_(0x35)
141 #define NVMCTRL_CTRLB_CMD_LSEER_Val _U_(0x36)
142 #define NVMCTRL_CTRLB_CMD_USEER_Val _U_(0x37)
143 #define NVMCTRL_CTRLB_CMD_EP (NVMCTRL_CTRLB_CMD_EP_Val << NVMCTRL_CTRLB_CMD_Pos)
144 #define NVMCTRL_CTRLB_CMD_EB (NVMCTRL_CTRLB_CMD_EB_Val << NVMCTRL_CTRLB_CMD_Pos)
145 #define NVMCTRL_CTRLB_CMD_WP (NVMCTRL_CTRLB_CMD_WP_Val << NVMCTRL_CTRLB_CMD_Pos)
146 #define NVMCTRL_CTRLB_CMD_WQW (NVMCTRL_CTRLB_CMD_WQW_Val << NVMCTRL_CTRLB_CMD_Pos)
147 #define NVMCTRL_CTRLB_CMD_SWRST (NVMCTRL_CTRLB_CMD_SWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
148 #define NVMCTRL_CTRLB_CMD_LR (NVMCTRL_CTRLB_CMD_LR_Val << NVMCTRL_CTRLB_CMD_Pos)
149 #define NVMCTRL_CTRLB_CMD_UR (NVMCTRL_CTRLB_CMD_UR_Val << NVMCTRL_CTRLB_CMD_Pos)
150 #define NVMCTRL_CTRLB_CMD_SPRM (NVMCTRL_CTRLB_CMD_SPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
151 #define NVMCTRL_CTRLB_CMD_CPRM (NVMCTRL_CTRLB_CMD_CPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
152 #define NVMCTRL_CTRLB_CMD_PBC (NVMCTRL_CTRLB_CMD_PBC_Val << NVMCTRL_CTRLB_CMD_Pos)
153 #define NVMCTRL_CTRLB_CMD_SSB (NVMCTRL_CTRLB_CMD_SSB_Val << NVMCTRL_CTRLB_CMD_Pos)
154 #define NVMCTRL_CTRLB_CMD_BKSWRST (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
155 #define NVMCTRL_CTRLB_CMD_CELCK (NVMCTRL_CTRLB_CMD_CELCK_Val << NVMCTRL_CTRLB_CMD_Pos)
156 #define NVMCTRL_CTRLB_CMD_CEULCK (NVMCTRL_CTRLB_CMD_CEULCK_Val << NVMCTRL_CTRLB_CMD_Pos)
157 #define NVMCTRL_CTRLB_CMD_SBPDIS (NVMCTRL_CTRLB_CMD_SBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
158 #define NVMCTRL_CTRLB_CMD_CBPDIS (NVMCTRL_CTRLB_CMD_CBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
159 #define NVMCTRL_CTRLB_CMD_ASEES0 (NVMCTRL_CTRLB_CMD_ASEES0_Val << NVMCTRL_CTRLB_CMD_Pos)
160 #define NVMCTRL_CTRLB_CMD_ASEES1 (NVMCTRL_CTRLB_CMD_ASEES1_Val << NVMCTRL_CTRLB_CMD_Pos)
161 #define NVMCTRL_CTRLB_CMD_SEERALOC (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos)
162 #define NVMCTRL_CTRLB_CMD_SEEFLUSH (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos)
163 #define NVMCTRL_CTRLB_CMD_LSEE (NVMCTRL_CTRLB_CMD_LSEE_Val << NVMCTRL_CTRLB_CMD_Pos)
164 #define NVMCTRL_CTRLB_CMD_USEE (NVMCTRL_CTRLB_CMD_USEE_Val << NVMCTRL_CTRLB_CMD_Pos)
165 #define NVMCTRL_CTRLB_CMD_LSEER (NVMCTRL_CTRLB_CMD_LSEER_Val << NVMCTRL_CTRLB_CMD_Pos)
166 #define NVMCTRL_CTRLB_CMD_USEER (NVMCTRL_CTRLB_CMD_USEER_Val << NVMCTRL_CTRLB_CMD_Pos)
167 #define NVMCTRL_CTRLB_CMDEX_Pos 8
168 #define NVMCTRL_CTRLB_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos)
169 #define NVMCTRL_CTRLB_CMDEX(value) (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos))
170 #define NVMCTRL_CTRLB_CMDEX_KEY_Val _U_(0xA5)
171 #define NVMCTRL_CTRLB_CMDEX_KEY (NVMCTRL_CTRLB_CMDEX_KEY_Val << NVMCTRL_CTRLB_CMDEX_Pos)
172 #define NVMCTRL_CTRLB_MASK _U_(0xFF7F)
175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
187 #define NVMCTRL_PARAM_OFFSET 0x08
188 #define NVMCTRL_PARAM_RESETVALUE _U_(0x00060000)
190 #define NVMCTRL_PARAM_NVMP_Pos 0
191 #define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
192 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
193 #define NVMCTRL_PARAM_PSZ_Pos 16
194 #define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
195 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
196 #define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0)
197 #define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1)
198 #define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2)
199 #define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3)
200 #define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4)
201 #define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5)
202 #define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6)
203 #define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7)
204 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
205 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
206 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
207 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
208 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
209 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
210 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
211 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
212 #define NVMCTRL_PARAM_SEE_Pos 31
213 #define NVMCTRL_PARAM_SEE (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos)
214 #define NVMCTRL_PARAM_MASK _U_(0x8007FFFF)
217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
237 #define NVMCTRL_INTENCLR_OFFSET 0x0C
238 #define NVMCTRL_INTENCLR_RESETVALUE _U_(0x0000)
240 #define NVMCTRL_INTENCLR_DONE_Pos 0
241 #define NVMCTRL_INTENCLR_DONE (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos)
242 #define NVMCTRL_INTENCLR_ADDRE_Pos 1
243 #define NVMCTRL_INTENCLR_ADDRE (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos)
244 #define NVMCTRL_INTENCLR_PROGE_Pos 2
245 #define NVMCTRL_INTENCLR_PROGE (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos)
246 #define NVMCTRL_INTENCLR_LOCKE_Pos 3
247 #define NVMCTRL_INTENCLR_LOCKE (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos)
248 #define NVMCTRL_INTENCLR_ECCSE_Pos 4
249 #define NVMCTRL_INTENCLR_ECCSE (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos)
250 #define NVMCTRL_INTENCLR_ECCDE_Pos 5
251 #define NVMCTRL_INTENCLR_ECCDE (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos)
252 #define NVMCTRL_INTENCLR_NVME_Pos 6
253 #define NVMCTRL_INTENCLR_NVME (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos)
254 #define NVMCTRL_INTENCLR_SUSP_Pos 7
255 #define NVMCTRL_INTENCLR_SUSP (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos)
256 #define NVMCTRL_INTENCLR_SEESFULL_Pos 8
257 #define NVMCTRL_INTENCLR_SEESFULL (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos)
258 #define NVMCTRL_INTENCLR_SEESOVF_Pos 9
259 #define NVMCTRL_INTENCLR_SEESOVF (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos)
260 #define NVMCTRL_INTENCLR_SEEWRC_Pos 10
261 #define NVMCTRL_INTENCLR_SEEWRC (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos)
262 #define NVMCTRL_INTENCLR_MASK _U_(0x07FF)
265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
285 #define NVMCTRL_INTENSET_OFFSET 0x0E
286 #define NVMCTRL_INTENSET_RESETVALUE _U_(0x0000)
288 #define NVMCTRL_INTENSET_DONE_Pos 0
289 #define NVMCTRL_INTENSET_DONE (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos)
290 #define NVMCTRL_INTENSET_ADDRE_Pos 1
291 #define NVMCTRL_INTENSET_ADDRE (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos)
292 #define NVMCTRL_INTENSET_PROGE_Pos 2
293 #define NVMCTRL_INTENSET_PROGE (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos)
294 #define NVMCTRL_INTENSET_LOCKE_Pos 3
295 #define NVMCTRL_INTENSET_LOCKE (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos)
296 #define NVMCTRL_INTENSET_ECCSE_Pos 4
297 #define NVMCTRL_INTENSET_ECCSE (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos)
298 #define NVMCTRL_INTENSET_ECCDE_Pos 5
299 #define NVMCTRL_INTENSET_ECCDE (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos)
300 #define NVMCTRL_INTENSET_NVME_Pos 6
301 #define NVMCTRL_INTENSET_NVME (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos)
302 #define NVMCTRL_INTENSET_SUSP_Pos 7
303 #define NVMCTRL_INTENSET_SUSP (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos)
304 #define NVMCTRL_INTENSET_SEESFULL_Pos 8
305 #define NVMCTRL_INTENSET_SEESFULL (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos)
306 #define NVMCTRL_INTENSET_SEESOVF_Pos 9
307 #define NVMCTRL_INTENSET_SEESOVF (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos)
308 #define NVMCTRL_INTENSET_SEEWRC_Pos 10
309 #define NVMCTRL_INTENSET_SEEWRC (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos)
310 #define NVMCTRL_INTENSET_MASK _U_(0x07FF)
313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
333 #define NVMCTRL_INTFLAG_OFFSET 0x10
334 #define NVMCTRL_INTFLAG_RESETVALUE _U_(0x0000)
336 #define NVMCTRL_INTFLAG_DONE_Pos 0
337 #define NVMCTRL_INTFLAG_DONE (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos)
338 #define NVMCTRL_INTFLAG_ADDRE_Pos 1
339 #define NVMCTRL_INTFLAG_ADDRE (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos)
340 #define NVMCTRL_INTFLAG_PROGE_Pos 2
341 #define NVMCTRL_INTFLAG_PROGE (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos)
342 #define NVMCTRL_INTFLAG_LOCKE_Pos 3
343 #define NVMCTRL_INTFLAG_LOCKE (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos)
344 #define NVMCTRL_INTFLAG_ECCSE_Pos 4
345 #define NVMCTRL_INTFLAG_ECCSE (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos)
346 #define NVMCTRL_INTFLAG_ECCDE_Pos 5
347 #define NVMCTRL_INTFLAG_ECCDE (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos)
348 #define NVMCTRL_INTFLAG_NVME_Pos 6
349 #define NVMCTRL_INTFLAG_NVME (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos)
350 #define NVMCTRL_INTFLAG_SUSP_Pos 7
351 #define NVMCTRL_INTFLAG_SUSP (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos)
352 #define NVMCTRL_INTFLAG_SEESFULL_Pos 8
353 #define NVMCTRL_INTFLAG_SEESFULL (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos)
354 #define NVMCTRL_INTFLAG_SEESOVF_Pos 9
355 #define NVMCTRL_INTFLAG_SEESOVF (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos)
356 #define NVMCTRL_INTFLAG_SEEWRC_Pos 10
357 #define NVMCTRL_INTFLAG_SEEWRC (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos)
358 #define NVMCTRL_INTFLAG_MASK _U_(0x07FF)
361 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
378 #define NVMCTRL_STATUS_OFFSET 0x12
379 #define NVMCTRL_STATUS_RESETVALUE _U_(0x0000)
381 #define NVMCTRL_STATUS_READY_Pos 0
382 #define NVMCTRL_STATUS_READY (_U_(0x1) << NVMCTRL_STATUS_READY_Pos)
383 #define NVMCTRL_STATUS_PRM_Pos 1
384 #define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
385 #define NVMCTRL_STATUS_LOAD_Pos 2
386 #define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
387 #define NVMCTRL_STATUS_SUSP_Pos 3
388 #define NVMCTRL_STATUS_SUSP (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos)
389 #define NVMCTRL_STATUS_AFIRST_Pos 4
390 #define NVMCTRL_STATUS_AFIRST (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos)
391 #define NVMCTRL_STATUS_BPDIS_Pos 5
392 #define NVMCTRL_STATUS_BPDIS (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos)
393 #define NVMCTRL_STATUS_BOOTPROT_Pos 8
394 #define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos)
395 #define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos))
396 #define NVMCTRL_STATUS_MASK _U_(0x0F3F)
399 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
409 #define NVMCTRL_ADDR_OFFSET 0x14
410 #define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000)
412 #define NVMCTRL_ADDR_ADDR_Pos 0
413 #define NVMCTRL_ADDR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos)
414 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
415 #define NVMCTRL_ADDR_MASK _U_(0x00FFFFFF)
418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
427 #define NVMCTRL_RUNLOCK_OFFSET 0x18
428 #define NVMCTRL_RUNLOCK_RESETVALUE _U_(0x00000000)
430 #define NVMCTRL_RUNLOCK_RUNLOCK_Pos 0
431 #define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)
432 #define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos))
433 #define NVMCTRL_RUNLOCK_MASK _U_(0xFFFFFFFF)
436 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
445 #define NVMCTRL_PBLDATA_OFFSET 0x1C
446 #define NVMCTRL_PBLDATA_RESETVALUE _U_(0xFFFFFFFF)
448 #define NVMCTRL_PBLDATA_DATA_Pos 0
449 #define NVMCTRL_PBLDATA_DATA_Msk (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos)
450 #define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos))
451 #define NVMCTRL_PBLDATA_MASK _U_(0xFFFFFFFF)
454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
466 #define NVMCTRL_ECCERR_OFFSET 0x24
467 #define NVMCTRL_ECCERR_RESETVALUE _U_(0x00000000)
469 #define NVMCTRL_ECCERR_ADDR_Pos 0
470 #define NVMCTRL_ECCERR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos)
471 #define NVMCTRL_ECCERR_ADDR(value) (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos))
472 #define NVMCTRL_ECCERR_TYPEL_Pos 28
473 #define NVMCTRL_ECCERR_TYPEL_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos)
474 #define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos))
475 #define NVMCTRL_ECCERR_TYPEL_NONE_Val _U_(0x0)
476 #define NVMCTRL_ECCERR_TYPEL_SINGLE_Val _U_(0x1)
477 #define NVMCTRL_ECCERR_TYPEL_DUAL_Val _U_(0x2)
478 #define NVMCTRL_ECCERR_TYPEL_NONE (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
479 #define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
480 #define NVMCTRL_ECCERR_TYPEL_DUAL (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos)
481 #define NVMCTRL_ECCERR_TYPEH_Pos 30
482 #define NVMCTRL_ECCERR_TYPEH_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos)
483 #define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos))
484 #define NVMCTRL_ECCERR_TYPEH_NONE_Val _U_(0x0)
485 #define NVMCTRL_ECCERR_TYPEH_SINGLE_Val _U_(0x1)
486 #define NVMCTRL_ECCERR_TYPEH_DUAL_Val _U_(0x2)
487 #define NVMCTRL_ECCERR_TYPEH_NONE (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
488 #define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
489 #define NVMCTRL_ECCERR_TYPEH_DUAL (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos)
490 #define NVMCTRL_ECCERR_MASK _U_(0xF0FFFFFF)
493 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
504 #define NVMCTRL_DBGCTRL_OFFSET 0x28
505 #define NVMCTRL_DBGCTRL_RESETVALUE _U_(0x00)
507 #define NVMCTRL_DBGCTRL_ECCDIS_Pos 0
508 #define NVMCTRL_DBGCTRL_ECCDIS (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos)
509 #define NVMCTRL_DBGCTRL_ECCELOG_Pos 1
510 #define NVMCTRL_DBGCTRL_ECCELOG (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos)
511 #define NVMCTRL_DBGCTRL_MASK _U_(0x03)
514 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
525 #define NVMCTRL_SEECFG_OFFSET 0x2A
526 #define NVMCTRL_SEECFG_RESETVALUE _U_(0x00)
528 #define NVMCTRL_SEECFG_WMODE_Pos 0
529 #define NVMCTRL_SEECFG_WMODE (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos)
530 #define NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0)
531 #define NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1)
532 #define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
533 #define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
534 #define NVMCTRL_SEECFG_APRDIS_Pos 1
535 #define NVMCTRL_SEECFG_APRDIS (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos)
536 #define NVMCTRL_SEECFG_MASK _U_(0x03)
539 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
557 #define NVMCTRL_SEESTAT_OFFSET 0x2C
558 #define NVMCTRL_SEESTAT_RESETVALUE _U_(0x00000000)
560 #define NVMCTRL_SEESTAT_ASEES_Pos 0
561 #define NVMCTRL_SEESTAT_ASEES (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos)
562 #define NVMCTRL_SEESTAT_LOAD_Pos 1
563 #define NVMCTRL_SEESTAT_LOAD (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos)
564 #define NVMCTRL_SEESTAT_BUSY_Pos 2
565 #define NVMCTRL_SEESTAT_BUSY (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos)
566 #define NVMCTRL_SEESTAT_LOCK_Pos 3
567 #define NVMCTRL_SEESTAT_LOCK (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos)
568 #define NVMCTRL_SEESTAT_RLOCK_Pos 4
569 #define NVMCTRL_SEESTAT_RLOCK (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos)
570 #define NVMCTRL_SEESTAT_SBLK_Pos 8
571 #define NVMCTRL_SEESTAT_SBLK_Msk (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos)
572 #define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos))
573 #define NVMCTRL_SEESTAT_PSZ_Pos 16
574 #define NVMCTRL_SEESTAT_PSZ_Msk (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos)
575 #define NVMCTRL_SEESTAT_PSZ(value) (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos))
576 #define NVMCTRL_SEESTAT_MASK _U_(0x00070F1F)
579 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
602 #define SECTION_NVMCTRL_SW0
603 #define SECTION_NVMCTRL_TEMP_LOG
604 #define SECTION_NVMCTRL_USER
615 #define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
616 #define AC_FUSES_BIAS0_Pos 0
617 #define AC_FUSES_BIAS0_Msk (_U_(0x3) << AC_FUSES_BIAS0_Pos)
618 #define AC_FUSES_BIAS0(value) (AC_FUSES_BIAS0_Msk & ((value) << AC_FUSES_BIAS0_Pos))
620 #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
621 #define ADC0_FUSES_BIASCOMP_Pos 2
622 #define ADC0_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos)
623 #define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos))
625 #define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
626 #define ADC0_FUSES_BIASR2R_Pos 8
627 #define ADC0_FUSES_BIASR2R_Msk (_U_(0x7) << ADC0_FUSES_BIASR2R_Pos)
628 #define ADC0_FUSES_BIASR2R(value) (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos))
630 #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
631 #define ADC0_FUSES_BIASREFBUF_Pos 5
632 #define ADC0_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos)
633 #define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos))
635 #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
636 #define ADC1_FUSES_BIASCOMP_Pos 16
637 #define ADC1_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos)
638 #define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos))
640 #define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
641 #define ADC1_FUSES_BIASR2R_Pos 22
642 #define ADC1_FUSES_BIASR2R_Msk (_U_(0x7) << ADC1_FUSES_BIASR2R_Pos)
643 #define ADC1_FUSES_BIASR2R(value) (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos))
645 #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
646 #define ADC1_FUSES_BIASREFBUF_Pos 19
647 #define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
648 #define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
650 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
651 #define FUSES_BOD33USERLEVEL_Pos 1
652 #define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
653 #define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
655 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
656 #define FUSES_BOD33_ACTION_Pos 9
657 #define FUSES_BOD33_ACTION_Msk (_U_(0x3) << FUSES_BOD33_ACTION_Pos)
658 #define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
660 #define FUSES_BOD33_DIS_ADDR NVMCTRL_USER
661 #define FUSES_BOD33_DIS_Pos 0
662 #define FUSES_BOD33_DIS_Msk (_U_(0x1) << FUSES_BOD33_DIS_Pos)
664 #define FUSES_BOD33_HYST_ADDR NVMCTRL_USER
665 #define FUSES_BOD33_HYST_Pos 11
666 #define FUSES_BOD33_HYST_Msk (_U_(0xF) << FUSES_BOD33_HYST_Pos)
667 #define FUSES_BOD33_HYST(value) (FUSES_BOD33_HYST_Msk & ((value) << FUSES_BOD33_HYST_Pos))
669 #define FUSES_HOT_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
670 #define FUSES_HOT_ADC_VAL_CTAT_Pos 12
671 #define FUSES_HOT_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_CTAT_Pos)
672 #define FUSES_HOT_ADC_VAL_CTAT(value) (FUSES_HOT_ADC_VAL_CTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_CTAT_Pos))
674 #define FUSES_HOT_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
675 #define FUSES_HOT_ADC_VAL_PTAT_Pos 20
676 #define FUSES_HOT_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_PTAT_Pos)
677 #define FUSES_HOT_ADC_VAL_PTAT(value) (FUSES_HOT_ADC_VAL_PTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_PTAT_Pos))
679 #define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
680 #define FUSES_HOT_INT1V_VAL_Pos 0
681 #define FUSES_HOT_INT1V_VAL_Msk (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
682 #define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
684 #define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
685 #define FUSES_HOT_TEMP_VAL_DEC_Pos 20
686 #define FUSES_HOT_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
687 #define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
689 #define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
690 #define FUSES_HOT_TEMP_VAL_INT_Pos 12
691 #define FUSES_HOT_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
692 #define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
694 #define FUSES_ROOM_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
695 #define FUSES_ROOM_ADC_VAL_CTAT_Pos 0
696 #define FUSES_ROOM_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_CTAT_Pos)
697 #define FUSES_ROOM_ADC_VAL_CTAT(value) (FUSES_ROOM_ADC_VAL_CTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_CTAT_Pos))
699 #define FUSES_ROOM_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
700 #define FUSES_ROOM_ADC_VAL_PTAT_Pos 8
701 #define FUSES_ROOM_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_PTAT_Pos)
702 #define FUSES_ROOM_ADC_VAL_PTAT(value) (FUSES_ROOM_ADC_VAL_PTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_PTAT_Pos))
704 #define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
705 #define FUSES_ROOM_INT1V_VAL_Pos 24
706 #define FUSES_ROOM_INT1V_VAL_Msk (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
707 #define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
709 #define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
710 #define FUSES_ROOM_TEMP_VAL_DEC_Pos 8
711 #define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
712 #define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
714 #define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
715 #define FUSES_ROOM_TEMP_VAL_INT_Pos 0
716 #define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
717 #define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
719 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
720 #define NVMCTRL_FUSES_BOOTPROT_Pos 26
721 #define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_FUSES_BOOTPROT_Pos)
722 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
724 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 8)
725 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 0
726 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFFFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
727 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
729 #define NVMCTRL_FUSES_SEEPSZ_ADDR (NVMCTRL_USER + 4)
730 #define NVMCTRL_FUSES_SEEPSZ_Pos 4
731 #define NVMCTRL_FUSES_SEEPSZ_Msk (_U_(0x7) << NVMCTRL_FUSES_SEEPSZ_Pos)
732 #define NVMCTRL_FUSES_SEEPSZ(value) (NVMCTRL_FUSES_SEEPSZ_Msk & ((value) << NVMCTRL_FUSES_SEEPSZ_Pos))
734 #define NVMCTRL_FUSES_SEESBLK_ADDR (NVMCTRL_USER + 4)
735 #define NVMCTRL_FUSES_SEESBLK_Pos 0
736 #define NVMCTRL_FUSES_SEESBLK_Msk (_U_(0xF) << NVMCTRL_FUSES_SEESBLK_Pos)
737 #define NVMCTRL_FUSES_SEESBLK(value) (NVMCTRL_FUSES_SEESBLK_Msk & ((value) << NVMCTRL_FUSES_SEESBLK_Pos))
739 #define RAMECC_FUSES_ECCDIS_ADDR (NVMCTRL_USER + 4)
740 #define RAMECC_FUSES_ECCDIS_Pos 7
741 #define RAMECC_FUSES_ECCDIS_Msk (_U_(0x1) << RAMECC_FUSES_ECCDIS_Pos)
743 #define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
744 #define USB_FUSES_TRANSN_Pos 0
745 #define USB_FUSES_TRANSN_Msk (_U_(0x1F) << USB_FUSES_TRANSN_Pos)
746 #define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
748 #define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
749 #define USB_FUSES_TRANSP_Pos 5
750 #define USB_FUSES_TRANSP_Msk (_U_(0x1F) << USB_FUSES_TRANSP_Pos)
751 #define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
753 #define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
754 #define USB_FUSES_TRIM_Pos 10
755 #define USB_FUSES_TRIM_Msk (_U_(0x7) << USB_FUSES_TRIM_Pos)
756 #define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
758 #define WDT_FUSES_ALWAYSON_ADDR (NVMCTRL_USER + 4)
759 #define WDT_FUSES_ALWAYSON_Pos 17
760 #define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
762 #define WDT_FUSES_ENABLE_ADDR (NVMCTRL_USER + 4)
763 #define WDT_FUSES_ENABLE_Pos 16
764 #define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
766 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
767 #define WDT_FUSES_EWOFFSET_Pos 26
768 #define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
769 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
771 #define WDT_FUSES_PER_ADDR (NVMCTRL_USER + 4)
772 #define WDT_FUSES_PER_Pos 18
773 #define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos)
774 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
776 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
777 #define WDT_FUSES_WEN_Pos 30
778 #define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos)
780 #define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4)
781 #define WDT_FUSES_WINDOW_Pos 22
782 #define WDT_FUSES_WINDOW_Msk (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
783 #define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
__IO NVMCTRL_INTFLAG_Type INTFLAG
Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear.
__O NVMCTRL_CTRLB_Type CTRLB
Offset: 0x04 ( /W 16) Control B.
__IO NVMCTRL_DBGCTRL_Type DBGCTRL
Offset: 0x28 (R/W 8) Debug Control.
__I NVMCTRL_RUNLOCK_Type RUNLOCK
Offset: 0x18 (R/ 32) Lock Section.
__IO NVMCTRL_ADDR_Type ADDR
Offset: 0x14 (R/W 32) Address.
__IO NVMCTRL_SEECFG_Type SEECFG
Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register.
__I NVMCTRL_STATUS_Type STATUS
Offset: 0x12 (R/ 16) Status.
__IO NVMCTRL_INTENSET_Type INTENSET
Offset: 0x0E (R/W 16) Interrupt Enable Set.
__I NVMCTRL_ECCERR_Type ECCERR
Offset: 0x24 (R/ 32) ECC Error Status Register.
__I NVMCTRL_PARAM_Type PARAM
Offset: 0x08 (R/ 32) NVM Parameter.
NVMCTRL APB hardware registers.
__IO NVMCTRL_CTRLA_Type CTRLA
Offset: 0x00 (R/W 16) Control A.
volatile const uint8_t RoReg8
__IO NVMCTRL_INTENCLR_Type INTENCLR
Offset: 0x0C (R/W 16) Interrupt Enable Clear.
__I NVMCTRL_SEESTAT_Type SEESTAT
Offset: 0x2C (R/ 32) SmartEEPROM Status Register.