SAME54P20A Test Project
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#include "clocks.h"
Go to the source code of this file.
Macros | |
#define | CONF_CORE_MCLK_NVM_WAIT_STATE 0x5 |
#define | CONF_CORE_MCLK_CPUDIV 0x1 |
#define | CONF_CORE_DMA_ENABLE (0) |
#define | CONF_CORE_CMCC_ENABLE (0) |
#define | CONF_CORE_PORT_EVCTRL_0_ENABLE (0) |
#define | CONF_CORE_PORT_EVCTRL_1_ENABLE (0) |
#define | CONF_CORE_PORT_EVCTRL_2_ENABLE (0) |
#define | CONF_CORE_CLK_XOSC0_ENABLE (1) |
#define | CONF_CORE_CLK_XOSC0_XTALEN (1) |
#define | CONF_CORE_CLK_XOSC0_RUNSTDBY (0) |
#define | CONF_CORE_CLK_XOSC0_ONDEMAND (0) |
#define | CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0) |
#define | CONF_CORE_CLK_XOSC0_ENALC (1) |
#define | CONF_CORE_CLK_XOSC0_CFDEN (1) |
#define | CONF_CORE_CLK_XOSC0_SWBEN (0) |
#define | CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us |
#define | CONF_CORE_CLK_XOSC0_FREQUENCY 12000000 |
#define | CONF_CORE_CLK_XOSC1_ENABLE (0) |
#define | CONF_CORE_CLK_XOSC1_XTALEN (0) |
#define | CONF_CORE_CLK_XOSC1_RUNSTDBY (0) |
#define | CONF_CORE_CLK_XOSC1_ONDEMAND (0) |
#define | CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0) |
#define | CONF_CORE_CLK_XOSC1_ENALC (0) |
#define | CONF_CORE_CLK_XOSC1_CFDEN (0) |
#define | CONF_CORE_CLK_XOSC1_SWBEN (0) |
#define | CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us |
#define | CONF_CORE_CLK_XOSC1_FREQUENCY 12000000 |
#define | CONF_CORE_CLK_XOSC32K_ENABLE (1) |
#define | CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE |
#define | CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us |
#define | CONF_CORE_CLK_XOSC32K_ONDEMAND (1) |
#define | CONF_CORE_CLK_XOSC32K_RUNSTDBY (0) |
#define | CONF_CORE_CLK_XOSC32K_EN1K (0) |
#define | CONF_CORE_CLK_XOSC32K_EN32K (1) |
#define | CONF_CORE_CLK_XOSC32K_XTALEN (1) |
#define | CONF_CORE_CLK_XOSC32K_CFDPRESC (0) |
#define | CONF_CORE_CLK_XOSC32K_CFDEN (0) |
#define | CONF_CORE_CLK_XOSC32K_SWBACK (0) |
#define | CONF_CORE_CLK_XOSC32K_WRTLOCK (0) |
#define | CONF_CORE_CLK_DPLL0_ENABLE (1) |
#define | CONF_CORE_CLK_DPLL0_ONDEMAND (0) |
#define | CONF_CORE_CLK_DPLL0_RUNSTDBY (0) |
#define | CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0 |
#define | CONF_CORE_CLK_DPLL0_LDR_VAL (119) |
#define | CONF_CORE_CLK_DPLL0_DIV_VAL (5) |
#define | CONF_CORE_CLK_DPLL0_DCOEN 0 |
#define | CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ |
#define | CONF_CORE_CLK_DPLL0_LBYPASS 1 |
#define | CONF_CORE_CLK_DPLL0_LTIME 0 |
#define | CONF_CORE_CLK_DPLL0_WUF 0 |
#define | CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 |
#define | CONF_CORE_CLK_DPLL0_FILTER 0x0 |
#define | CONF_CORE_CLK_DPLL1_ENABLE (0) |
#define | CONF_CORE_CLK_DPLL1_ONDEMAND (0) |
#define | CONF_CORE_CLK_DPLL1_RUNSTDBY (0) |
#define | CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0 |
#define | CONF_CORE_CLK_DPLL1_LDR_VAL (0) |
#define | CONF_CORE_CLK_DPLL1_DIV_VAL (0) |
#define | CONF_CORE_CLK_DPLL1_DCOEN 0 |
#define | CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ |
#define | CONF_CORE_CLK_DPLL1_LBYPASS 0 |
#define | CONF_CORE_CLK_DPLL1_LTIME 0 |
#define | CONF_CORE_CLK_DPLL1_WUF 0 |
#define | CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 |
#define | CONF_CORE_CLK_DPLL1_FILTER 0x0 |
#define | CONF_CORE_GCLK_0_ENABLE 1 |
#define | CONF_CORE_GCLK_0_RUN_IN_STANDBY 1 |
#define | CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_0_DIV_VAL 1 |
#define | CONF_CORE_GCLK_0_DIVSEL 0 |
#define | CONF_CORE_GCLK_0_OUTPUT_ENABLE 1 |
#define | CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1 |
#define | CONF_CORE_GCLK_0_IDC 1 |
#define | CONF_CORE_GCLK_1_ENABLE 0 |
#define | CONF_CORE_GCLK_1_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_1_DIV_VAL 1 |
#define | CONF_CORE_GCLK_1_DIVSEL 0 |
#define | CONF_CORE_GCLK_1_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_1_IDC 0 |
#define | CONF_CORE_GCLK_2_ENABLE 0 |
#define | CONF_CORE_GCLK_2_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_2_DIV_VAL 1 |
#define | CONF_CORE_GCLK_2_DIVSEL 0 |
#define | CONF_CORE_GCLK_2_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_2_IDC 0 |
#define | CONF_CORE_GCLK_3_ENABLE 1 |
#define | CONF_CORE_GCLK_3_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K |
#define | CONF_CORE_GCLK_3_DIV_VAL 1 |
#define | CONF_CORE_GCLK_3_DIVSEL 0 |
#define | CONF_CORE_GCLK_3_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_3_IDC 0 |
#define | CONF_CORE_GCLK_4_ENABLE 0 |
#define | CONF_CORE_GCLK_4_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_4_DIV_VAL 1 |
#define | CONF_CORE_GCLK_4_DIVSEL 1 |
#define | CONF_CORE_GCLK_4_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_4_IDC 0 |
#define | CONF_CORE_GCLK_5_ENABLE 0 |
#define | CONF_CORE_GCLK_5_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_5_DIV_VAL 1 |
#define | CONF_CORE_GCLK_5_DIVSEL 0 |
#define | CONF_CORE_GCLK_5_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_5_IDC 0 |
#define | CONF_CORE_GCLK_6_ENABLE 0 |
#define | CONF_CORE_GCLK_6_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_6_DIV_VAL 1 |
#define | CONF_CORE_GCLK_6_DIVSEL 0 |
#define | CONF_CORE_GCLK_6_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_6_IDC 0 |
#define | CONF_CORE_GCLK_7_ENABLE 0 |
#define | CONF_CORE_GCLK_7_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_7_DIV_VAL 1 |
#define | CONF_CORE_GCLK_7_DIVSEL 0 |
#define | CONF_CORE_GCLK_7_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_7_IDC 0 |
#define | CONF_CORE_GCLK_8_ENABLE 0 |
#define | CONF_CORE_GCLK_8_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_8_DIV_VAL 1 |
#define | CONF_CORE_GCLK_8_DIVSEL 0 |
#define | CONF_CORE_GCLK_8_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_8_IDC 0 |
#define | CONF_CORE_GCLK_9_ENABLE 0 |
#define | CONF_CORE_GCLK_9_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_9_DIV_VAL 1 |
#define | CONF_CORE_GCLK_9_DIVSEL 0 |
#define | CONF_CORE_GCLK_9_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_9_IDC 0 |
#define | CONF_CORE_GCLK_10_ENABLE 0 |
#define | CONF_CORE_GCLK_10_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_10_DIV_VAL 1 |
#define | CONF_CORE_GCLK_10_DIVSEL 0 |
#define | CONF_CORE_GCLK_10_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_10_IDC 0 |
#define | CONF_CORE_GCLK_11_ENABLE 0 |
#define | CONF_CORE_GCLK_11_RUN_IN_STANDBY 0 |
#define | CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0 |
#define | CONF_CORE_GCLK_11_DIV_VAL 1 |
#define | CONF_CORE_GCLK_11_DIVSEL 0 |
#define | CONF_CORE_GCLK_11_OUTPUT_ENABLE 0 |
#define | CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0 |
#define | CONF_CORE_GCLK_11_IDC 0 |
Core-DFLL48M-Configuration | |
Configuration options for DFLL48M | |
#define | CONF_CORE_CLK_DFLL_ENABLE (1) |
Enables or Disables the DFLL48M Clock. More... | |
#define | CONF_CORE_CLK_DFLL_ONDEMAND (0) |
Enables or Disables on-demand operation. More... | |
#define | CONF_CORE_CLK_DFLL_RUNSTDBY (0) |
Enables or Disables run-in-standby operation. More... | |
#define | CONF_CORE_CLK_DFLL_WAITLOCK (0) |
This bit controls the DFLL output clock, depending on the lock status: More... | |
#define | CONF_CORE_CLK_DFLL_BPLKC (0) |
#define | CONF_CORE_CLK_DFLL_QLDIS (0) |
#define | CONF_CORE_CLK_DFLL_CCDIS (1) |
#define | CONF_CORE_CLK_DFLL_USBCRM (1) |
#define | CONF_CORE_CLK_DFLL_LLAW (0) |
#define | CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED |
#define | CONF_CORE_CLK_DFLL_MODE 0x01 |
#define | CONF_CORE_CLK_DFLL_DIFF_VAL 0 |
#define | CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4) |
#define | CONF_CORE_CLK_DFLL_FINE_VAL 128 |
#define | CONF_CORE_CLK_DFLL_CSTEP_VAL 1 |
#define | CONF_CORE_CLK_DFLL_FSTEP_VAL 1 |
#define | CONF_CORE_CLK_DFLL_MUL_VAL (48000000) |
#define | CONF_CORE_CLK_DFLL_GCLK_SRC 3 |
GCLK Source used to generate DFLL48M. More... | |
#define | CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0 |
This is the master config for the core module for this mcu. This file is required for the core module to function.
Definition in file conf_core.h.
#define CONF_CORE_CLK_DFLL_ENABLE (1) |
Enables or Disables the DFLL48M Clock.
DFLL48M Enable
Definition at line 99 of file conf_core.h.
#define CONF_CORE_CLK_DFLL_GCLK_SRC 3 |
GCLK Source used to generate DFLL48M.
DFLL48M GCLK Source
Definition at line 154 of file conf_core.h.
#define CONF_CORE_CLK_DFLL_ONDEMAND (0) |
Enables or Disables on-demand operation.
DFLL48M On Demand Control
Definition at line 107 of file conf_core.h.
#define CONF_CORE_CLK_DFLL_RUNSTDBY (0) |
Enables or Disables run-in-standby operation.
DFLL48M Run in Standby Control
Definition at line 115 of file conf_core.h.
#define CONF_CORE_CLK_DFLL_WAITLOCK (0) |
This bit controls the DFLL output clock, depending on the lock status:
DFLL48M Wait Lock Control
Definition at line 124 of file conf_core.h.
#define CONF_CORE_CLK_DPLL0_FILTER 0x0 |
pg. 732 of the datasheet FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor 0x0 | 92.7 kHz | 0.76 0x1 | 131 kHz | 1.08 0x2 | 46.4 kHz | 0.38 0x3 | 65.6 kHz | 0.54 0x4 | 131 kHz | 0.56 0x5 | 185 kHz | 0.79 0x6 | 65.6 kHz | 0.28 0x7 | 92.7 kHz | 0.39 0x8 | 46.4 kHz | 1.49 0x9 | 65.6 kHz | 2.11 0xA | 23.2 kHz | 0.75 0xB | 32.8 kHz | 1.06 0xC | 65.6 kHz | 1.07 0xD | 92.7 kHz | 1.51 0xE | 32.8 kHz | 0.53 0xF | 46.4 kHz | 0.75
When in doubt, leave this at its default.
Definition at line 194 of file conf_core.h.
#define CONF_CORE_CLK_DPLL1_FILTER 0x0 |
pg. 732 of the datasheet
When in doubt, leave this at its default.
Definition at line 234 of file conf_core.h.
#define CONF_CORE_CMCC_ENABLE (0) |
Define whether the CMCC (Cortex-M Cache Controller) is enabled or not.
Definition at line 45 of file conf_core.h.
#define CONF_CORE_DMA_ENABLE (0) |
Define whether the DMAC is enabled or not.
Definition at line 38 of file conf_core.h.
#define CONF_CORE_MCLK_CPUDIV 0x1 |
Define the master clock divisor.
Definition at line 31 of file conf_core.h.
#define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5 |
Define the number of wait states for the master clock. Can be [0-15].
Definition at line 18 of file conf_core.h.