tc.h
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#ifndef _SAME54_TC_COMPONENT_
#define _SAME54_TC_COMPONENT_
/* ========================================================================== */
/* ========================================================================== */
#define TC_U2249
#define REV_TC 0x300
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1;
uint32_t ENABLE:1;
uint32_t MODE:2;
uint32_t PRESCSYNC:2;
uint32_t RUNSTDBY:1;
uint32_t ONDEMAND:1;
uint32_t PRESCALER:3;
uint32_t ALOCK:1;
uint32_t :4;
uint32_t CAPTEN0:1;
uint32_t CAPTEN1:1;
uint32_t :2;
uint32_t COPEN0:1;
uint32_t COPEN1:1;
uint32_t :2;
uint32_t CAPTMODE0:2;
uint32_t :1;
uint32_t CAPTMODE1:2;
uint32_t :3;
} bit;
struct {
uint32_t :16;
uint32_t CAPTEN:2;
uint32_t :2;
uint32_t COPEN:2;
uint32_t :10;
} vec;
uint32_t reg;
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLA_OFFSET 0x00
#define TC_CTRLA_RESETVALUE _U_(0x00000000)
#define TC_CTRLA_SWRST_Pos 0
#define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
#define TC_CTRLA_ENABLE_Pos 1
#define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
#define TC_CTRLA_MODE_Pos 2
#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0)
#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1)
#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2)
#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_PRESCSYNC_Pos 4
#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0)
#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1)
#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2)
#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_RUNSTDBY_Pos 6
#define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
#define TC_CTRLA_ONDEMAND_Pos 7
#define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
#define TC_CTRLA_PRESCALER_Pos 8
#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0)
#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1)
#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2)
#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3)
#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4)
#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5)
#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6)
#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7)
#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_ALOCK_Pos 11
#define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
#define TC_CTRLA_CAPTEN0_Pos 16
#define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
#define TC_CTRLA_CAPTEN1_Pos 17
#define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
#define TC_CTRLA_CAPTEN_Pos 16
#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
#define TC_CTRLA_COPEN0_Pos 20
#define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
#define TC_CTRLA_COPEN1_Pos 21
#define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
#define TC_CTRLA_COPEN_Pos 20
#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
#define TC_CTRLA_CAPTMODE0_Pos 24
#define TC_CTRLA_CAPTMODE0_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE0(value) (TC_CTRLA_CAPTMODE0_Msk & ((value) << TC_CTRLA_CAPTMODE0_Pos))
#define TC_CTRLA_CAPTMODE0_DEFAULT_Val _U_(0x0)
#define TC_CTRLA_CAPTMODE0_CAPTMIN_Val _U_(0x1)
#define TC_CTRLA_CAPTMODE0_CAPTMAX_Val _U_(0x2)
#define TC_CTRLA_CAPTMODE0_DEFAULT (TC_CTRLA_CAPTMODE0_DEFAULT_Val << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE0_CAPTMIN (TC_CTRLA_CAPTMODE0_CAPTMIN_Val << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE0_CAPTMAX (TC_CTRLA_CAPTMODE0_CAPTMAX_Val << TC_CTRLA_CAPTMODE0_Pos)
#define TC_CTRLA_CAPTMODE1_Pos 27
#define TC_CTRLA_CAPTMODE1_Msk (_U_(0x3) << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_CAPTMODE1(value) (TC_CTRLA_CAPTMODE1_Msk & ((value) << TC_CTRLA_CAPTMODE1_Pos))
#define TC_CTRLA_CAPTMODE1_DEFAULT_Val _U_(0x0)
#define TC_CTRLA_CAPTMODE1_CAPTMIN_Val _U_(0x1)
#define TC_CTRLA_CAPTMODE1_CAPTMAX_Val _U_(0x2)
#define TC_CTRLA_CAPTMODE1_DEFAULT (TC_CTRLA_CAPTMODE1_DEFAULT_Val << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_CAPTMODE1_CAPTMIN (TC_CTRLA_CAPTMODE1_CAPTMIN_Val << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_CAPTMODE1_CAPTMAX (TC_CTRLA_CAPTMODE1_CAPTMAX_Val << TC_CTRLA_CAPTMODE1_Pos)
#define TC_CTRLA_MASK _U_(0x1B330FFF)
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1;
uint8_t LUPD:1;
uint8_t ONESHOT:1;
uint8_t :2;
uint8_t CMD:3;
} bit;
uint8_t reg;
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBCLR_OFFSET 0x04
#define TC_CTRLBCLR_RESETVALUE _U_(0x00)
#define TC_CTRLBCLR_DIR_Pos 0
#define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
#define TC_CTRLBCLR_LUPD_Pos 1
#define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
#define TC_CTRLBCLR_ONESHOT_Pos 2
#define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
#define TC_CTRLBCLR_CMD_Pos 5
#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0)
#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1)
#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2)
#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3)
#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4)
#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5)
#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_MASK _U_(0xE7)
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1;
uint8_t LUPD:1;
uint8_t ONESHOT:1;
uint8_t :2;
uint8_t CMD:3;
} bit;
uint8_t reg;
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBSET_OFFSET 0x05
#define TC_CTRLBSET_RESETVALUE _U_(0x00)
#define TC_CTRLBSET_DIR_Pos 0
#define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
#define TC_CTRLBSET_LUPD_Pos 1
#define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
#define TC_CTRLBSET_ONESHOT_Pos 2
#define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
#define TC_CTRLBSET_CMD_Pos 5
#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0)
#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1)
#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2)
#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3)
#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4)
#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5)
#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_MASK _U_(0xE7)
/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t EVACT:3;
uint16_t :1;
uint16_t TCINV:1;
uint16_t TCEI:1;
uint16_t :2;
uint16_t OVFEO:1;
uint16_t :3;
uint16_t MCEO0:1;
uint16_t MCEO1:1;
uint16_t :2;
} bit;
struct {
uint16_t :12;
uint16_t MCEO:2;
uint16_t :2;
} vec;
uint16_t reg;
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_EVCTRL_OFFSET 0x06
#define TC_EVCTRL_RESETVALUE _U_(0x0000)
#define TC_EVCTRL_EVACT_Pos 0
#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0)
#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1)
#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2)
#define TC_EVCTRL_EVACT_START_Val _U_(0x3)
#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4)
#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5)
#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6)
#define TC_EVCTRL_EVACT_PW_Val _U_(0x7)
#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_TCINV_Pos 4
#define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
#define TC_EVCTRL_TCEI_Pos 5
#define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
#define TC_EVCTRL_OVFEO_Pos 8
#define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
#define TC_EVCTRL_MCEO0_Pos 12
#define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
#define TC_EVCTRL_MCEO1_Pos 13
#define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
#define TC_EVCTRL_MCEO_Pos 12
#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
#define TC_EVCTRL_MASK _U_(0x3137)
/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1;
uint8_t ERR:1;
uint8_t :2;
uint8_t MC0:1;
uint8_t MC1:1;
uint8_t :2;
} bit;
struct {
uint8_t :4;
uint8_t MC:2;
uint8_t :2;
} vec;
uint8_t reg;
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENCLR_OFFSET 0x08
#define TC_INTENCLR_RESETVALUE _U_(0x00)
#define TC_INTENCLR_OVF_Pos 0
#define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
#define TC_INTENCLR_ERR_Pos 1
#define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
#define TC_INTENCLR_MC0_Pos 4
#define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
#define TC_INTENCLR_MC1_Pos 5
#define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
#define TC_INTENCLR_MC_Pos 4
#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
#define TC_INTENCLR_MASK _U_(0x33)
/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1;
uint8_t ERR:1;
uint8_t :2;
uint8_t MC0:1;
uint8_t MC1:1;
uint8_t :2;
} bit;
struct {
uint8_t :4;
uint8_t MC:2;
uint8_t :2;
} vec;
uint8_t reg;
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENSET_OFFSET 0x09
#define TC_INTENSET_RESETVALUE _U_(0x00)
#define TC_INTENSET_OVF_Pos 0
#define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
#define TC_INTENSET_ERR_Pos 1
#define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
#define TC_INTENSET_MC0_Pos 4
#define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
#define TC_INTENSET_MC1_Pos 5
#define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
#define TC_INTENSET_MC_Pos 4
#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
#define TC_INTENSET_MASK _U_(0x33)
/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t OVF:1;
__I uint8_t ERR:1;
__I uint8_t :2;
__I uint8_t MC0:1;
__I uint8_t MC1:1;
__I uint8_t :2;
} bit;
struct {
__I uint8_t :4;
__I uint8_t MC:2;
__I uint8_t :2;
} vec;
uint8_t reg;
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTFLAG_OFFSET 0x0A
#define TC_INTFLAG_RESETVALUE _U_(0x00)
#define TC_INTFLAG_OVF_Pos 0
#define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
#define TC_INTFLAG_ERR_Pos 1
#define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
#define TC_INTFLAG_MC0_Pos 4
#define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
#define TC_INTFLAG_MC1_Pos 5
#define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
#define TC_INTFLAG_MC_Pos 4
#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
#define TC_INTFLAG_MASK _U_(0x33)
/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STOP:1;
uint8_t SLAVE:1;
uint8_t :1;
uint8_t PERBUFV:1;
uint8_t CCBUFV0:1;
uint8_t CCBUFV1:1;
uint8_t :2;
} bit;
struct {
uint8_t :4;
uint8_t CCBUFV:2;
uint8_t :2;
} vec;
uint8_t reg;
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_STATUS_OFFSET 0x0B
#define TC_STATUS_RESETVALUE _U_(0x01)
#define TC_STATUS_STOP_Pos 0
#define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
#define TC_STATUS_SLAVE_Pos 1
#define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
#define TC_STATUS_PERBUFV_Pos 3
#define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
#define TC_STATUS_CCBUFV0_Pos 4
#define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
#define TC_STATUS_CCBUFV1_Pos 5
#define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
#define TC_STATUS_CCBUFV_Pos 4
#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
#define TC_STATUS_MASK _U_(0x3B)
/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WAVEGEN:2;
uint8_t :6;
} bit;
uint8_t reg;
} TC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_WAVE_OFFSET 0x0C
#define TC_WAVE_RESETVALUE _U_(0x00)
#define TC_WAVE_WAVEGEN_Pos 0
#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0)
#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1)
#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2)
#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3)
#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_MASK _U_(0x03)
/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INVEN0:1;
uint8_t INVEN1:1;
uint8_t :6;
} bit;
struct {
uint8_t INVEN:2;
uint8_t :6;
} vec;
uint8_t reg;
} TC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_DRVCTRL_OFFSET 0x0D
#define TC_DRVCTRL_RESETVALUE _U_(0x00)
#define TC_DRVCTRL_INVEN0_Pos 0
#define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
#define TC_DRVCTRL_INVEN1_Pos 1
#define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
#define TC_DRVCTRL_INVEN_Pos 0
#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
#define TC_DRVCTRL_MASK _U_(0x03)
/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1;
uint8_t :7;
} bit;
uint8_t reg;
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_DBGCTRL_OFFSET 0x0F
#define TC_DBGCTRL_RESETVALUE _U_(0x00)
#define TC_DBGCTRL_DBGRUN_Pos 0
#define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
#define TC_DBGCTRL_MASK _U_(0x01)
/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1;
uint32_t ENABLE:1;
uint32_t CTRLB:1;
uint32_t STATUS:1;
uint32_t COUNT:1;
uint32_t PER:1;
uint32_t CC0:1;
uint32_t CC1:1;
uint32_t :24;
} bit;
struct {
uint32_t :6;
uint32_t CC:2;
uint32_t :24;
} vec;
uint32_t reg;
} TC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_SYNCBUSY_OFFSET 0x10
#define TC_SYNCBUSY_RESETVALUE _U_(0x00000000)
#define TC_SYNCBUSY_SWRST_Pos 0
#define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
#define TC_SYNCBUSY_ENABLE_Pos 1
#define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
#define TC_SYNCBUSY_CTRLB_Pos 2
#define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
#define TC_SYNCBUSY_STATUS_Pos 3
#define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
#define TC_SYNCBUSY_COUNT_Pos 4
#define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
#define TC_SYNCBUSY_PER_Pos 5
#define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
#define TC_SYNCBUSY_CC0_Pos 6
#define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
#define TC_SYNCBUSY_CC1_Pos 7
#define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
#define TC_SYNCBUSY_CC_Pos 6
#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
#define TC_SYNCBUSY_MASK _U_(0x000000FF)
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16;
} bit;
uint16_t reg;
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_COUNT_OFFSET 0x14
#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000)
#define TC_COUNT16_COUNT_COUNT_Pos 0
#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
#define TC_COUNT16_COUNT_MASK _U_(0xFFFF)
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32;
} bit;
uint32_t reg;
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_COUNT_OFFSET 0x14
#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000)
#define TC_COUNT32_COUNT_COUNT_Pos 0
#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
#define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF)
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COUNT:8;
} bit;
uint8_t reg;
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_COUNT_OFFSET 0x14
#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00)
#define TC_COUNT8_COUNT_COUNT_Pos 0
#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
#define TC_COUNT8_COUNT_MASK _U_(0xFF)
/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:8;
} bit;
uint8_t reg;
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_PER_OFFSET 0x1B
#define TC_COUNT8_PER_RESETVALUE _U_(0xFF)
#define TC_COUNT8_PER_PER_Pos 0
#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
#define TC_COUNT8_PER_MASK _U_(0xFF)
/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CC:16;
} bit;
uint16_t reg;
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_CC_OFFSET 0x1C
#define TC_COUNT16_CC_RESETVALUE _U_(0x0000)
#define TC_COUNT16_CC_CC_Pos 0
#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
#define TC_COUNT16_CC_MASK _U_(0xFFFF)
/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CC:32;
} bit;
uint32_t reg;
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_CC_OFFSET 0x1C
#define TC_COUNT32_CC_RESETVALUE _U_(0x00000000)
#define TC_COUNT32_CC_CC_Pos 0
#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
#define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF)
/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CC:8;
} bit;
uint8_t reg;
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_CC_OFFSET 0x1C
#define TC_COUNT8_CC_RESETVALUE _U_(0x00)
#define TC_COUNT8_CC_CC_Pos 0
#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
#define TC_COUNT8_CC_MASK _U_(0xFF)
/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PERBUF:8;
} bit;
uint8_t reg;
} TC_COUNT8_PERBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_PERBUF_OFFSET 0x2F
#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF)
#define TC_COUNT8_PERBUF_PERBUF_Pos 0
#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
#define TC_COUNT8_PERBUF_MASK _U_(0xFF)
/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CCBUF:16;
} bit;
uint16_t reg;
} TC_COUNT16_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_CCBUF_OFFSET 0x30
#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000)
#define TC_COUNT16_CCBUF_CCBUF_Pos 0
#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
#define TC_COUNT16_CCBUF_MASK _U_(0xFFFF)
/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CCBUF:32;
} bit;
uint32_t reg;
} TC_COUNT32_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_CCBUF_OFFSET 0x30
#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000)
#define TC_COUNT32_CCBUF_CCBUF_Pos 0
#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
#define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF)
/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CCBUF:8;
} bit;
uint8_t reg;
} TC_COUNT8_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_CCBUF_OFFSET 0x30
#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00)
#define TC_COUNT8_CCBUF_CCBUF_Pos 0
#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
#define TC_COUNT8_CCBUF_MASK _U_(0xFF)
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA;
__IO TC_CTRLBCLR_Type CTRLBCLR;
__IO TC_CTRLBSET_Type CTRLBSET;
__IO TC_EVCTRL_Type EVCTRL;
__IO TC_INTENCLR_Type INTENCLR;
__IO TC_INTENSET_Type INTENSET;
__IO TC_INTFLAG_Type INTFLAG;
__IO TC_STATUS_Type STATUS;
__IO TC_WAVE_Type WAVE;
__IO TC_DRVCTRL_Type DRVCTRL;
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL;
__I TC_SYNCBUSY_Type SYNCBUSY;
__IO TC_COUNT8_COUNT_Type COUNT;
RoReg8 Reserved2[0x6];
__IO TC_COUNT8_PER_Type PER;
__IO TC_COUNT8_CC_Type CC[2];
RoReg8 Reserved3[0x11];
__IO TC_COUNT8_PERBUF_Type PERBUF;
__IO TC_COUNT8_CCBUF_Type CCBUF[2];
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA;
__IO TC_CTRLBCLR_Type CTRLBCLR;
__IO TC_CTRLBSET_Type CTRLBSET;
__IO TC_EVCTRL_Type EVCTRL;
__IO TC_INTENCLR_Type INTENCLR;
__IO TC_INTENSET_Type INTENSET;
__IO TC_INTFLAG_Type INTFLAG;
__IO TC_STATUS_Type STATUS;
__IO TC_WAVE_Type WAVE;
__IO TC_DRVCTRL_Type DRVCTRL;
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL;
__I TC_SYNCBUSY_Type SYNCBUSY;
__IO TC_COUNT16_COUNT_Type COUNT;
RoReg8 Reserved2[0x6];
__IO TC_COUNT16_CC_Type CC[2];
RoReg8 Reserved3[0x10];
__IO TC_COUNT16_CCBUF_Type CCBUF[2];
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA;
__IO TC_CTRLBCLR_Type CTRLBCLR;
__IO TC_CTRLBSET_Type CTRLBSET;
__IO TC_EVCTRL_Type EVCTRL;
__IO TC_INTENCLR_Type INTENCLR;
__IO TC_INTENSET_Type INTENSET;
__IO TC_INTFLAG_Type INTFLAG;
__IO TC_STATUS_Type STATUS;
__IO TC_WAVE_Type WAVE;
__IO TC_DRVCTRL_Type DRVCTRL;
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL;
__I TC_SYNCBUSY_Type SYNCBUSY;
__IO TC_COUNT32_COUNT_Type COUNT;
RoReg8 Reserved2[0x4];
__IO TC_COUNT32_CC_Type CC[2];
RoReg8 Reserved3[0xC];
__IO TC_COUNT32_CCBUF_Type CCBUF[2];
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
TcCount8 COUNT8;
TcCount16 COUNT16;
TcCount32 COUNT32;
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME54_TC_COMPONENT_ */
TC_COUNT32_CCBUF_Type
Definition: tc.h:733
TC_STATUS_Type::CCBUFV1
uint8_t CCBUFV1
Definition: tc.h:419
TcCount32::COUNT
__IO TC_COUNT32_COUNT_Type COUNT
Offset: 0x14 (R/W 32) COUNT32 Count.
Definition: tc.h:833
TC_INTFLAG_Type::ERR
__I uint8_t ERR
Definition: tc.h:379
TC_COUNT16_COUNT_Type::reg
uint16_t reg
Definition: tc.h:575
TC_COUNT32_CC_Type
Definition: tc.h:661
TC_INTENSET_Type
Definition: tc.h:340
TC_CTRLBSET_Type::ONESHOT
uint8_t ONESHOT
Definition: tc.h:207
TcCount16::INTENCLR
__IO TC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear.
Definition: tc.h:800
Tc::COUNT16
TcCount16 COUNT16
Offset: 0x00 16-bit Counter Mode.
Definition: tc.h:844
TC_EVCTRL_Type
Definition: tc.h:243
TC_COUNT32_COUNT_Type::COUNT
uint32_t COUNT
Definition: tc.h:591
TcCount8::CTRLBCLR
__IO TC_CTRLBCLR_Type CTRLBCLR
Offset: 0x04 (R/W 8) Control B Clear.
Definition: tc.h:771
TC_INTENCLR_Type
Definition: tc.h:304
TC_EVCTRL_Type::OVFEO
uint16_t OVFEO
Definition: tc.h:250
TC_COUNT8_CC_Type::reg
uint8_t reg
Definition: tc.h:683
TcCount8::DRVCTRL
__IO TC_DRVCTRL_Type DRVCTRL
Offset: 0x0D (R/W 8) Control C.
Definition: tc.h:779
TcCount32::CTRLBCLR
__IO TC_CTRLBCLR_Type CTRLBCLR
Offset: 0x04 (R/W 8) Control B Clear.
Definition: tc.h:821
TC_EVCTRL_Type::TCEI
uint16_t TCEI
Definition: tc.h:248
TcCount8::INTENCLR
__IO TC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear.
Definition: tc.h:774
TC_CTRLBSET_Type::LUPD
uint8_t LUPD
Definition: tc.h:206
TC_CTRLA_Type::ENABLE
uint32_t ENABLE
Definition: tc.h:47
TC_SYNCBUSY_Type::SWRST
uint32_t SWRST
Definition: tc.h:526
TcCount8::STATUS
__IO TC_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status.
Definition: tc.h:777
TC_COUNT16_CC_Type::reg
uint16_t reg
Definition: tc.h:647
TC_COUNT8_CCBUF_Type::reg
uint8_t reg
Definition: tc.h:755
TC_CTRLBSET_Type::reg
uint8_t reg
Definition: tc.h:211
TC_STATUS_Type::SLAVE
uint8_t SLAVE
Definition: tc.h:415
TcCount32::CTRLA
__IO TC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
Definition: tc.h:820
TcCount16::SYNCBUSY
__I TC_SYNCBUSY_Type SYNCBUSY
Offset: 0x10 (R/ 32) Synchronization Status.
Definition: tc.h:808
TcCount16::CTRLA
__IO TC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
Definition: tc.h:796
TC_INTENCLR_Type::MC0
uint8_t MC0
Definition: tc.h:309
TC_STATUS_Type
Definition: tc.h:412
TC_INTENSET_Type::MC
uint8_t MC
Definition: tc.h:351
TC_INTENSET_Type::ERR
uint8_t ERR
Definition: tc.h:343
TC_CTRLBCLR_Type::LUPD
uint8_t LUPD
Definition: tc.h:166
TC_CTRLBCLR_Type::reg
uint8_t reg
Definition: tc.h:171
TC_CTRLA_Type::COPEN
uint32_t COPEN
Definition: tc.h:70
TC_COUNT16_CCBUF_Type::CCBUF
uint16_t CCBUF
Definition: tc.h:717
TcCount16::INTENSET
__IO TC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set.
Definition: tc.h:801
TC_SYNCBUSY_Type
Definition: tc.h:524
TC_SYNCBUSY_Type::CC0
uint32_t CC0
Definition: tc.h:532
TC_SYNCBUSY_Type::CC
uint32_t CC
Definition: tc.h:538
TC_COUNT16_CCBUF_Type::reg
uint16_t reg
Definition: tc.h:719
TC_STATUS_Type::CCBUFV
uint8_t CCBUFV
Definition: tc.h:424
TC_WAVE_Type
Definition: tc.h:451
TC_COUNT8_PER_Type
Definition: tc.h:625
TC_CTRLBCLR_Type::ONESHOT
uint8_t ONESHOT
Definition: tc.h:167
TC_SYNCBUSY_Type::ENABLE
uint32_t ENABLE
Definition: tc.h:527
TcCount8::CTRLBSET
__IO TC_CTRLBSET_Type CTRLBSET
Offset: 0x05 (R/W 8) Control B Set.
Definition: tc.h:772
TC_DRVCTRL_Type::reg
uint8_t reg
Definition: tc.h:488
TC_COUNT32_COUNT_Type::reg
uint32_t reg
Definition: tc.h:593
TC_CTRLA_Type::ALOCK
uint32_t ALOCK
Definition: tc.h:53
TC_COUNT8_COUNT_Type
Definition: tc.h:607
TcCount8::INTFLAG
__IO TC_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear.
Definition: tc.h:776
TC_CTRLA_Type::COPEN1
uint32_t COPEN1
Definition: tc.h:59
TC_CTRLA_Type::CAPTEN
uint32_t CAPTEN
Definition: tc.h:68
TC_COUNT32_CC_Type::CC
uint32_t CC
Definition: tc.h:663
TC_COUNT8_CC_Type
Definition: tc.h:679
TC_COUNT32_COUNT_Type
Definition: tc.h:589
TC_INTENSET_Type::reg
uint8_t reg
Definition: tc.h:354
TC_DRVCTRL_Type::INVEN
uint8_t INVEN
Definition: tc.h:485
TC_COUNT8_PER_Type::reg
uint8_t reg
Definition: tc.h:629
TC_COUNT32_CCBUF_Type::reg
uint32_t reg
Definition: tc.h:737
TC_CTRLA_Type::PRESCALER
uint32_t PRESCALER
Definition: tc.h:52
TcCount32::DBGCTRL
__IO TC_DBGCTRL_Type DBGCTRL
Offset: 0x0F (R/W 8) Debug Control.
Definition: tc.h:831
TC_COUNT8_PERBUF_Type::reg
uint8_t reg
Definition: tc.h:701
TC_CTRLA_Type
Definition: tc.h:44
TC_CTRLBCLR_Type::CMD
uint8_t CMD
Definition: tc.h:169
TC_DBGCTRL_Type::DBGRUN
uint8_t DBGRUN
Definition: tc.h:508
TC_INTENCLR_Type::MC1
uint8_t MC1
Definition: tc.h:310
Tc
Definition: tc.h:842
TC_STATUS_Type::PERBUFV
uint8_t PERBUFV
Definition: tc.h:417
TcCount16::STATUS
__IO TC_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status.
Definition: tc.h:803
TC_CTRLA_Type::COPEN0
uint32_t COPEN0
Definition: tc.h:58
TC_COUNT8_COUNT_Type::reg
uint8_t reg
Definition: tc.h:611
TC_INTFLAG_Type::MC
__I uint8_t MC
Definition: tc.h:387
Tc::COUNT8
TcCount8 COUNT8
Offset: 0x00 8-bit Counter Mode.
Definition: tc.h:843
TcCount8
TC_COUNT8 hardware registers.
Definition: tc.h:769
TC_CTRLA_Type::reg
uint32_t reg
Definition: tc.h:73
TC_WAVE_Type::WAVEGEN
uint8_t WAVEGEN
Definition: tc.h:453
TcCount32::SYNCBUSY
__I TC_SYNCBUSY_Type SYNCBUSY
Offset: 0x10 (R/ 32) Synchronization Status.
Definition: tc.h:832
TcCount16::CTRLBCLR
__IO TC_CTRLBCLR_Type CTRLBCLR
Offset: 0x04 (R/W 8) Control B Clear.
Definition: tc.h:797
TC_INTFLAG_Type::uint8_t
__I uint8_t
Definition: tc.h:380
Tc::COUNT32
TcCount32 COUNT32
Offset: 0x00 32-bit Counter Mode.
Definition: tc.h:845
TcCount32::INTENSET
__IO TC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set.
Definition: tc.h:825
TC_INTENCLR_Type::ERR
uint8_t ERR
Definition: tc.h:307
TC_EVCTRL_Type::reg
uint16_t reg
Definition: tc.h:261
TcCount16::EVCTRL
__IO TC_EVCTRL_Type EVCTRL
Offset: 0x06 (R/W 16) Event Control.
Definition: tc.h:799
TC_CTRLA_Type::RUNSTDBY
uint32_t RUNSTDBY
Definition: tc.h:50
TC_CTRLA_Type::SWRST
uint32_t SWRST
Definition: tc.h:46
TC_INTENSET_Type::MC0
uint8_t MC0
Definition: tc.h:345
TC_INTFLAG_Type::OVF
__I uint8_t OVF
Definition: tc.h:378
TC_CTRLBCLR_Type
Definition: tc.h:163
TC_DRVCTRL_Type
Definition: tc.h:478
TC_INTENSET_Type::MC1
uint8_t MC1
Definition: tc.h:346
TcCount8::DBGCTRL
__IO TC_DBGCTRL_Type DBGCTRL
Offset: 0x0F (R/W 8) Debug Control.
Definition: tc.h:781
TcCount16::COUNT
__IO TC_COUNT16_COUNT_Type COUNT
Offset: 0x14 (R/W 16) COUNT16 Count.
Definition: tc.h:809
TC_WAVE_Type::reg
uint8_t reg
Definition: tc.h:456
TC_INTENCLR_Type::reg
uint8_t reg
Definition: tc.h:318
TC_SYNCBUSY_Type::COUNT
uint32_t COUNT
Definition: tc.h:530
TcCount32
TC_COUNT32 hardware registers.
Definition: tc.h:819
TC_INTFLAG_Type::MC0
__I uint8_t MC0
Definition: tc.h:381
TC_EVCTRL_Type::TCINV
uint16_t TCINV
Definition: tc.h:247
TC_SYNCBUSY_Type::CC1
uint32_t CC1
Definition: tc.h:533
TcCount32::WAVE
__IO TC_WAVE_Type WAVE
Offset: 0x0C (R/W 8) Waveform Generation Control.
Definition: tc.h:828
TcCount16
TC_COUNT16 hardware registers.
Definition: tc.h:795
TC_EVCTRL_Type::MCEO0
uint16_t MCEO0
Definition: tc.h:252
TcCount16::WAVE
__IO TC_WAVE_Type WAVE
Offset: 0x0C (R/W 8) Waveform Generation Control.
Definition: tc.h:804
TcCount32::STATUS
__IO TC_STATUS_Type STATUS
Offset: 0x0B (R/W 8) Status.
Definition: tc.h:827
TC_DBGCTRL_Type
Definition: tc.h:506
TC_COUNT8_PER_Type::PER
uint8_t PER
Definition: tc.h:627
TC_INTFLAG_Type
Definition: tc.h:376
TcCount8::INTENSET
__IO TC_INTENSET_Type INTENSET
Offset: 0x09 (R/W 8) Interrupt Enable Set.
Definition: tc.h:775
TC_CTRLA_Type::PRESCSYNC
uint32_t PRESCSYNC
Definition: tc.h:49
TC_CTRLA_Type::MODE
uint32_t MODE
Definition: tc.h:48
TcCount8::PER
__IO TC_COUNT8_PER_Type PER
Offset: 0x1B (R/W 8) COUNT8 Period.
Definition: tc.h:785
TcCount32::CTRLBSET
__IO TC_CTRLBSET_Type CTRLBSET
Offset: 0x05 (R/W 8) Control B Set.
Definition: tc.h:822
TC_COUNT32_CCBUF_Type::CCBUF
uint32_t CCBUF
Definition: tc.h:735
TC_CTRLBSET_Type
Definition: tc.h:203
TC_INTENSET_Type::OVF
uint8_t OVF
Definition: tc.h:342
TcCount8::PERBUF
__IO TC_COUNT8_PERBUF_Type PERBUF
Offset: 0x2F (R/W 8) COUNT8 Period Buffer.
Definition: tc.h:788
TC_COUNT8_PERBUF_Type
Definition: tc.h:697
TcCount8::WAVE
__IO TC_WAVE_Type WAVE
Offset: 0x0C (R/W 8) Waveform Generation Control.
Definition: tc.h:778
TC_CTRLBCLR_Type::DIR
uint8_t DIR
Definition: tc.h:165
TcCount32::DRVCTRL
__IO TC_DRVCTRL_Type DRVCTRL
Offset: 0x0D (R/W 8) Control C.
Definition: tc.h:829
TcCount8::CTRLA
__IO TC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 32) Control A.
Definition: tc.h:770
TC_COUNT16_CC_Type::CC
uint16_t CC
Definition: tc.h:645
TC_CTRLA_Type::CAPTMODE1
uint32_t CAPTMODE1
Definition: tc.h:63
TC_SYNCBUSY_Type::reg
uint32_t reg
Definition: tc.h:541
TC_DBGCTRL_Type::reg
uint8_t reg
Definition: tc.h:511
TC_COUNT8_CCBUF_Type::CCBUF
uint8_t CCBUF
Definition: tc.h:753
TC_STATUS_Type::CCBUFV0
uint8_t CCBUFV0
Definition: tc.h:418
TcCount32::EVCTRL
__IO TC_EVCTRL_Type EVCTRL
Offset: 0x06 (R/W 16) Event Control.
Definition: tc.h:823
TC_CTRLA_Type::CAPTEN0
uint32_t CAPTEN0
Definition: tc.h:55
TC_EVCTRL_Type::MCEO1
uint16_t MCEO1
Definition: tc.h:253
TcCount8::SYNCBUSY
__I TC_SYNCBUSY_Type SYNCBUSY
Offset: 0x10 (R/ 32) Synchronization Status.
Definition: tc.h:782
TcCount16::DRVCTRL
__IO TC_DRVCTRL_Type DRVCTRL
Offset: 0x0D (R/W 8) Control C.
Definition: tc.h:805
TC_COUNT16_CCBUF_Type
Definition: tc.h:715
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
TC_SYNCBUSY_Type::CTRLB
uint32_t CTRLB
Definition: tc.h:528
TcCount8::COUNT
__IO TC_COUNT8_COUNT_Type COUNT
Offset: 0x14 (R/W 8) COUNT8 Count.
Definition: tc.h:783
TC_COUNT16_COUNT_Type::COUNT
uint16_t COUNT
Definition: tc.h:573
TC_COUNT16_CC_Type
Definition: tc.h:643
TC_INTFLAG_Type::reg
uint8_t reg
Definition: tc.h:390
TC_COUNT8_CC_Type::CC
uint8_t CC
Definition: tc.h:681
TC_EVCTRL_Type::MCEO
uint16_t MCEO
Definition: tc.h:258
TC_CTRLBSET_Type::DIR
uint8_t DIR
Definition: tc.h:205
TC_CTRLBSET_Type::CMD
uint8_t CMD
Definition: tc.h:209
TC_COUNT8_CCBUF_Type
Definition: tc.h:751
TC_COUNT8_COUNT_Type::COUNT
uint8_t COUNT
Definition: tc.h:609
TC_INTENCLR_Type::MC
uint8_t MC
Definition: tc.h:315
TC_CTRLA_Type::CAPTMODE0
uint32_t CAPTMODE0
Definition: tc.h:61
TC_SYNCBUSY_Type::STATUS
uint32_t STATUS
Definition: tc.h:529
TC_SYNCBUSY_Type::PER
uint32_t PER
Definition: tc.h:531
TcCount16::DBGCTRL
__IO TC_DBGCTRL_Type DBGCTRL
Offset: 0x0F (R/W 8) Debug Control.
Definition: tc.h:807
TcCount16::CTRLBSET
__IO TC_CTRLBSET_Type CTRLBSET
Offset: 0x05 (R/W 8) Control B Set.
Definition: tc.h:798
TcCount32::INTENCLR
__IO TC_INTENCLR_Type INTENCLR
Offset: 0x08 (R/W 8) Interrupt Enable Clear.
Definition: tc.h:824
TC_COUNT8_PERBUF_Type::PERBUF
uint8_t PERBUF
Definition: tc.h:699
TC_CTRLA_Type::CAPTEN1
uint32_t CAPTEN1
Definition: tc.h:56
TC_INTFLAG_Type::MC1
__I uint8_t MC1
Definition: tc.h:382
TC_DRVCTRL_Type::INVEN0
uint8_t INVEN0
Definition: tc.h:480
TC_INTENCLR_Type::OVF
uint8_t OVF
Definition: tc.h:306
TC_COUNT32_CC_Type::reg
uint32_t reg
Definition: tc.h:665
TC_STATUS_Type::STOP
uint8_t STOP
Definition: tc.h:414
TC_DRVCTRL_Type::INVEN1
uint8_t INVEN1
Definition: tc.h:481
TC_STATUS_Type::reg
uint8_t reg
Definition: tc.h:427
TC_EVCTRL_Type::EVACT
uint16_t EVACT
Definition: tc.h:245
TcCount16::INTFLAG
__IO TC_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear.
Definition: tc.h:802
TcCount8::EVCTRL
__IO TC_EVCTRL_Type EVCTRL
Offset: 0x06 (R/W 16) Event Control.
Definition: tc.h:773
TcCount32::INTFLAG
__IO TC_INTFLAG_Type INTFLAG
Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear.
Definition: tc.h:826
TC_COUNT16_COUNT_Type
Definition: tc.h:571
TC_CTRLA_Type::ONDEMAND
uint32_t ONDEMAND
Definition: tc.h:51