same54p19a.h
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#ifndef _SAME54P19A_
#define _SAME54P19A_
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg;
typedef volatile const uint16_t RoReg16;
typedef volatile const uint8_t RoReg8;
#else
typedef volatile uint32_t RoReg;
typedef volatile uint16_t RoReg16;
typedef volatile uint8_t RoReg8;
#endif
typedef volatile uint32_t WoReg;
typedef volatile uint16_t WoReg16;
typedef volatile uint8_t WoReg8;
typedef volatile uint32_t RwReg;
typedef volatile uint16_t RwReg16;
typedef volatile uint8_t RwReg8;
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U
#define _L_(x) x ## L
#define _UL_(x) x ## UL
#else /* Assembler */
#define _U_(x) x
#define _L_(x) x
#define _UL_(x) x
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/* ************************************************************************** */
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
/****** SAME54P19A-specific Interrupt Numbers *********************/
PM_IRQn = 0,
MCLK_IRQn = 1,
OSCCTRL_0_IRQn = 2,
OSCCTRL_1_IRQn = 3,
OSCCTRL_2_IRQn = 4,
OSCCTRL_3_IRQn = 5,
OSCCTRL_4_IRQn = 6,
OSC32KCTRL_IRQn = 7,
SUPC_0_IRQn = 8,
SUPC_1_IRQn = 9,
WDT_IRQn = 10,
RTC_IRQn = 11,
EIC_0_IRQn = 12,
EIC_1_IRQn = 13,
EIC_2_IRQn = 14,
EIC_3_IRQn = 15,
EIC_4_IRQn = 16,
EIC_5_IRQn = 17,
EIC_6_IRQn = 18,
EIC_7_IRQn = 19,
EIC_8_IRQn = 20,
EIC_9_IRQn = 21,
EIC_10_IRQn = 22,
EIC_11_IRQn = 23,
EIC_12_IRQn = 24,
EIC_13_IRQn = 25,
EIC_14_IRQn = 26,
EIC_15_IRQn = 27,
FREQM_IRQn = 28,
NVMCTRL_0_IRQn = 29,
NVMCTRL_1_IRQn = 30,
DMAC_0_IRQn = 31,
DMAC_1_IRQn = 32,
DMAC_2_IRQn = 33,
DMAC_3_IRQn = 34,
DMAC_4_IRQn = 35,
EVSYS_0_IRQn = 36,
EVSYS_1_IRQn = 37,
EVSYS_2_IRQn = 38,
EVSYS_3_IRQn = 39,
EVSYS_4_IRQn = 40,
PAC_IRQn = 41,
RAMECC_IRQn = 45,
SERCOM0_0_IRQn = 46,
SERCOM0_1_IRQn = 47,
SERCOM0_2_IRQn = 48,
SERCOM0_3_IRQn = 49,
SERCOM1_0_IRQn = 50,
SERCOM1_1_IRQn = 51,
SERCOM1_2_IRQn = 52,
SERCOM1_3_IRQn = 53,
SERCOM2_0_IRQn = 54,
SERCOM2_1_IRQn = 55,
SERCOM2_2_IRQn = 56,
SERCOM2_3_IRQn = 57,
SERCOM3_0_IRQn = 58,
SERCOM3_1_IRQn = 59,
SERCOM3_2_IRQn = 60,
SERCOM3_3_IRQn = 61,
SERCOM4_0_IRQn = 62,
SERCOM4_1_IRQn = 63,
SERCOM4_2_IRQn = 64,
SERCOM4_3_IRQn = 65,
SERCOM5_0_IRQn = 66,
SERCOM5_1_IRQn = 67,
SERCOM5_2_IRQn = 68,
SERCOM5_3_IRQn = 69,
SERCOM6_0_IRQn = 70,
SERCOM6_1_IRQn = 71,
SERCOM6_2_IRQn = 72,
SERCOM6_3_IRQn = 73,
SERCOM7_0_IRQn = 74,
SERCOM7_1_IRQn = 75,
SERCOM7_2_IRQn = 76,
SERCOM7_3_IRQn = 77,
CAN0_IRQn = 78,
CAN1_IRQn = 79,
USB_0_IRQn = 80,
USB_1_IRQn = 81,
USB_2_IRQn = 82,
USB_3_IRQn = 83,
GMAC_IRQn = 84,
TCC0_0_IRQn = 85,
TCC0_1_IRQn = 86,
TCC0_2_IRQn = 87,
TCC0_3_IRQn = 88,
TCC0_4_IRQn = 89,
TCC0_5_IRQn = 90,
TCC0_6_IRQn = 91,
TCC1_0_IRQn = 92,
TCC1_1_IRQn = 93,
TCC1_2_IRQn = 94,
TCC1_3_IRQn = 95,
TCC1_4_IRQn = 96,
TCC2_0_IRQn = 97,
TCC2_1_IRQn = 98,
TCC2_2_IRQn = 99,
TCC2_3_IRQn = 100,
TCC3_0_IRQn = 101,
TCC3_1_IRQn = 102,
TCC3_2_IRQn = 103,
TCC4_0_IRQn = 104,
TCC4_1_IRQn = 105,
TCC4_2_IRQn = 106,
TC0_IRQn = 107,
TC1_IRQn = 108,
TC2_IRQn = 109,
TC3_IRQn = 110,
TC4_IRQn = 111,
TC5_IRQn = 112,
TC6_IRQn = 113,
TC7_IRQn = 114,
PDEC_0_IRQn = 115,
PDEC_1_IRQn = 116,
PDEC_2_IRQn = 117,
ADC0_0_IRQn = 118,
ADC0_1_IRQn = 119,
ADC1_0_IRQn = 120,
ADC1_1_IRQn = 121,
AC_IRQn = 122,
DAC_0_IRQn = 123,
DAC_1_IRQn = 124,
DAC_2_IRQn = 125,
DAC_3_IRQn = 126,
DAC_4_IRQn = 127,
I2S_IRQn = 128,
PCC_IRQn = 129,
AES_IRQn = 130,
TRNG_IRQn = 131,
ICM_IRQn = 132,
PUKCC_IRQn = 133,
QSPI_IRQn = 134,
SDHC0_IRQn = 135,
SDHC1_IRQn = 136,
PERIPH_COUNT_IRQn = 137
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pfnMemManagement_Handler;
void* pfnBusFault_Handler;
void* pfnUsageFault_Handler;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pfnDebugMonitor_Handler;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnMCLK_Handler; /* 1 Main Clock */
void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
void* pfnWDT_Handler; /* 10 Watchdog Timer */
void* pfnRTC_Handler; /* 11 Real-Time Counter */
void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
void* pfnFREQM_Handler; /* 28 Frequency Meter */
void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
void* pvReserved42;
void* pvReserved43;
void* pvReserved44;
void* pfnRAMECC_Handler; /* 45 RAM ECC */
void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */
void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */
void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */
void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */
void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */
void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */
void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */
void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */
void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
void* pfnCAN1_Handler; /* 79 Control Area Network 1 */
void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
void* pfnGMAC_Handler; /* 84 Ethernet MAC */
void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */
void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
void* pfnAC_Handler; /* 122 Analog Comparators */
void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
void* pfnTRNG_Handler; /* 131 True Random Generator */
void* pfnICM_Handler; /* 132 Integrity Check Monitor */
void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
void* pfnQSPI_Handler; /* 134 Quad SPI interface */
void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */
} DeviceVectors;
/* Cortex-M4 processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void MemManagement_Handler ( void );
void BusFault_Handler ( void );
void UsageFault_Handler ( void );
void SVCall_Handler ( void );
void DebugMonitor_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void PM_Handler ( void );
void MCLK_Handler ( void );
void OSCCTRL_0_Handler ( void );
void OSCCTRL_1_Handler ( void );
void OSCCTRL_2_Handler ( void );
void OSCCTRL_3_Handler ( void );
void OSCCTRL_4_Handler ( void );
void OSC32KCTRL_Handler ( void );
void SUPC_0_Handler ( void );
void SUPC_1_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_0_Handler ( void );
void EIC_1_Handler ( void );
void EIC_2_Handler ( void );
void EIC_3_Handler ( void );
void EIC_4_Handler ( void );
void EIC_5_Handler ( void );
void EIC_6_Handler ( void );
void EIC_7_Handler ( void );
void EIC_8_Handler ( void );
void EIC_9_Handler ( void );
void EIC_10_Handler ( void );
void EIC_11_Handler ( void );
void EIC_12_Handler ( void );
void EIC_13_Handler ( void );
void EIC_14_Handler ( void );
void EIC_15_Handler ( void );
void FREQM_Handler ( void );
void NVMCTRL_0_Handler ( void );
void NVMCTRL_1_Handler ( void );
void DMAC_0_Handler ( void );
void DMAC_1_Handler ( void );
void DMAC_2_Handler ( void );
void DMAC_3_Handler ( void );
void DMAC_4_Handler ( void );
void EVSYS_0_Handler ( void );
void EVSYS_1_Handler ( void );
void EVSYS_2_Handler ( void );
void EVSYS_3_Handler ( void );
void EVSYS_4_Handler ( void );
void PAC_Handler ( void );
void RAMECC_Handler ( void );
void SERCOM0_0_Handler ( void );
void SERCOM0_1_Handler ( void );
void SERCOM0_2_Handler ( void );
void SERCOM0_3_Handler ( void );
void SERCOM1_0_Handler ( void );
void SERCOM1_1_Handler ( void );
void SERCOM1_2_Handler ( void );
void SERCOM1_3_Handler ( void );
void SERCOM2_0_Handler ( void );
void SERCOM2_1_Handler ( void );
void SERCOM2_2_Handler ( void );
void SERCOM2_3_Handler ( void );
void SERCOM3_0_Handler ( void );
void SERCOM3_1_Handler ( void );
void SERCOM3_2_Handler ( void );
void SERCOM3_3_Handler ( void );
void SERCOM4_0_Handler ( void );
void SERCOM4_1_Handler ( void );
void SERCOM4_2_Handler ( void );
void SERCOM4_3_Handler ( void );
void SERCOM5_0_Handler ( void );
void SERCOM5_1_Handler ( void );
void SERCOM5_2_Handler ( void );
void SERCOM5_3_Handler ( void );
void SERCOM6_0_Handler ( void );
void SERCOM6_1_Handler ( void );
void SERCOM6_2_Handler ( void );
void SERCOM6_3_Handler ( void );
void SERCOM7_0_Handler ( void );
void SERCOM7_1_Handler ( void );
void SERCOM7_2_Handler ( void );
void SERCOM7_3_Handler ( void );
void CAN0_Handler ( void );
void CAN1_Handler ( void );
void USB_0_Handler ( void );
void USB_1_Handler ( void );
void USB_2_Handler ( void );
void USB_3_Handler ( void );
void GMAC_Handler ( void );
void TCC0_0_Handler ( void );
void TCC0_1_Handler ( void );
void TCC0_2_Handler ( void );
void TCC0_3_Handler ( void );
void TCC0_4_Handler ( void );
void TCC0_5_Handler ( void );
void TCC0_6_Handler ( void );
void TCC1_0_Handler ( void );
void TCC1_1_Handler ( void );
void TCC1_2_Handler ( void );
void TCC1_3_Handler ( void );
void TCC1_4_Handler ( void );
void TCC2_0_Handler ( void );
void TCC2_1_Handler ( void );
void TCC2_2_Handler ( void );
void TCC2_3_Handler ( void );
void TCC3_0_Handler ( void );
void TCC3_1_Handler ( void );
void TCC3_2_Handler ( void );
void TCC4_0_Handler ( void );
void TCC4_1_Handler ( void );
void TCC4_2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void TC5_Handler ( void );
void TC6_Handler ( void );
void TC7_Handler ( void );
void PDEC_0_Handler ( void );
void PDEC_1_Handler ( void );
void PDEC_2_Handler ( void );
void ADC0_0_Handler ( void );
void ADC0_1_Handler ( void );
void ADC1_0_Handler ( void );
void ADC1_1_Handler ( void );
void AC_Handler ( void );
void DAC_0_Handler ( void );
void DAC_1_Handler ( void );
void DAC_2_Handler ( void );
void DAC_3_Handler ( void );
void DAC_4_Handler ( void );
void I2S_Handler ( void );
void PCC_Handler ( void );
void AES_Handler ( void );
void TRNG_Handler ( void );
void ICM_Handler ( void );
void PUKCC_Handler ( void );
void QSPI_Handler ( void );
void SDHC0_Handler ( void );
void SDHC1_Handler ( void );
/*
* \brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 1
#define __DEBUG_LVL 3
#define __FPU_PRESENT 1
#define __MPU_PRESENT 1
#define __NVIC_PRIO_BITS 3
#define __TRACE_LVL 2
#define __VTOR_PRESENT 1
#define __Vendor_SysTickConfig 0
#include <core_cm4.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_same54.h"
#endif /* DONT_USE_CMSIS_INIT */
/* ************************************************************************** */
/* ************************************************************************** */
#include "component/ac.h"
#include "component/adc.h"
#include "component/aes.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/cmcc.h"
#include "component/dac.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/gmac.h"
#include "component/hmatrixb.h"
#include "component/icm.h"
#include "component/i2s.h"
#include "component/mclk.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pcc.h"
#include "component/pdec.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/qspi.h"
#include "component/ramecc.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdhc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/trng.h"
#include "component/usb.h"
#include "component/wdt.h"
/* ************************************************************************** */
/* ************************************************************************** */
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/aes.h"
#include "instance/can0.h"
#include "instance/can1.h"
#include "instance/ccl.h"
#include "instance/cmcc.h"
#include "instance/dac.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/gmac.h"
#include "instance/hmatrix.h"
#include "instance/icm.h"
#include "instance/i2s.h"
#include "instance/mclk.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pcc.h"
#include "instance/pdec.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/pukcc.h"
#include "instance/qspi.h"
#include "instance/ramecc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdhc0.h"
#include "instance/sdhc1.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/sercom4.h"
#include "instance/sercom5.h"
#include "instance/sercom6.h"
#include "instance/sercom7.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tc5.h"
#include "instance/tc6.h"
#include "instance/tc7.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tcc3.h"
#include "instance/tcc4.h"
#include "instance/trng.h"
#include "instance/usb.h"
#include "instance/wdt.h"
/* ************************************************************************** */
/* ************************************************************************** */
// Peripheral instances on HPB0 bridge
#define ID_PAC 0
#define ID_PM 1
#define ID_MCLK 2
#define ID_RSTC 3
#define ID_OSCCTRL 4
#define ID_OSC32KCTRL 5
#define ID_SUPC 6
#define ID_GCLK 7
#define ID_WDT 8
#define ID_RTC 9
#define ID_EIC 10
#define ID_FREQM 11
#define ID_SERCOM0 12
#define ID_SERCOM1 13
#define ID_TC0 14
#define ID_TC1 15
// Peripheral instances on HPB1 bridge
#define ID_USB 32
#define ID_DSU 33
#define ID_NVMCTRL 34
#define ID_CMCC 35
#define ID_PORT 36
#define ID_DMAC 37
#define ID_HMATRIX 38
#define ID_EVSYS 39
#define ID_SERCOM2 41
#define ID_SERCOM3 42
#define ID_TCC0 43
#define ID_TCC1 44
#define ID_TC2 45
#define ID_TC3 46
#define ID_RAMECC 48
// Peripheral instances on HPB2 bridge
#define ID_CAN0 64
#define ID_CAN1 65
#define ID_GMAC 66
#define ID_TCC2 67
#define ID_TCC3 68
#define ID_TC4 69
#define ID_TC5 70
#define ID_PDEC 71
#define ID_AC 72
#define ID_AES 73
#define ID_TRNG 74
#define ID_ICM 75
#define ID_PUKCC 76
#define ID_QSPI 77
#define ID_CCL 78
// Peripheral instances on HPB3 bridge
#define ID_SERCOM4 96
#define ID_SERCOM5 97
#define ID_SERCOM6 98
#define ID_SERCOM7 99
#define ID_TCC4 100
#define ID_TC6 101
#define ID_TC7 102
#define ID_ADC0 103
#define ID_ADC1 104
#define ID_DAC 105
#define ID_I2S 106
#define ID_PCC 107
// Peripheral instances on AHB (as if on bridge 4)
#define ID_SDHC0 128
#define ID_SDHC1 129
#define ID_PERIPH_COUNT 130
/* ************************************************************************** */
/* ************************************************************************** */
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42002000)
#define ADC0 (0x43001C00)
#define ADC1 (0x43002000)
#define AES (0x42002400)
#define CAN0 (0x42000000)
#define CAN1 (0x42000400)
#define CCL (0x42003800)
#define CMCC (0x41006000)
#define CMCC_AHB (0x03000000)
#define DAC (0x43002400)
#define DMAC (0x4100A000)
#define DSU (0x41002000)
#define EIC (0x40002800)
#define EVSYS (0x4100E000)
#define FREQM (0x40002C00)
#define GCLK (0x40001C00)
#define GMAC (0x42000800)
#define HMATRIX (0x4100C000)
#define ICM (0x42002C00)
#define I2S (0x43002800)
#define MCLK (0x40000800)
#define NVMCTRL (0x41004000)
#define NVMCTRL_SW0 (0x00800080)
#define NVMCTRL_TEMP_LOG (0x00800100)
#define NVMCTRL_USER (0x00804000)
#define OSCCTRL (0x40001000)
#define OSC32KCTRL (0x40001400)
#define PAC (0x40000000)
#define PCC (0x43002C00)
#define PDEC (0x42001C00)
#define PM (0x40000400)
#define PORT (0x41008000)
#define PUKCC (0x42003000)
#define PUKCC_AHB (0x02000000)
#define QSPI (0x42003400)
#define QSPI_AHB (0x04000000)
#define RAMECC (0x41020000)
#define RSTC (0x40000C00)
#define RTC (0x40002400)
#define SDHC0 (0x45000000)
#define SDHC1 (0x46000000)
#define SERCOM0 (0x40003000)
#define SERCOM1 (0x40003400)
#define SERCOM2 (0x41012000)
#define SERCOM3 (0x41014000)
#define SERCOM4 (0x43000000)
#define SERCOM5 (0x43000400)
#define SERCOM6 (0x43000800)
#define SERCOM7 (0x43000C00)
#define SUPC (0x40001800)
#define TC0 (0x40003800)
#define TC1 (0x40003C00)
#define TC2 (0x4101A000)
#define TC3 (0x4101C000)
#define TC4 (0x42001400)
#define TC5 (0x42001800)
#define TC6 (0x43001400)
#define TC7 (0x43001800)
#define TCC0 (0x41016000)
#define TCC1 (0x41018000)
#define TCC2 (0x42000C00)
#define TCC3 (0x42001000)
#define TCC4 (0x43001000)
#define TRNG (0x42002800)
#define USB (0x41000000)
#define WDT (0x40002000)
#else
#define AC ((Ac *)0x42002000UL)
#define AC_INST_NUM 1
#define AC_INSTS { AC }
#define ADC0 ((Adc *)0x43001C00UL)
#define ADC1 ((Adc *)0x43002000UL)
#define ADC_INST_NUM 2
#define ADC_INSTS { ADC0, ADC1 }
#define AES ((Aes *)0x42002400UL)
#define AES_INST_NUM 1
#define AES_INSTS { AES }
#define CAN0 ((Can *)0x42000000UL)
#define CAN1 ((Can *)0x42000400UL)
#define CAN_INST_NUM 2
#define CAN_INSTS { CAN0, CAN1 }
#define CCL ((Ccl *)0x42003800UL)
#define CCL_INST_NUM 1
#define CCL_INSTS { CCL }
#define CMCC ((Cmcc *)0x41006000UL)
#define CMCC_AHB (0x03000000UL)
#define CMCC_INST_NUM 1
#define CMCC_INSTS { CMCC }
#define DAC ((Dac *)0x43002400UL)
#define DAC_INST_NUM 1
#define DAC_INSTS { DAC }
#define DMAC ((Dmac *)0x4100A000UL)
#define DMAC_INST_NUM 1
#define DMAC_INSTS { DMAC }
#define DSU ((Dsu *)0x41002000UL)
#define DSU_INST_NUM 1
#define DSU_INSTS { DSU }
#define EIC ((Eic *)0x40002800UL)
#define EIC_INST_NUM 1
#define EIC_INSTS { EIC }
#define EVSYS ((Evsys *)0x4100E000UL)
#define EVSYS_INST_NUM 1
#define EVSYS_INSTS { EVSYS }
#define FREQM ((Freqm *)0x40002C00UL)
#define FREQM_INST_NUM 1
#define FREQM_INSTS { FREQM }
#define GCLK ((Gclk *)0x40001C00UL)
#define GCLK_INST_NUM 1
#define GCLK_INSTS { GCLK }
#define GMAC ((Gmac *)0x42000800UL)
#define GMAC_INST_NUM 1
#define GMAC_INSTS { GMAC }
#define HMATRIX ((Hmatrixb *)0x4100C000UL)
#define HMATRIXB_INST_NUM 1
#define HMATRIXB_INSTS { HMATRIX }
#define ICM ((Icm *)0x42002C00UL)
#define ICM_INST_NUM 1
#define ICM_INSTS { ICM }
#define I2S ((I2s *)0x43002800UL)
#define I2S_INST_NUM 1
#define I2S_INSTS { I2S }
#define MCLK ((Mclk *)0x40000800UL)
#define MCLK_INST_NUM 1
#define MCLK_INSTS { MCLK }
#define NVMCTRL ((Nvmctrl *)0x41004000UL)
#define NVMCTRL_SW0 (0x00800080UL)
#define NVMCTRL_TEMP_LOG (0x00800100UL)
#define NVMCTRL_USER (0x00804000UL)
#define NVMCTRL_INST_NUM 1
#define NVMCTRL_INSTS { NVMCTRL }
#define OSCCTRL ((Oscctrl *)0x40001000UL)
#define OSCCTRL_INST_NUM 1
#define OSCCTRL_INSTS { OSCCTRL }
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL)
#define OSC32KCTRL_INST_NUM 1
#define OSC32KCTRL_INSTS { OSC32KCTRL }
#define PAC ((Pac *)0x40000000UL)
#define PAC_INST_NUM 1
#define PAC_INSTS { PAC }
#define PCC ((Pcc *)0x43002C00UL)
#define PCC_INST_NUM 1
#define PCC_INSTS { PCC }
#define PDEC ((Pdec *)0x42001C00UL)
#define PDEC_INST_NUM 1
#define PDEC_INSTS { PDEC }
#define PM ((Pm *)0x40000400UL)
#define PM_INST_NUM 1
#define PM_INSTS { PM }
#define PORT ((Port *)0x41008000UL)
#define PORT_INST_NUM 1
#define PORT_INSTS { PORT }
#define PUKCC ((void *)0x42003000UL)
#define PUKCC_AHB ((void *)0x02000000UL)
#define PUKCC_INST_NUM 1
#define PUKCC_INSTS { PUKCC }
#define QSPI ((Qspi *)0x42003400UL)
#define QSPI_AHB (0x04000000UL)
#define QSPI_INST_NUM 1
#define QSPI_INSTS { QSPI }
#define RAMECC ((Ramecc *)0x41020000UL)
#define RAMECC_INST_NUM 1
#define RAMECC_INSTS { RAMECC }
#define RSTC ((Rstc *)0x40000C00UL)
#define RSTC_INST_NUM 1
#define RSTC_INSTS { RSTC }
#define RTC ((Rtc *)0x40002400UL)
#define RTC_INST_NUM 1
#define RTC_INSTS { RTC }
#define SDHC0 ((Sdhc *)0x45000000UL)
#define SDHC1 ((Sdhc *)0x46000000UL)
#define SDHC_INST_NUM 2
#define SDHC_INSTS { SDHC0, SDHC1 }
#define SERCOM0 ((Sercom *)0x40003000UL)
#define SERCOM1 ((Sercom *)0x40003400UL)
#define SERCOM2 ((Sercom *)0x41012000UL)
#define SERCOM3 ((Sercom *)0x41014000UL)
#define SERCOM4 ((Sercom *)0x43000000UL)
#define SERCOM5 ((Sercom *)0x43000400UL)
#define SERCOM6 ((Sercom *)0x43000800UL)
#define SERCOM7 ((Sercom *)0x43000C00UL)
#define SERCOM_INST_NUM 8
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 }
#define SUPC ((Supc *)0x40001800UL)
#define SUPC_INST_NUM 1
#define SUPC_INSTS { SUPC }
#define TC0 ((Tc *)0x40003800UL)
#define TC1 ((Tc *)0x40003C00UL)
#define TC2 ((Tc *)0x4101A000UL)
#define TC3 ((Tc *)0x4101C000UL)
#define TC4 ((Tc *)0x42001400UL)
#define TC5 ((Tc *)0x42001800UL)
#define TC6 ((Tc *)0x43001400UL)
#define TC7 ((Tc *)0x43001800UL)
#define TC_INST_NUM 8
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 }
#define TCC0 ((Tcc *)0x41016000UL)
#define TCC1 ((Tcc *)0x41018000UL)
#define TCC2 ((Tcc *)0x42000C00UL)
#define TCC3 ((Tcc *)0x42001000UL)
#define TCC4 ((Tcc *)0x43001000UL)
#define TCC_INST_NUM 5
#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 }
#define TRNG ((Trng *)0x42002800UL)
#define TRNG_INST_NUM 1
#define TRNG_INSTS { TRNG }
#define USB ((Usb *)0x41000000UL)
#define USB_INST_NUM 1
#define USB_INSTS { USB }
#define WDT ((Wdt *)0x40002000UL)
#define WDT_INST_NUM 1
#define WDT_INSTS { WDT }
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ************************************************************************** */
/* ************************************************************************** */
#include "pio/same54p19a.h"
/* ************************************************************************** */
/* ************************************************************************** */
#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */
#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */
#define FLASH_PAGE_SIZE 512
#define FLASH_NB_OF_PAGES 1024
#define FLASH_USER_PAGE_SIZE 512
#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
#define FLASH_ADDR _UL_(0x00000000)
#define CMCC_DATARAM_ADDR _UL_(0x03000000)
#define CMCC_DATARAM_SIZE _UL_(0x00001000)
#define CMCC_TAGRAM_ADDR _UL_(0x03001000)
#define CMCC_TAGRAM_SIZE _UL_(0x00000400)
#define CMCC_VALIDRAM_ADDR _UL_(0x03002000)
#define CMCC_VALIDRAM_SIZE _UL_(0x00000040)
#define HSRAM_ADDR _UL_(0x20000000)
#define HSRAM_ETB_ADDR _UL_(0x20000000)
#define HSRAM_ETB_SIZE _UL_(0x00008000)
#define HSRAM_RET1_ADDR _UL_(0x20000000)
#define HSRAM_RET1_SIZE _UL_(0x00008000)
#define HPB0_ADDR _UL_(0x40000000)
#define HPB1_ADDR _UL_(0x41000000)
#define HPB2_ADDR _UL_(0x42000000)
#define HPB3_ADDR _UL_(0x43000000)
#define SEEPROM_ADDR _UL_(0x44000000)
#define BKUPRAM_ADDR _UL_(0x47000000)
#define PPB_ADDR _UL_(0xE0000000)
#define DSU_DID_RESETVALUE _UL_(0x61840301)
#define ADC0_TOUCH_LINES_NUM 32
#define PORT_GROUPS 4
/* ************************************************************************** */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
#endif /* SAME54P19A_H */
EIC_4_IRQn
@ EIC_4_IRQn
Definition: same54p19a.h:120
DAC_4_IRQn
@ DAC_4_IRQn
Definition: same54p19a.h:228
icm.h
Instance description for ICM.
icm.h
Component description for ICM.
IRQn_Type
enum IRQn IRQn_Type
SERCOM6_1_IRQn
@ SERCOM6_1_IRQn
Definition: same54p19a.h:172
tc4.h
Instance description for TC4.
SERCOM4_0_IRQn
@ SERCOM4_0_IRQn
Definition: same54p19a.h:163
TCC2_3_IRQn
@ TCC2_3_IRQn
Definition: same54p19a.h:201
mclk.h
Component description for MCLK.
FREQM_IRQn
@ FREQM_IRQn
Definition: same54p19a.h:132
TCC4_2_IRQn
@ TCC4_2_IRQn
Definition: same54p19a.h:207
EIC_8_IRQn
@ EIC_8_IRQn
Definition: same54p19a.h:124
SUPC_1_IRQn
@ SUPC_1_IRQn
Definition: same54p19a.h:113
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: same54p19a.h:94
tc5.h
Instance description for TC5.
supc.h
Component description for SUPC.
can0.h
Instance description for CAN0.
TC4_IRQn
@ TC4_IRQn
Definition: same54p19a.h:212
pdec.h
Component description for PDEC.
SERCOM0_0_IRQn
@ SERCOM0_0_IRQn
Definition: same54p19a.h:147
system_same54.h
Low-level initialization functions called upon chip startup.
SERCOM5_0_IRQn
@ SERCOM5_0_IRQn
Definition: same54p19a.h:167
TCC0_6_IRQn
@ TCC0_6_IRQn
Definition: same54p19a.h:192
DMAC_2_IRQn
@ DMAC_2_IRQn
Definition: same54p19a.h:137
EVSYS_0_IRQn
@ EVSYS_0_IRQn
Definition: same54p19a.h:140
TC5_IRQn
@ TC5_IRQn
Definition: same54p19a.h:213
tc2.h
Instance description for TC2.
ADC1_1_IRQn
@ ADC1_1_IRQn
Definition: same54p19a.h:222
can1.h
Instance description for CAN1.
TCC1_0_IRQn
@ TCC1_0_IRQn
Definition: same54p19a.h:193
DMAC_4_IRQn
@ DMAC_4_IRQn
Definition: same54p19a.h:139
EIC_9_IRQn
@ EIC_9_IRQn
Definition: same54p19a.h:125
pac.h
Component description for PAC.
PM_IRQn
@ PM_IRQn
Definition: same54p19a.h:104
tc3.h
Instance description for TC3.
EIC_7_IRQn
@ EIC_7_IRQn
Definition: same54p19a.h:123
TC6_IRQn
@ TC6_IRQn
Definition: same54p19a.h:214
rtc.h
Component description for RTC.
WDT_IRQn
@ WDT_IRQn
Definition: same54p19a.h:114
USB_1_IRQn
@ USB_1_IRQn
Definition: same54p19a.h:182
sercom2.h
Instance description for SERCOM2.
DAC_0_IRQn
@ DAC_0_IRQn
Definition: same54p19a.h:224
sdhc1.h
Instance description for SDHC1.
tcc0.h
Instance description for TCC0.
SERCOM7_2_IRQn
@ SERCOM7_2_IRQn
Definition: same54p19a.h:177
oscctrl.h
Component description for OSCCTRL.
tc6.h
Instance description for TC6.
TC7_IRQn
@ TC7_IRQn
Definition: same54p19a.h:215
NVMCTRL_1_IRQn
@ NVMCTRL_1_IRQn
Definition: same54p19a.h:134
cmcc.h
Component description for CMCC.
NVMCTRL_0_IRQn
@ NVMCTRL_0_IRQn
Definition: same54p19a.h:133
sercom0.h
Instance description for SERCOM0.
wdt.h
Instance description for WDT.
tcc1.h
Instance description for TCC1.
MCLK_IRQn
@ MCLK_IRQn
Definition: same54p19a.h:105
tc7.h
Instance description for TC7.
i2s.h
Instance description for I2S.
TCC2_1_IRQn
@ TCC2_1_IRQn
Definition: same54p19a.h:199
sercom3.h
Instance description for SERCOM3.
sdhc0.h
Instance description for SDHC0.
DAC_2_IRQn
@ DAC_2_IRQn
Definition: same54p19a.h:226
aes.h
Instance description for AES.
EIC_10_IRQn
@ EIC_10_IRQn
Definition: same54p19a.h:126
IRQn
IRQn
Definition: same54n19a.h:92
sercom6.h
Instance description for SERCOM6.
oscctrl.h
Instance description for OSCCTRL.
adc.h
Component description for ADC.
CAN0_IRQn
@ CAN0_IRQn
Definition: same54p19a.h:179
I2S_IRQn
@ I2S_IRQn
Definition: same54p19a.h:229
TRNG_IRQn
@ TRNG_IRQn
Definition: same54p19a.h:232
SERCOM1_3_IRQn
@ SERCOM1_3_IRQn
Definition: same54p19a.h:154
DMAC_1_IRQn
@ DMAC_1_IRQn
Definition: same54p19a.h:136
ADC0_0_IRQn
@ ADC0_0_IRQn
Definition: same54p19a.h:219
RTC_IRQn
@ RTC_IRQn
Definition: same54p19a.h:115
SDHC1_IRQn
@ SDHC1_IRQn
Definition: same54p19a.h:237
sercom4.h
Instance description for SERCOM4.
usb.h
Instance description for USB.
pukcc.h
Instance description for PUKCC.
PendSV_IRQn
@ PendSV_IRQn
Definition: same54p19a.h:101
AC_IRQn
@ AC_IRQn
Definition: same54p19a.h:223
SERCOM3_1_IRQn
@ SERCOM3_1_IRQn
Definition: same54p19a.h:160
sercom7.h
Instance description for SERCOM7.
SERCOM2_0_IRQn
@ SERCOM2_0_IRQn
Definition: same54p19a.h:155
BusFault_IRQn
@ BusFault_IRQn
Definition: same54p19a.h:97
nvmctrl.h
Component description for NVMCTRL.
SERCOM2_2_IRQn
@ SERCOM2_2_IRQn
Definition: same54p19a.h:157
ccl.h
Component description for CCL.
TCC1_4_IRQn
@ TCC1_4_IRQn
Definition: same54p19a.h:197
tc0.h
Instance description for TC0.
hmatrixb.h
Component description for HMATRIXB.
USB_2_IRQn
@ USB_2_IRQn
Definition: same54p19a.h:183
gclk.h
Instance description for GCLK.
EIC_3_IRQn
@ EIC_3_IRQn
Definition: same54p19a.h:119
SERCOM6_3_IRQn
@ SERCOM6_3_IRQn
Definition: same54p19a.h:174
PDEC_2_IRQn
@ PDEC_2_IRQn
Definition: same54p19a.h:218
PDEC_1_IRQn
@ PDEC_1_IRQn
Definition: same54p19a.h:217
tc1.h
Instance description for TC1.
port.h
Instance description for PORT.
tc.h
Component description for TC.
_DeviceVectors
Definition: same54n19a.h:243
usb.h
Component description for USB.
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: same54p19a.h:100
sercom5.h
Instance description for SERCOM5.
wdt.h
Component description for WDT.
ccl.h
Instance description for CCL.
QSPI_IRQn
@ QSPI_IRQn
Definition: same54p19a.h:235
TCC0_1_IRQn
@ TCC0_1_IRQn
Definition: same54p19a.h:187
ICM_IRQn
@ ICM_IRQn
Definition: same54p19a.h:233
SERCOM4_1_IRQn
@ SERCOM4_1_IRQn
Definition: same54p19a.h:164
dsu.h
Instance description for DSU.
SERCOM5_1_IRQn
@ SERCOM5_1_IRQn
Definition: same54p19a.h:168
WoReg16
volatile uint16_t WoReg16
Definition: same54p19a.h:60
TCC3_1_IRQn
@ TCC3_1_IRQn
Definition: same54p19a.h:203
dmac.h
Component description for DMAC.
CAN1_IRQn
@ CAN1_IRQn
Definition: same54p19a.h:180
DAC_1_IRQn
@ DAC_1_IRQn
Definition: same54p19a.h:225
OSCCTRL_4_IRQn
@ OSCCTRL_4_IRQn
Definition: same54p19a.h:110
SERCOM4_3_IRQn
@ SERCOM4_3_IRQn
Definition: same54p19a.h:166
qspi.h
Instance description for QSPI.
pm.h
Component description for PM.
TCC0_2_IRQn
@ TCC0_2_IRQn
Definition: same54p19a.h:188
SERCOM1_0_IRQn
@ SERCOM1_0_IRQn
Definition: same54p19a.h:151
OSCCTRL_1_IRQn
@ OSCCTRL_1_IRQn
Definition: same54p19a.h:107
same54p19a.h
Peripheral I/O description for SAME54P19A.
pdec.h
Instance description for PDEC.
EIC_11_IRQn
@ EIC_11_IRQn
Definition: same54p19a.h:127
RAMECC_IRQn
@ RAMECC_IRQn
Definition: same54p19a.h:146
dac.h
Component description for DAC.
HardFault_IRQn
@ HardFault_IRQn
Definition: same54p19a.h:95
EIC_14_IRQn
@ EIC_14_IRQn
Definition: same54p19a.h:130
EIC_6_IRQn
@ EIC_6_IRQn
Definition: same54p19a.h:122
pac.h
Instance description for PAC.
DMAC_0_IRQn
@ DMAC_0_IRQn
Definition: same54p19a.h:135
gmac.h
Component description for GMAC.
RwReg8
volatile uint8_t RwReg8
Definition: same54p19a.h:64
SERCOM7_3_IRQn
@ SERCOM7_3_IRQn
Definition: same54p19a.h:178
rstc.h
Instance description for RSTC.
EVSYS_2_IRQn
@ EVSYS_2_IRQn
Definition: same54p19a.h:142
TCC0_0_IRQn
@ TCC0_0_IRQn
Definition: same54p19a.h:186
gmac.h
Instance description for GMAC.
DMAC_3_IRQn
@ DMAC_3_IRQn
Definition: same54p19a.h:138
SERCOM3_0_IRQn
@ SERCOM3_0_IRQn
Definition: same54p19a.h:159
SERCOM1_2_IRQn
@ SERCOM1_2_IRQn
Definition: same54p19a.h:153
EIC_12_IRQn
@ EIC_12_IRQn
Definition: same54p19a.h:128
ac.h
Component description for AC.
SDHC0_IRQn
@ SDHC0_IRQn
Definition: same54p19a.h:236
trng.h
Component description for TRNG.
Reset_Handler
void Reset_Handler(void)
This is the code that gets called on processor reset. To initialize the device, and call the main() r...
Definition: startup_same54.c:499
SERCOM0_1_IRQn
@ SERCOM0_1_IRQn
Definition: same54p19a.h:148
AES_IRQn
@ AES_IRQn
Definition: same54p19a.h:231
DAC_3_IRQn
@ DAC_3_IRQn
Definition: same54p19a.h:227
WoReg8
volatile uint8_t WoReg8
Definition: same54p19a.h:61
SVCall_IRQn
@ SVCall_IRQn
Definition: same54p19a.h:99
TCC1_3_IRQn
@ TCC1_3_IRQn
Definition: same54p19a.h:196
TCC0_3_IRQn
@ TCC0_3_IRQn
Definition: same54p19a.h:189
eic.h
Instance description for EIC.
OSCCTRL_2_IRQn
@ OSCCTRL_2_IRQn
Definition: same54p19a.h:108
sercom.h
Component description for SERCOM.
USB_3_IRQn
@ USB_3_IRQn
Definition: same54p19a.h:184
PCC_IRQn
@ PCC_IRQn
Definition: same54p19a.h:230
EVSYS_1_IRQn
@ EVSYS_1_IRQn
Definition: same54p19a.h:141
TC3_IRQn
@ TC3_IRQn
Definition: same54p19a.h:211
SERCOM3_2_IRQn
@ SERCOM3_2_IRQn
Definition: same54p19a.h:161
ramecc.h
Instance description for RAMECC.
SERCOM0_3_IRQn
@ SERCOM0_3_IRQn
Definition: same54p19a.h:150
OSCCTRL_3_IRQn
@ OSCCTRL_3_IRQn
Definition: same54p19a.h:109
GMAC_IRQn
@ GMAC_IRQn
Definition: same54p19a.h:185
EIC_1_IRQn
@ EIC_1_IRQn
Definition: same54p19a.h:117
WoReg
volatile uint32_t WoReg
Definition: same54p19a.h:59
dsu.h
Component description for DSU.
pcc.h
Component description for PCC.
osc32kctrl.h
Component description for OSC32KCTRL.
PAC_IRQn
@ PAC_IRQn
Definition: same54p19a.h:145
gclk.h
Component description for GCLK.
SERCOM0_2_IRQn
@ SERCOM0_2_IRQn
Definition: same54p19a.h:149
PERIPH_COUNT_IRQn
@ PERIPH_COUNT_IRQn
Definition: same54p19a.h:239
TCC2_0_IRQn
@ TCC2_0_IRQn
Definition: same54p19a.h:198
cmcc.h
Instance description for CMCC.
trng.h
Instance description for TRNG.
EVSYS_3_IRQn
@ EVSYS_3_IRQn
Definition: same54p19a.h:143
TC2_IRQn
@ TC2_IRQn
Definition: same54p19a.h:210
qspi.h
Component description for QSPI.
rtc.h
Instance description for RTC.
SERCOM1_1_IRQn
@ SERCOM1_1_IRQn
Definition: same54p19a.h:152
ADC0_1_IRQn
@ ADC0_1_IRQn
Definition: same54p19a.h:220
OSCCTRL_0_IRQn
@ OSCCTRL_0_IRQn
Definition: same54p19a.h:106
evsys.h
Component description for EVSYS.
SERCOM4_2_IRQn
@ SERCOM4_2_IRQn
Definition: same54p19a.h:165
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: same54p19a.h:96
TCC1_2_IRQn
@ TCC1_2_IRQn
Definition: same54p19a.h:195
EVSYS_4_IRQn
@ EVSYS_4_IRQn
Definition: same54p19a.h:144
SERCOM6_0_IRQn
@ SERCOM6_0_IRQn
Definition: same54p19a.h:171
PUKCC_IRQn
@ PUKCC_IRQn
Definition: same54p19a.h:234
port.h
Component description for PORT.
ac.h
Instance description for AC.
SERCOM3_3_IRQn
@ SERCOM3_3_IRQn
Definition: same54p19a.h:162
mclk.h
Instance description for MCLK.
UsageFault_IRQn
@ UsageFault_IRQn
Definition: same54p19a.h:98
RoReg8
volatile const uint8_t RoReg8
Definition: same54p19a.h:53
PDEC_0_IRQn
@ PDEC_0_IRQn
Definition: same54p19a.h:216
eic.h
Component description for EIC.
aes.h
Component description for AES.
EIC_2_IRQn
@ EIC_2_IRQn
Definition: same54p19a.h:118
TCC2_2_IRQn
@ TCC2_2_IRQn
Definition: same54p19a.h:200
ADC1_0_IRQn
@ ADC1_0_IRQn
Definition: same54p19a.h:221
EIC_15_IRQn
@ EIC_15_IRQn
Definition: same54p19a.h:131
SERCOM5_3_IRQn
@ SERCOM5_3_IRQn
Definition: same54p19a.h:170
RwReg
volatile uint32_t RwReg
Definition: same54p19a.h:62
hmatrix.h
Instance description for HMATRIX.
OSC32KCTRL_IRQn
@ OSC32KCTRL_IRQn
Definition: same54p19a.h:111
TCC0_4_IRQn
@ TCC0_4_IRQn
Definition: same54p19a.h:190
adc0.h
Instance description for ADC0.
EIC_0_IRQn
@ EIC_0_IRQn
Definition: same54p19a.h:116
TC1_IRQn
@ TC1_IRQn
Definition: same54p19a.h:209
evsys.h
Instance description for EVSYS.
TCC3_2_IRQn
@ TCC3_2_IRQn
Definition: same54p19a.h:204
adc1.h
Instance description for ADC1.
can.h
Component description for CAN.
SERCOM2_1_IRQn
@ SERCOM2_1_IRQn
Definition: same54p19a.h:156
dac.h
Instance description for DAC.
sercom1.h
Instance description for SERCOM1.
SERCOM2_3_IRQn
@ SERCOM2_3_IRQn
Definition: same54p19a.h:158
tcc4.h
Instance description for TCC4.
rstc.h
Component description for RSTC.
USB_0_IRQn
@ USB_0_IRQn
Definition: same54p19a.h:181
TCC0_5_IRQn
@ TCC0_5_IRQn
Definition: same54p19a.h:191
tcc.h
Component description for TCC.
SERCOM5_2_IRQn
@ SERCOM5_2_IRQn
Definition: same54p19a.h:169
SERCOM7_0_IRQn
@ SERCOM7_0_IRQn
Definition: same54p19a.h:175
RoReg16
volatile const uint16_t RoReg16
Definition: same54p19a.h:52
EIC_13_IRQn
@ EIC_13_IRQn
Definition: same54p19a.h:129
TCC1_1_IRQn
@ TCC1_1_IRQn
Definition: same54p19a.h:194
freqm.h
Component description for FREQM.
RoReg
volatile const uint32_t RoReg
Definition: same54p19a.h:51
TCC3_0_IRQn
@ TCC3_0_IRQn
Definition: same54p19a.h:202
SysTick_IRQn
@ SysTick_IRQn
Definition: same54p19a.h:102
supc.h
Instance description for SUPC.
tcc2.h
Instance description for TCC2.
osc32kctrl.h
Instance description for OSC32KCTRL.
RwReg16
volatile uint16_t RwReg16
Definition: same54p19a.h:63
dmac.h
Instance description for DMAC.
i2s.h
Component description for I2S.
pm.h
Instance description for PM.
ramecc.h
Component description for RAMECC.
tcc3.h
Instance description for TCC3.
pcc.h
Instance description for PCC.
TC0_IRQn
@ TC0_IRQn
Definition: same54p19a.h:208
freqm.h
Instance description for FREQM.
TCC4_1_IRQn
@ TCC4_1_IRQn
Definition: same54p19a.h:206
SUPC_0_IRQn
@ SUPC_0_IRQn
Definition: same54p19a.h:112
EIC_5_IRQn
@ EIC_5_IRQn
Definition: same54p19a.h:121
sdhc.h
Component description for SDHC.
SERCOM6_2_IRQn
@ SERCOM6_2_IRQn
Definition: same54p19a.h:173
TCC4_0_IRQn
@ TCC4_0_IRQn
Definition: same54p19a.h:205
nvmctrl.h
Instance description for NVMCTRL.
SERCOM7_1_IRQn
@ SERCOM7_1_IRQn
Definition: same54p19a.h:176