i2s.h
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#ifndef _SAME54_I2S_COMPONENT_
#define _SAME54_I2S_COMPONENT_
/* ========================================================================== */
/* ========================================================================== */
#define I2S_U2224
#define REV_I2S 0x200
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1;
uint8_t ENABLE:1;
uint8_t CKEN0:1;
uint8_t CKEN1:1;
uint8_t TXEN:1;
uint8_t RXEN:1;
uint8_t :2;
} bit;
struct {
uint8_t :2;
uint8_t CKEN:2;
uint8_t :4;
} vec;
uint8_t reg;
} I2S_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_CTRLA_OFFSET 0x00
#define I2S_CTRLA_RESETVALUE _U_(0x00)
#define I2S_CTRLA_SWRST_Pos 0
#define I2S_CTRLA_SWRST (_U_(0x1) << I2S_CTRLA_SWRST_Pos)
#define I2S_CTRLA_ENABLE_Pos 1
#define I2S_CTRLA_ENABLE (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)
#define I2S_CTRLA_CKEN0_Pos 2
#define I2S_CTRLA_CKEN0 (_U_(1) << I2S_CTRLA_CKEN0_Pos)
#define I2S_CTRLA_CKEN1_Pos 3
#define I2S_CTRLA_CKEN1 (_U_(1) << I2S_CTRLA_CKEN1_Pos)
#define I2S_CTRLA_CKEN_Pos 2
#define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos)
#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
#define I2S_CTRLA_TXEN_Pos 4
#define I2S_CTRLA_TXEN (_U_(0x1) << I2S_CTRLA_TXEN_Pos)
#define I2S_CTRLA_RXEN_Pos 5
#define I2S_CTRLA_RXEN (_U_(0x1) << I2S_CTRLA_RXEN_Pos)
#define I2S_CTRLA_MASK _U_(0x3F)
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SLOTSIZE:2;
uint32_t NBSLOTS:3;
uint32_t FSWIDTH:2;
uint32_t BITDELAY:1;
uint32_t FSSEL:1;
uint32_t FSINV:1;
uint32_t FSOUTINV:1;
uint32_t SCKSEL:1;
uint32_t SCKOUTINV:1;
uint32_t MCKSEL:1;
uint32_t MCKEN:1;
uint32_t MCKOUTINV:1;
uint32_t MCKDIV:6;
uint32_t :2;
uint32_t MCKOUTDIV:6;
uint32_t :2;
} bit;
uint32_t reg;
} I2S_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_CLKCTRL_OFFSET 0x04
#define I2S_CLKCTRL_RESETVALUE _U_(0x00000000)
#define I2S_CLKCTRL_SLOTSIZE_Pos 0
#define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
#define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0)
#define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1)
#define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2)
#define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3)
#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_NBSLOTS_Pos 2
#define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)
#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
#define I2S_CLKCTRL_FSWIDTH_Pos 5
#define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
#define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0)
#define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1)
#define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2)
#define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3)
#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_BITDELAY_Pos 7
#define I2S_CLKCTRL_BITDELAY (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0)
#define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1)
#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_FSSEL_Pos 8
#define I2S_CLKCTRL_FSSEL (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0)
#define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1)
#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSINV_Pos 9
#define I2S_CLKCTRL_FSINV (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)
#define I2S_CLKCTRL_FSOUTINV_Pos 10
#define I2S_CLKCTRL_FSOUTINV (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)
#define I2S_CLKCTRL_SCKSEL_Pos 11
#define I2S_CLKCTRL_SCKSEL (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0)
#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1)
#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKOUTINV_Pos 12
#define I2S_CLKCTRL_SCKOUTINV (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)
#define I2S_CLKCTRL_MCKSEL_Pos 13
#define I2S_CLKCTRL_MCKSEL (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0)
#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1)
#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKEN_Pos 14
#define I2S_CLKCTRL_MCKEN (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)
#define I2S_CLKCTRL_MCKOUTINV_Pos 15
#define I2S_CLKCTRL_MCKOUTINV (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)
#define I2S_CLKCTRL_MCKDIV_Pos 16
#define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKDIV_Pos)
#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
#define I2S_CLKCTRL_MCKOUTDIV_Pos 24
#define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x3F) << I2S_CLKCTRL_MCKOUTDIV_Pos)
#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
#define I2S_CLKCTRL_MASK _U_(0x3F3FFFFF)
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1;
uint16_t RXRDY1:1;
uint16_t :2;
uint16_t RXOR0:1;
uint16_t RXOR1:1;
uint16_t :2;
uint16_t TXRDY0:1;
uint16_t TXRDY1:1;
uint16_t :2;
uint16_t TXUR0:1;
uint16_t TXUR1:1;
uint16_t :2;
} bit;
struct {
uint16_t RXRDY:2;
uint16_t :2;
uint16_t RXOR:2;
uint16_t :2;
uint16_t TXRDY:2;
uint16_t :2;
uint16_t TXUR:2;
uint16_t :2;
} vec;
uint16_t reg;
} I2S_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTENCLR_OFFSET 0x0C
#define I2S_INTENCLR_RESETVALUE _U_(0x0000)
#define I2S_INTENCLR_RXRDY0_Pos 0
#define I2S_INTENCLR_RXRDY0 (_U_(1) << I2S_INTENCLR_RXRDY0_Pos)
#define I2S_INTENCLR_RXRDY1_Pos 1
#define I2S_INTENCLR_RXRDY1 (_U_(1) << I2S_INTENCLR_RXRDY1_Pos)
#define I2S_INTENCLR_RXRDY_Pos 0
#define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)
#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
#define I2S_INTENCLR_RXOR0_Pos 4
#define I2S_INTENCLR_RXOR0 (_U_(1) << I2S_INTENCLR_RXOR0_Pos)
#define I2S_INTENCLR_RXOR1_Pos 5
#define I2S_INTENCLR_RXOR1 (_U_(1) << I2S_INTENCLR_RXOR1_Pos)
#define I2S_INTENCLR_RXOR_Pos 4
#define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)
#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
#define I2S_INTENCLR_TXRDY0_Pos 8
#define I2S_INTENCLR_TXRDY0 (_U_(1) << I2S_INTENCLR_TXRDY0_Pos)
#define I2S_INTENCLR_TXRDY1_Pos 9
#define I2S_INTENCLR_TXRDY1 (_U_(1) << I2S_INTENCLR_TXRDY1_Pos)
#define I2S_INTENCLR_TXRDY_Pos 8
#define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)
#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
#define I2S_INTENCLR_TXUR0_Pos 12
#define I2S_INTENCLR_TXUR0 (_U_(1) << I2S_INTENCLR_TXUR0_Pos)
#define I2S_INTENCLR_TXUR1_Pos 13
#define I2S_INTENCLR_TXUR1 (_U_(1) << I2S_INTENCLR_TXUR1_Pos)
#define I2S_INTENCLR_TXUR_Pos 12
#define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)
#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
#define I2S_INTENCLR_MASK _U_(0x3333)
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1;
uint16_t RXRDY1:1;
uint16_t :2;
uint16_t RXOR0:1;
uint16_t RXOR1:1;
uint16_t :2;
uint16_t TXRDY0:1;
uint16_t TXRDY1:1;
uint16_t :2;
uint16_t TXUR0:1;
uint16_t TXUR1:1;
uint16_t :2;
} bit;
struct {
uint16_t RXRDY:2;
uint16_t :2;
uint16_t RXOR:2;
uint16_t :2;
uint16_t TXRDY:2;
uint16_t :2;
uint16_t TXUR:2;
uint16_t :2;
} vec;
uint16_t reg;
} I2S_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTENSET_OFFSET 0x10
#define I2S_INTENSET_RESETVALUE _U_(0x0000)
#define I2S_INTENSET_RXRDY0_Pos 0
#define I2S_INTENSET_RXRDY0 (_U_(1) << I2S_INTENSET_RXRDY0_Pos)
#define I2S_INTENSET_RXRDY1_Pos 1
#define I2S_INTENSET_RXRDY1 (_U_(1) << I2S_INTENSET_RXRDY1_Pos)
#define I2S_INTENSET_RXRDY_Pos 0
#define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)
#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
#define I2S_INTENSET_RXOR0_Pos 4
#define I2S_INTENSET_RXOR0 (_U_(1) << I2S_INTENSET_RXOR0_Pos)
#define I2S_INTENSET_RXOR1_Pos 5
#define I2S_INTENSET_RXOR1 (_U_(1) << I2S_INTENSET_RXOR1_Pos)
#define I2S_INTENSET_RXOR_Pos 4
#define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos)
#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
#define I2S_INTENSET_TXRDY0_Pos 8
#define I2S_INTENSET_TXRDY0 (_U_(1) << I2S_INTENSET_TXRDY0_Pos)
#define I2S_INTENSET_TXRDY1_Pos 9
#define I2S_INTENSET_TXRDY1 (_U_(1) << I2S_INTENSET_TXRDY1_Pos)
#define I2S_INTENSET_TXRDY_Pos 8
#define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)
#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
#define I2S_INTENSET_TXUR0_Pos 12
#define I2S_INTENSET_TXUR0 (_U_(1) << I2S_INTENSET_TXUR0_Pos)
#define I2S_INTENSET_TXUR1_Pos 13
#define I2S_INTENSET_TXUR1 (_U_(1) << I2S_INTENSET_TXUR1_Pos)
#define I2S_INTENSET_TXUR_Pos 12
#define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos)
#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
#define I2S_INTENSET_MASK _U_(0x3333)
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint16_t RXRDY0:1;
__I uint16_t RXRDY1:1;
__I uint16_t :2;
__I uint16_t RXOR0:1;
__I uint16_t RXOR1:1;
__I uint16_t :2;
__I uint16_t TXRDY0:1;
__I uint16_t TXRDY1:1;
__I uint16_t :2;
__I uint16_t TXUR0:1;
__I uint16_t TXUR1:1;
__I uint16_t :2;
} bit;
struct {
__I uint16_t RXRDY:2;
__I uint16_t :2;
__I uint16_t RXOR:2;
__I uint16_t :2;
__I uint16_t TXRDY:2;
__I uint16_t :2;
__I uint16_t TXUR:2;
__I uint16_t :2;
} vec;
uint16_t reg;
} I2S_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTFLAG_OFFSET 0x14
#define I2S_INTFLAG_RESETVALUE _U_(0x0000)
#define I2S_INTFLAG_RXRDY0_Pos 0
#define I2S_INTFLAG_RXRDY0 (_U_(1) << I2S_INTFLAG_RXRDY0_Pos)
#define I2S_INTFLAG_RXRDY1_Pos 1
#define I2S_INTFLAG_RXRDY1 (_U_(1) << I2S_INTFLAG_RXRDY1_Pos)
#define I2S_INTFLAG_RXRDY_Pos 0
#define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)
#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
#define I2S_INTFLAG_RXOR0_Pos 4
#define I2S_INTFLAG_RXOR0 (_U_(1) << I2S_INTFLAG_RXOR0_Pos)
#define I2S_INTFLAG_RXOR1_Pos 5
#define I2S_INTFLAG_RXOR1 (_U_(1) << I2S_INTFLAG_RXOR1_Pos)
#define I2S_INTFLAG_RXOR_Pos 4
#define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)
#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
#define I2S_INTFLAG_TXRDY0_Pos 8
#define I2S_INTFLAG_TXRDY0 (_U_(1) << I2S_INTFLAG_TXRDY0_Pos)
#define I2S_INTFLAG_TXRDY1_Pos 9
#define I2S_INTFLAG_TXRDY1 (_U_(1) << I2S_INTFLAG_TXRDY1_Pos)
#define I2S_INTFLAG_TXRDY_Pos 8
#define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)
#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
#define I2S_INTFLAG_TXUR0_Pos 12
#define I2S_INTFLAG_TXUR0 (_U_(1) << I2S_INTFLAG_TXUR0_Pos)
#define I2S_INTFLAG_TXUR1_Pos 13
#define I2S_INTFLAG_TXUR1 (_U_(1) << I2S_INTFLAG_TXUR1_Pos)
#define I2S_INTFLAG_TXUR_Pos 12
#define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)
#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
#define I2S_INTFLAG_MASK _U_(0x3333)
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1;
uint16_t ENABLE:1;
uint16_t CKEN0:1;
uint16_t CKEN1:1;
uint16_t TXEN:1;
uint16_t RXEN:1;
uint16_t :2;
uint16_t TXDATA:1;
uint16_t RXDATA:1;
uint16_t :6;
} bit;
struct {
uint16_t :2;
uint16_t CKEN:2;
uint16_t :12;
} vec;
uint16_t reg;
} I2S_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_SYNCBUSY_OFFSET 0x18
#define I2S_SYNCBUSY_RESETVALUE _U_(0x0000)
#define I2S_SYNCBUSY_SWRST_Pos 0
#define I2S_SYNCBUSY_SWRST (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)
#define I2S_SYNCBUSY_ENABLE_Pos 1
#define I2S_SYNCBUSY_ENABLE (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)
#define I2S_SYNCBUSY_CKEN0_Pos 2
#define I2S_SYNCBUSY_CKEN0 (_U_(1) << I2S_SYNCBUSY_CKEN0_Pos)
#define I2S_SYNCBUSY_CKEN1_Pos 3
#define I2S_SYNCBUSY_CKEN1 (_U_(1) << I2S_SYNCBUSY_CKEN1_Pos)
#define I2S_SYNCBUSY_CKEN_Pos 2
#define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)
#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
#define I2S_SYNCBUSY_TXEN_Pos 4
#define I2S_SYNCBUSY_TXEN (_U_(0x1) << I2S_SYNCBUSY_TXEN_Pos)
#define I2S_SYNCBUSY_RXEN_Pos 5
#define I2S_SYNCBUSY_RXEN (_U_(0x1) << I2S_SYNCBUSY_RXEN_Pos)
#define I2S_SYNCBUSY_TXDATA_Pos 8
#define I2S_SYNCBUSY_TXDATA (_U_(0x1) << I2S_SYNCBUSY_TXDATA_Pos)
#define I2S_SYNCBUSY_RXDATA_Pos 9
#define I2S_SYNCBUSY_RXDATA (_U_(0x1) << I2S_SYNCBUSY_RXDATA_Pos)
#define I2S_SYNCBUSY_MASK _U_(0x033F)
/* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2;
uint32_t TXDEFAULT:2;
uint32_t TXSAME:1;
uint32_t :2;
uint32_t SLOTADJ:1;
uint32_t DATASIZE:3;
uint32_t :1;
uint32_t WORDADJ:1;
uint32_t EXTEND:2;
uint32_t BITREV:1;
uint32_t SLOTDIS0:1;
uint32_t SLOTDIS1:1;
uint32_t SLOTDIS2:1;
uint32_t SLOTDIS3:1;
uint32_t SLOTDIS4:1;
uint32_t SLOTDIS5:1;
uint32_t SLOTDIS6:1;
uint32_t SLOTDIS7:1;
uint32_t MONO:1;
uint32_t DMA:1;
uint32_t :6;
} bit;
struct {
uint32_t :16;
uint32_t SLOTDIS:8;
uint32_t :8;
} vec;
uint32_t reg;
} I2S_TXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_TXCTRL_OFFSET 0x20
#define I2S_TXCTRL_RESETVALUE _U_(0x00000000)
#define I2S_TXCTRL_TXDEFAULT_Pos 2
#define I2S_TXCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXDEFAULT(value) (I2S_TXCTRL_TXDEFAULT_Msk & ((value) << I2S_TXCTRL_TXDEFAULT_Pos))
#define I2S_TXCTRL_TXDEFAULT_ZERO_Val _U_(0x0)
#define I2S_TXCTRL_TXDEFAULT_ONE_Val _U_(0x1)
#define I2S_TXCTRL_TXDEFAULT_HIZ_Val _U_(0x3)
#define I2S_TXCTRL_TXDEFAULT_ZERO (I2S_TXCTRL_TXDEFAULT_ZERO_Val << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXDEFAULT_ONE (I2S_TXCTRL_TXDEFAULT_ONE_Val << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXDEFAULT_HIZ (I2S_TXCTRL_TXDEFAULT_HIZ_Val << I2S_TXCTRL_TXDEFAULT_Pos)
#define I2S_TXCTRL_TXSAME_Pos 4
#define I2S_TXCTRL_TXSAME (_U_(0x1) << I2S_TXCTRL_TXSAME_Pos)
#define I2S_TXCTRL_TXSAME_ZERO_Val _U_(0x0)
#define I2S_TXCTRL_TXSAME_SAME_Val _U_(0x1)
#define I2S_TXCTRL_TXSAME_ZERO (I2S_TXCTRL_TXSAME_ZERO_Val << I2S_TXCTRL_TXSAME_Pos)
#define I2S_TXCTRL_TXSAME_SAME (I2S_TXCTRL_TXSAME_SAME_Val << I2S_TXCTRL_TXSAME_Pos)
#define I2S_TXCTRL_SLOTADJ_Pos 7
#define I2S_TXCTRL_SLOTADJ (_U_(0x1) << I2S_TXCTRL_SLOTADJ_Pos)
#define I2S_TXCTRL_SLOTADJ_RIGHT_Val _U_(0x0)
#define I2S_TXCTRL_SLOTADJ_LEFT_Val _U_(0x1)
#define I2S_TXCTRL_SLOTADJ_RIGHT (I2S_TXCTRL_SLOTADJ_RIGHT_Val << I2S_TXCTRL_SLOTADJ_Pos)
#define I2S_TXCTRL_SLOTADJ_LEFT (I2S_TXCTRL_SLOTADJ_LEFT_Val << I2S_TXCTRL_SLOTADJ_Pos)
#define I2S_TXCTRL_DATASIZE_Pos 8
#define I2S_TXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE(value) (I2S_TXCTRL_DATASIZE_Msk & ((value) << I2S_TXCTRL_DATASIZE_Pos))
#define I2S_TXCTRL_DATASIZE_32_Val _U_(0x0)
#define I2S_TXCTRL_DATASIZE_24_Val _U_(0x1)
#define I2S_TXCTRL_DATASIZE_20_Val _U_(0x2)
#define I2S_TXCTRL_DATASIZE_18_Val _U_(0x3)
#define I2S_TXCTRL_DATASIZE_16_Val _U_(0x4)
#define I2S_TXCTRL_DATASIZE_16C_Val _U_(0x5)
#define I2S_TXCTRL_DATASIZE_8_Val _U_(0x6)
#define I2S_TXCTRL_DATASIZE_8C_Val _U_(0x7)
#define I2S_TXCTRL_DATASIZE_32 (I2S_TXCTRL_DATASIZE_32_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_24 (I2S_TXCTRL_DATASIZE_24_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_20 (I2S_TXCTRL_DATASIZE_20_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_18 (I2S_TXCTRL_DATASIZE_18_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_16 (I2S_TXCTRL_DATASIZE_16_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_16C (I2S_TXCTRL_DATASIZE_16C_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_8 (I2S_TXCTRL_DATASIZE_8_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_DATASIZE_8C (I2S_TXCTRL_DATASIZE_8C_Val << I2S_TXCTRL_DATASIZE_Pos)
#define I2S_TXCTRL_WORDADJ_Pos 12
#define I2S_TXCTRL_WORDADJ (_U_(0x1) << I2S_TXCTRL_WORDADJ_Pos)
#define I2S_TXCTRL_WORDADJ_RIGHT_Val _U_(0x0)
#define I2S_TXCTRL_WORDADJ_LEFT_Val _U_(0x1)
#define I2S_TXCTRL_WORDADJ_RIGHT (I2S_TXCTRL_WORDADJ_RIGHT_Val << I2S_TXCTRL_WORDADJ_Pos)
#define I2S_TXCTRL_WORDADJ_LEFT (I2S_TXCTRL_WORDADJ_LEFT_Val << I2S_TXCTRL_WORDADJ_Pos)
#define I2S_TXCTRL_EXTEND_Pos 13
#define I2S_TXCTRL_EXTEND_Msk (_U_(0x3) << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND(value) (I2S_TXCTRL_EXTEND_Msk & ((value) << I2S_TXCTRL_EXTEND_Pos))
#define I2S_TXCTRL_EXTEND_ZERO_Val _U_(0x0)
#define I2S_TXCTRL_EXTEND_ONE_Val _U_(0x1)
#define I2S_TXCTRL_EXTEND_MSBIT_Val _U_(0x2)
#define I2S_TXCTRL_EXTEND_LSBIT_Val _U_(0x3)
#define I2S_TXCTRL_EXTEND_ZERO (I2S_TXCTRL_EXTEND_ZERO_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND_ONE (I2S_TXCTRL_EXTEND_ONE_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND_MSBIT (I2S_TXCTRL_EXTEND_MSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_EXTEND_LSBIT (I2S_TXCTRL_EXTEND_LSBIT_Val << I2S_TXCTRL_EXTEND_Pos)
#define I2S_TXCTRL_BITREV_Pos 15
#define I2S_TXCTRL_BITREV (_U_(0x1) << I2S_TXCTRL_BITREV_Pos)
#define I2S_TXCTRL_BITREV_MSBIT_Val _U_(0x0)
#define I2S_TXCTRL_BITREV_LSBIT_Val _U_(0x1)
#define I2S_TXCTRL_BITREV_MSBIT (I2S_TXCTRL_BITREV_MSBIT_Val << I2S_TXCTRL_BITREV_Pos)
#define I2S_TXCTRL_BITREV_LSBIT (I2S_TXCTRL_BITREV_LSBIT_Val << I2S_TXCTRL_BITREV_Pos)
#define I2S_TXCTRL_SLOTDIS0_Pos 16
#define I2S_TXCTRL_SLOTDIS0 (_U_(1) << I2S_TXCTRL_SLOTDIS0_Pos)
#define I2S_TXCTRL_SLOTDIS1_Pos 17
#define I2S_TXCTRL_SLOTDIS1 (_U_(1) << I2S_TXCTRL_SLOTDIS1_Pos)
#define I2S_TXCTRL_SLOTDIS2_Pos 18
#define I2S_TXCTRL_SLOTDIS2 (_U_(1) << I2S_TXCTRL_SLOTDIS2_Pos)
#define I2S_TXCTRL_SLOTDIS3_Pos 19
#define I2S_TXCTRL_SLOTDIS3 (_U_(1) << I2S_TXCTRL_SLOTDIS3_Pos)
#define I2S_TXCTRL_SLOTDIS4_Pos 20
#define I2S_TXCTRL_SLOTDIS4 (_U_(1) << I2S_TXCTRL_SLOTDIS4_Pos)
#define I2S_TXCTRL_SLOTDIS5_Pos 21
#define I2S_TXCTRL_SLOTDIS5 (_U_(1) << I2S_TXCTRL_SLOTDIS5_Pos)
#define I2S_TXCTRL_SLOTDIS6_Pos 22
#define I2S_TXCTRL_SLOTDIS6 (_U_(1) << I2S_TXCTRL_SLOTDIS6_Pos)
#define I2S_TXCTRL_SLOTDIS7_Pos 23
#define I2S_TXCTRL_SLOTDIS7 (_U_(1) << I2S_TXCTRL_SLOTDIS7_Pos)
#define I2S_TXCTRL_SLOTDIS_Pos 16
#define I2S_TXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_TXCTRL_SLOTDIS_Pos)
#define I2S_TXCTRL_SLOTDIS(value) (I2S_TXCTRL_SLOTDIS_Msk & ((value) << I2S_TXCTRL_SLOTDIS_Pos))
#define I2S_TXCTRL_MONO_Pos 24
#define I2S_TXCTRL_MONO (_U_(0x1) << I2S_TXCTRL_MONO_Pos)
#define I2S_TXCTRL_MONO_STEREO_Val _U_(0x0)
#define I2S_TXCTRL_MONO_MONO_Val _U_(0x1)
#define I2S_TXCTRL_MONO_STEREO (I2S_TXCTRL_MONO_STEREO_Val << I2S_TXCTRL_MONO_Pos)
#define I2S_TXCTRL_MONO_MONO (I2S_TXCTRL_MONO_MONO_Val << I2S_TXCTRL_MONO_Pos)
#define I2S_TXCTRL_DMA_Pos 25
#define I2S_TXCTRL_DMA (_U_(0x1) << I2S_TXCTRL_DMA_Pos)
#define I2S_TXCTRL_DMA_SINGLE_Val _U_(0x0)
#define I2S_TXCTRL_DMA_MULTIPLE_Val _U_(0x1)
#define I2S_TXCTRL_DMA_SINGLE (I2S_TXCTRL_DMA_SINGLE_Val << I2S_TXCTRL_DMA_Pos)
#define I2S_TXCTRL_DMA_MULTIPLE (I2S_TXCTRL_DMA_MULTIPLE_Val << I2S_TXCTRL_DMA_Pos)
#define I2S_TXCTRL_MASK _U_(0x03FFF79C)
/* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SERMODE:2;
uint32_t :3;
uint32_t CLKSEL:1;
uint32_t :1;
uint32_t SLOTADJ:1;
uint32_t DATASIZE:3;
uint32_t :1;
uint32_t WORDADJ:1;
uint32_t EXTEND:2;
uint32_t BITREV:1;
uint32_t SLOTDIS0:1;
uint32_t SLOTDIS1:1;
uint32_t SLOTDIS2:1;
uint32_t SLOTDIS3:1;
uint32_t SLOTDIS4:1;
uint32_t SLOTDIS5:1;
uint32_t SLOTDIS6:1;
uint32_t SLOTDIS7:1;
uint32_t MONO:1;
uint32_t DMA:1;
uint32_t RXLOOP:1;
uint32_t :5;
} bit;
struct {
uint32_t :16;
uint32_t SLOTDIS:8;
uint32_t :8;
} vec;
uint32_t reg;
} I2S_RXCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_RXCTRL_OFFSET 0x24
#define I2S_RXCTRL_RESETVALUE _U_(0x00000000)
#define I2S_RXCTRL_SERMODE_Pos 0
#define I2S_RXCTRL_SERMODE_Msk (_U_(0x3) << I2S_RXCTRL_SERMODE_Pos)
#define I2S_RXCTRL_SERMODE(value) (I2S_RXCTRL_SERMODE_Msk & ((value) << I2S_RXCTRL_SERMODE_Pos))
#define I2S_RXCTRL_SERMODE_RX_Val _U_(0x0)
#define I2S_RXCTRL_SERMODE_PDM2_Val _U_(0x2)
#define I2S_RXCTRL_SERMODE_RX (I2S_RXCTRL_SERMODE_RX_Val << I2S_RXCTRL_SERMODE_Pos)
#define I2S_RXCTRL_SERMODE_PDM2 (I2S_RXCTRL_SERMODE_PDM2_Val << I2S_RXCTRL_SERMODE_Pos)
#define I2S_RXCTRL_CLKSEL_Pos 5
#define I2S_RXCTRL_CLKSEL (_U_(0x1) << I2S_RXCTRL_CLKSEL_Pos)
#define I2S_RXCTRL_CLKSEL_CLK0_Val _U_(0x0)
#define I2S_RXCTRL_CLKSEL_CLK1_Val _U_(0x1)
#define I2S_RXCTRL_CLKSEL_CLK0 (I2S_RXCTRL_CLKSEL_CLK0_Val << I2S_RXCTRL_CLKSEL_Pos)
#define I2S_RXCTRL_CLKSEL_CLK1 (I2S_RXCTRL_CLKSEL_CLK1_Val << I2S_RXCTRL_CLKSEL_Pos)
#define I2S_RXCTRL_SLOTADJ_Pos 7
#define I2S_RXCTRL_SLOTADJ (_U_(0x1) << I2S_RXCTRL_SLOTADJ_Pos)
#define I2S_RXCTRL_SLOTADJ_RIGHT_Val _U_(0x0)
#define I2S_RXCTRL_SLOTADJ_LEFT_Val _U_(0x1)
#define I2S_RXCTRL_SLOTADJ_RIGHT (I2S_RXCTRL_SLOTADJ_RIGHT_Val << I2S_RXCTRL_SLOTADJ_Pos)
#define I2S_RXCTRL_SLOTADJ_LEFT (I2S_RXCTRL_SLOTADJ_LEFT_Val << I2S_RXCTRL_SLOTADJ_Pos)
#define I2S_RXCTRL_DATASIZE_Pos 8
#define I2S_RXCTRL_DATASIZE_Msk (_U_(0x7) << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE(value) (I2S_RXCTRL_DATASIZE_Msk & ((value) << I2S_RXCTRL_DATASIZE_Pos))
#define I2S_RXCTRL_DATASIZE_32_Val _U_(0x0)
#define I2S_RXCTRL_DATASIZE_24_Val _U_(0x1)
#define I2S_RXCTRL_DATASIZE_20_Val _U_(0x2)
#define I2S_RXCTRL_DATASIZE_18_Val _U_(0x3)
#define I2S_RXCTRL_DATASIZE_16_Val _U_(0x4)
#define I2S_RXCTRL_DATASIZE_16C_Val _U_(0x5)
#define I2S_RXCTRL_DATASIZE_8_Val _U_(0x6)
#define I2S_RXCTRL_DATASIZE_8C_Val _U_(0x7)
#define I2S_RXCTRL_DATASIZE_32 (I2S_RXCTRL_DATASIZE_32_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_24 (I2S_RXCTRL_DATASIZE_24_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_20 (I2S_RXCTRL_DATASIZE_20_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_18 (I2S_RXCTRL_DATASIZE_18_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_16 (I2S_RXCTRL_DATASIZE_16_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_16C (I2S_RXCTRL_DATASIZE_16C_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_8 (I2S_RXCTRL_DATASIZE_8_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_DATASIZE_8C (I2S_RXCTRL_DATASIZE_8C_Val << I2S_RXCTRL_DATASIZE_Pos)
#define I2S_RXCTRL_WORDADJ_Pos 12
#define I2S_RXCTRL_WORDADJ (_U_(0x1) << I2S_RXCTRL_WORDADJ_Pos)
#define I2S_RXCTRL_WORDADJ_RIGHT_Val _U_(0x0)
#define I2S_RXCTRL_WORDADJ_LEFT_Val _U_(0x1)
#define I2S_RXCTRL_WORDADJ_RIGHT (I2S_RXCTRL_WORDADJ_RIGHT_Val << I2S_RXCTRL_WORDADJ_Pos)
#define I2S_RXCTRL_WORDADJ_LEFT (I2S_RXCTRL_WORDADJ_LEFT_Val << I2S_RXCTRL_WORDADJ_Pos)
#define I2S_RXCTRL_EXTEND_Pos 13
#define I2S_RXCTRL_EXTEND_Msk (_U_(0x3) << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND(value) (I2S_RXCTRL_EXTEND_Msk & ((value) << I2S_RXCTRL_EXTEND_Pos))
#define I2S_RXCTRL_EXTEND_ZERO_Val _U_(0x0)
#define I2S_RXCTRL_EXTEND_ONE_Val _U_(0x1)
#define I2S_RXCTRL_EXTEND_MSBIT_Val _U_(0x2)
#define I2S_RXCTRL_EXTEND_LSBIT_Val _U_(0x3)
#define I2S_RXCTRL_EXTEND_ZERO (I2S_RXCTRL_EXTEND_ZERO_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND_ONE (I2S_RXCTRL_EXTEND_ONE_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND_MSBIT (I2S_RXCTRL_EXTEND_MSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_EXTEND_LSBIT (I2S_RXCTRL_EXTEND_LSBIT_Val << I2S_RXCTRL_EXTEND_Pos)
#define I2S_RXCTRL_BITREV_Pos 15
#define I2S_RXCTRL_BITREV (_U_(0x1) << I2S_RXCTRL_BITREV_Pos)
#define I2S_RXCTRL_BITREV_MSBIT_Val _U_(0x0)
#define I2S_RXCTRL_BITREV_LSBIT_Val _U_(0x1)
#define I2S_RXCTRL_BITREV_MSBIT (I2S_RXCTRL_BITREV_MSBIT_Val << I2S_RXCTRL_BITREV_Pos)
#define I2S_RXCTRL_BITREV_LSBIT (I2S_RXCTRL_BITREV_LSBIT_Val << I2S_RXCTRL_BITREV_Pos)
#define I2S_RXCTRL_SLOTDIS0_Pos 16
#define I2S_RXCTRL_SLOTDIS0 (_U_(1) << I2S_RXCTRL_SLOTDIS0_Pos)
#define I2S_RXCTRL_SLOTDIS1_Pos 17
#define I2S_RXCTRL_SLOTDIS1 (_U_(1) << I2S_RXCTRL_SLOTDIS1_Pos)
#define I2S_RXCTRL_SLOTDIS2_Pos 18
#define I2S_RXCTRL_SLOTDIS2 (_U_(1) << I2S_RXCTRL_SLOTDIS2_Pos)
#define I2S_RXCTRL_SLOTDIS3_Pos 19
#define I2S_RXCTRL_SLOTDIS3 (_U_(1) << I2S_RXCTRL_SLOTDIS3_Pos)
#define I2S_RXCTRL_SLOTDIS4_Pos 20
#define I2S_RXCTRL_SLOTDIS4 (_U_(1) << I2S_RXCTRL_SLOTDIS4_Pos)
#define I2S_RXCTRL_SLOTDIS5_Pos 21
#define I2S_RXCTRL_SLOTDIS5 (_U_(1) << I2S_RXCTRL_SLOTDIS5_Pos)
#define I2S_RXCTRL_SLOTDIS6_Pos 22
#define I2S_RXCTRL_SLOTDIS6 (_U_(1) << I2S_RXCTRL_SLOTDIS6_Pos)
#define I2S_RXCTRL_SLOTDIS7_Pos 23
#define I2S_RXCTRL_SLOTDIS7 (_U_(1) << I2S_RXCTRL_SLOTDIS7_Pos)
#define I2S_RXCTRL_SLOTDIS_Pos 16
#define I2S_RXCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_RXCTRL_SLOTDIS_Pos)
#define I2S_RXCTRL_SLOTDIS(value) (I2S_RXCTRL_SLOTDIS_Msk & ((value) << I2S_RXCTRL_SLOTDIS_Pos))
#define I2S_RXCTRL_MONO_Pos 24
#define I2S_RXCTRL_MONO (_U_(0x1) << I2S_RXCTRL_MONO_Pos)
#define I2S_RXCTRL_MONO_STEREO_Val _U_(0x0)
#define I2S_RXCTRL_MONO_MONO_Val _U_(0x1)
#define I2S_RXCTRL_MONO_STEREO (I2S_RXCTRL_MONO_STEREO_Val << I2S_RXCTRL_MONO_Pos)
#define I2S_RXCTRL_MONO_MONO (I2S_RXCTRL_MONO_MONO_Val << I2S_RXCTRL_MONO_Pos)
#define I2S_RXCTRL_DMA_Pos 25
#define I2S_RXCTRL_DMA (_U_(0x1) << I2S_RXCTRL_DMA_Pos)
#define I2S_RXCTRL_DMA_SINGLE_Val _U_(0x0)
#define I2S_RXCTRL_DMA_MULTIPLE_Val _U_(0x1)
#define I2S_RXCTRL_DMA_SINGLE (I2S_RXCTRL_DMA_SINGLE_Val << I2S_RXCTRL_DMA_Pos)
#define I2S_RXCTRL_DMA_MULTIPLE (I2S_RXCTRL_DMA_MULTIPLE_Val << I2S_RXCTRL_DMA_Pos)
#define I2S_RXCTRL_RXLOOP_Pos 26
#define I2S_RXCTRL_RXLOOP (_U_(0x1) << I2S_RXCTRL_RXLOOP_Pos)
#define I2S_RXCTRL_MASK _U_(0x07FFF7A3)
/* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32;
} bit;
uint32_t reg;
} I2S_TXDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_TXDATA_OFFSET 0x30
#define I2S_TXDATA_RESETVALUE _U_(0x00000000)
#define I2S_TXDATA_DATA_Pos 0
#define I2S_TXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_TXDATA_DATA_Pos)
#define I2S_TXDATA_DATA(value) (I2S_TXDATA_DATA_Msk & ((value) << I2S_TXDATA_DATA_Pos))
#define I2S_TXDATA_MASK _U_(0xFFFFFFFF)
/* -------- I2S_RXDATA : (I2S Offset: 0x34) (R/ 32) Rx Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32;
} bit;
uint32_t reg;
} I2S_RXDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_RXDATA_OFFSET 0x34
#define I2S_RXDATA_RESETVALUE _U_(0x00000000)
#define I2S_RXDATA_DATA_Pos 0
#define I2S_RXDATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_RXDATA_DATA_Pos)
#define I2S_RXDATA_DATA(value) (I2S_RXDATA_DATA_Msk & ((value) << I2S_RXDATA_DATA_Pos))
#define I2S_RXDATA_MASK _U_(0xFFFFFFFF)
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO I2S_CTRLA_Type CTRLA;
RoReg8 Reserved1[0x3];
__IO I2S_CLKCTRL_Type CLKCTRL[2];
__IO I2S_INTENCLR_Type INTENCLR;
RoReg8 Reserved2[0x2];
__IO I2S_INTENSET_Type INTENSET;
RoReg8 Reserved3[0x2];
__IO I2S_INTFLAG_Type INTFLAG;
RoReg8 Reserved4[0x2];
__I I2S_SYNCBUSY_Type SYNCBUSY;
RoReg8 Reserved5[0x6];
__IO I2S_TXCTRL_Type TXCTRL;
__IO I2S_RXCTRL_Type RXCTRL;
RoReg8 Reserved6[0x8];
__O I2S_TXDATA_Type TXDATA;
__I I2S_RXDATA_Type RXDATA;
} I2s;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME54_I2S_COMPONENT_ */
I2S_INTENSET_Type::RXOR1
uint16_t RXOR1
Definition: i2s.h:250
I2S_CTRLA_Type::CKEN
uint8_t CKEN
Definition: i2s.h:56
I2S_SYNCBUSY_Type::SWRST
uint16_t SWRST
Definition: i2s.h:374
I2S_INTENSET_Type::RXOR0
uint16_t RXOR0
Definition: i2s.h:249
I2S_TXCTRL_Type::reg
uint32_t reg
Definition: i2s.h:449
I2S_CLKCTRL_Type::MCKEN
uint32_t MCKEN
Definition: i2s.h:97
I2S_RXCTRL_Type::SLOTDIS
uint32_t SLOTDIS
Definition: i2s.h:581
I2S_INTFLAG_Type::TXRDY1
__I uint16_t TXRDY1
Definition: i2s.h:317
I2S_RXDATA_Type
Definition: i2s.h:707
I2s::RXCTRL
__IO I2S_RXCTRL_Type RXCTRL
Offset: 0x24 (R/W 32) Rx Serializer Control.
Definition: i2s.h:738
I2S_RXCTRL_Type::RXLOOP
uint32_t RXLOOP
Definition: i2s.h:576
I2S_INTENSET_Type::RXOR
uint16_t RXOR
Definition: i2s.h:262
I2S_TXCTRL_Type::WORDADJ
uint32_t WORDADJ
Definition: i2s.h:429
I2S_INTENCLR_Type::RXRDY0
uint16_t RXRDY0
Definition: i2s.h:182
I2S_RXCTRL_Type::BITREV
uint32_t BITREV
Definition: i2s.h:565
I2S_INTENCLR_Type
Definition: i2s.h:180
I2S_CLKCTRL_Type::MCKDIV
uint32_t MCKDIV
Definition: i2s.h:99
I2S_SYNCBUSY_Type::CKEN
uint16_t CKEN
Definition: i2s.h:387
I2S_CLKCTRL_Type::SCKSEL
uint32_t SCKSEL
Definition: i2s.h:94
I2S_INTENSET_Type::TXUR0
uint16_t TXUR0
Definition: i2s.h:255
I2S_CLKCTRL_Type::FSOUTINV
uint32_t FSOUTINV
Definition: i2s.h:93
I2S_INTENSET_Type::TXRDY1
uint16_t TXRDY1
Definition: i2s.h:253
I2S_RXCTRL_Type::SLOTDIS1
uint32_t SLOTDIS1
Definition: i2s.h:567
I2S_RXCTRL_Type::SLOTDIS2
uint32_t SLOTDIS2
Definition: i2s.h:568
I2S_INTFLAG_Type::TXUR0
__I uint16_t TXUR0
Definition: i2s.h:319
I2S_TXDATA_Type
Definition: i2s.h:689
I2S_INTFLAG_Type::reg
uint16_t reg
Definition: i2s.h:333
I2S_RXCTRL_Type::SLOTDIS6
uint32_t SLOTDIS6
Definition: i2s.h:572
I2S_RXCTRL_Type::CLKSEL
uint32_t CLKSEL
Definition: i2s.h:558
I2S_RXCTRL_Type::SERMODE
uint32_t SERMODE
Definition: i2s.h:556
I2S_CTRLA_Type
Definition: i2s.h:44
I2S_INTENSET_Type::RXRDY
uint16_t RXRDY
Definition: i2s.h:260
I2S_RXCTRL_Type::SLOTDIS7
uint32_t SLOTDIS7
Definition: i2s.h:573
I2S_INTFLAG_Type::RXOR0
__I uint16_t RXOR0
Definition: i2s.h:313
I2S_TXCTRL_Type::TXSAME
uint32_t TXSAME
Definition: i2s.h:424
I2S_INTFLAG_Type
Definition: i2s.h:308
I2S_INTENCLR_Type::TXRDY0
uint16_t TXRDY0
Definition: i2s.h:188
I2S_INTFLAG_Type::RXRDY1
__I uint16_t RXRDY1
Definition: i2s.h:311
I2S_CTRLA_Type::ENABLE
uint8_t ENABLE
Definition: i2s.h:47
I2S_RXCTRL_Type::DATASIZE
uint32_t DATASIZE
Definition: i2s.h:561
I2S_INTENCLR_Type::TXRDY1
uint16_t TXRDY1
Definition: i2s.h:189
I2S_TXCTRL_Type::SLOTDIS5
uint32_t SLOTDIS5
Definition: i2s.h:437
I2S_TXCTRL_Type::SLOTDIS
uint32_t SLOTDIS
Definition: i2s.h:446
I2S_SYNCBUSY_Type::RXEN
uint16_t RXEN
Definition: i2s.h:379
I2S_SYNCBUSY_Type::TXDATA
uint16_t TXDATA
Definition: i2s.h:381
I2S_RXCTRL_Type::SLOTADJ
uint32_t SLOTADJ
Definition: i2s.h:560
I2S_INTENCLR_Type::RXRDY1
uint16_t RXRDY1
Definition: i2s.h:183
I2S_RXCTRL_Type::MONO
uint32_t MONO
Definition: i2s.h:574
I2S_RXCTRL_Type
Definition: i2s.h:554
I2s::RXDATA
__I I2S_RXDATA_Type RXDATA
Offset: 0x34 (R/ 32) Rx Data.
Definition: i2s.h:741
I2S_RXCTRL_Type::DMA
uint32_t DMA
Definition: i2s.h:575
I2S_CLKCTRL_Type::reg
uint32_t reg
Definition: i2s.h:104
I2S_TXCTRL_Type::SLOTDIS3
uint32_t SLOTDIS3
Definition: i2s.h:435
I2S_RXDATA_Type::reg
uint32_t reg
Definition: i2s.h:711
I2S_INTFLAG_Type::RXRDY0
__I uint16_t RXRDY0
Definition: i2s.h:310
I2S_SYNCBUSY_Type::reg
uint16_t reg
Definition: i2s.h:390
I2S_TXCTRL_Type::EXTEND
uint32_t EXTEND
Definition: i2s.h:430
I2S_TXCTRL_Type::SLOTDIS7
uint32_t SLOTDIS7
Definition: i2s.h:439
I2S_SYNCBUSY_Type::CKEN0
uint16_t CKEN0
Definition: i2s.h:376
I2S_RXCTRL_Type::SLOTDIS5
uint32_t SLOTDIS5
Definition: i2s.h:571
I2S_SYNCBUSY_Type::TXEN
uint16_t TXEN
Definition: i2s.h:378
I2S_TXCTRL_Type
Definition: i2s.h:420
I2s::CTRLA
__IO I2S_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A.
Definition: i2s.h:726
I2S_INTENCLR_Type::TXUR0
uint16_t TXUR0
Definition: i2s.h:191
I2s::TXCTRL
__IO I2S_TXCTRL_Type TXCTRL
Offset: 0x20 (R/W 32) Tx Serializer Control.
Definition: i2s.h:737
I2S_INTFLAG_Type::RXRDY
__I uint16_t RXRDY
Definition: i2s.h:324
I2S_INTENSET_Type
Definition: i2s.h:244
I2S_INTENCLR_Type::TXUR
uint16_t TXUR
Definition: i2s.h:202
I2S_CTRLA_Type::TXEN
uint8_t TXEN
Definition: i2s.h:50
I2S_TXCTRL_Type::SLOTDIS4
uint32_t SLOTDIS4
Definition: i2s.h:436
I2S_RXDATA_Type::DATA
uint32_t DATA
Definition: i2s.h:709
I2S_TXCTRL_Type::SLOTDIS0
uint32_t SLOTDIS0
Definition: i2s.h:432
I2s::INTENSET
__IO I2S_INTENSET_Type INTENSET
Offset: 0x10 (R/W 16) Interrupt Enable Set.
Definition: i2s.h:731
I2S_INTENCLR_Type::TXRDY
uint16_t TXRDY
Definition: i2s.h:200
I2S_INTENSET_Type::RXRDY0
uint16_t RXRDY0
Definition: i2s.h:246
I2S_TXCTRL_Type::DATASIZE
uint32_t DATASIZE
Definition: i2s.h:427
I2S_SYNCBUSY_Type
Definition: i2s.h:372
I2S_RXCTRL_Type::WORDADJ
uint32_t WORDADJ
Definition: i2s.h:563
I2S_SYNCBUSY_Type::ENABLE
uint16_t ENABLE
Definition: i2s.h:375
I2s::INTFLAG
__IO I2S_INTFLAG_Type INTFLAG
Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear.
Definition: i2s.h:733
I2S_CLKCTRL_Type::FSINV
uint32_t FSINV
Definition: i2s.h:92
I2S_RXCTRL_Type::SLOTDIS3
uint32_t SLOTDIS3
Definition: i2s.h:569
I2S_TXCTRL_Type::TXDEFAULT
uint32_t TXDEFAULT
Definition: i2s.h:423
I2S_CTRLA_Type::reg
uint8_t reg
Definition: i2s.h:59
I2S_RXCTRL_Type::SLOTDIS0
uint32_t SLOTDIS0
Definition: i2s.h:566
I2S_TXCTRL_Type::BITREV
uint32_t BITREV
Definition: i2s.h:431
I2S_INTFLAG_Type::TXUR1
__I uint16_t TXUR1
Definition: i2s.h:320
I2S_RXCTRL_Type::SLOTDIS4
uint32_t SLOTDIS4
Definition: i2s.h:570
I2S_SYNCBUSY_Type::RXDATA
uint16_t RXDATA
Definition: i2s.h:382
I2S_INTENSET_Type::reg
uint16_t reg
Definition: i2s.h:269
I2S_INTENCLR_Type::TXUR1
uint16_t TXUR1
Definition: i2s.h:192
I2S_CLKCTRL_Type::SCKOUTINV
uint32_t SCKOUTINV
Definition: i2s.h:95
I2S_TXDATA_Type::reg
uint32_t reg
Definition: i2s.h:693
I2S_CTRLA_Type::SWRST
uint8_t SWRST
Definition: i2s.h:46
I2S_RXCTRL_Type::reg
uint32_t reg
Definition: i2s.h:584
I2S_INTENCLR_Type::RXOR0
uint16_t RXOR0
Definition: i2s.h:185
I2S_INTENCLR_Type::RXRDY
uint16_t RXRDY
Definition: i2s.h:196
I2S_INTENSET_Type::TXRDY
uint16_t TXRDY
Definition: i2s.h:264
I2S_CLKCTRL_Type
Definition: i2s.h:85
I2S_TXCTRL_Type::SLOTDIS6
uint32_t SLOTDIS6
Definition: i2s.h:438
I2S_CLKCTRL_Type::SLOTSIZE
uint32_t SLOTSIZE
Definition: i2s.h:87
I2S_INTFLAG_Type::TXRDY0
__I uint16_t TXRDY0
Definition: i2s.h:316
I2S_INTENSET_Type::TXUR
uint16_t TXUR
Definition: i2s.h:266
I2S_INTENCLR_Type::RXOR1
uint16_t RXOR1
Definition: i2s.h:186
I2S_CLKCTRL_Type::MCKOUTDIV
uint32_t MCKOUTDIV
Definition: i2s.h:101
I2S_CLKCTRL_Type::FSSEL
uint32_t FSSEL
Definition: i2s.h:91
I2S_INTFLAG_Type::uint16_t
__I uint16_t
Definition: i2s.h:312
I2S_INTFLAG_Type::TXRDY
__I uint16_t TXRDY
Definition: i2s.h:328
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
I2S_TXCTRL_Type::MONO
uint32_t MONO
Definition: i2s.h:440
I2S_RXCTRL_Type::EXTEND
uint32_t EXTEND
Definition: i2s.h:564
I2S_TXCTRL_Type::DMA
uint32_t DMA
Definition: i2s.h:441
I2S_TXCTRL_Type::SLOTADJ
uint32_t SLOTADJ
Definition: i2s.h:426
I2S_INTENSET_Type::TXRDY0
uint16_t TXRDY0
Definition: i2s.h:252
I2s
I2S hardware registers.
Definition: i2s.h:725
I2S_CLKCTRL_Type::FSWIDTH
uint32_t FSWIDTH
Definition: i2s.h:89
I2S_TXDATA_Type::DATA
uint32_t DATA
Definition: i2s.h:691
I2s::TXDATA
__O I2S_TXDATA_Type TXDATA
Offset: 0x30 ( /W 32) Tx Data.
Definition: i2s.h:740
I2S_INTENCLR_Type::reg
uint16_t reg
Definition: i2s.h:205
I2S_TXCTRL_Type::SLOTDIS1
uint32_t SLOTDIS1
Definition: i2s.h:433
I2S_INTENCLR_Type::RXOR
uint16_t RXOR
Definition: i2s.h:198
I2S_CLKCTRL_Type::MCKOUTINV
uint32_t MCKOUTINV
Definition: i2s.h:98
I2S_CLKCTRL_Type::NBSLOTS
uint32_t NBSLOTS
Definition: i2s.h:88
I2S_SYNCBUSY_Type::CKEN1
uint16_t CKEN1
Definition: i2s.h:377
I2S_CTRLA_Type::CKEN1
uint8_t CKEN1
Definition: i2s.h:49
I2s::SYNCBUSY
__I I2S_SYNCBUSY_Type SYNCBUSY
Offset: 0x18 (R/ 16) Synchronization Status.
Definition: i2s.h:735
I2S_CTRLA_Type::RXEN
uint8_t RXEN
Definition: i2s.h:51
I2S_CLKCTRL_Type::MCKSEL
uint32_t MCKSEL
Definition: i2s.h:96
I2S_INTFLAG_Type::RXOR1
__I uint16_t RXOR1
Definition: i2s.h:314
I2s::INTENCLR
__IO I2S_INTENCLR_Type INTENCLR
Offset: 0x0C (R/W 16) Interrupt Enable Clear.
Definition: i2s.h:729
I2S_CLKCTRL_Type::BITDELAY
uint32_t BITDELAY
Definition: i2s.h:90
I2S_TXCTRL_Type::SLOTDIS2
uint32_t SLOTDIS2
Definition: i2s.h:434
I2S_INTFLAG_Type::TXUR
__I uint16_t TXUR
Definition: i2s.h:330
I2S_CTRLA_Type::CKEN0
uint8_t CKEN0
Definition: i2s.h:48
I2S_INTFLAG_Type::RXOR
__I uint16_t RXOR
Definition: i2s.h:326
I2S_INTENSET_Type::RXRDY1
uint16_t RXRDY1
Definition: i2s.h:247
I2S_INTENSET_Type::TXUR1
uint16_t TXUR1
Definition: i2s.h:256