osc32kctrl.h
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#ifndef _SAME54_OSC32KCTRL_COMPONENT_
#define _SAME54_OSC32KCTRL_COMPONENT_
/* ========================================================================== */
/* ========================================================================== */
#define OSC32KCTRL_U2400
#define REV_OSC32KCTRL 0x100
/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1;
uint32_t :1;
uint32_t XOSC32KFAIL:1;
uint32_t :29;
} bit;
uint32_t reg;
} OSC32KCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTENCLR_OFFSET 0x00
#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000)
#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0
#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2
#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
#define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005)
/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1;
uint32_t :1;
uint32_t XOSC32KFAIL:1;
uint32_t :29;
} bit;
uint32_t reg;
} OSC32KCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTENSET_OFFSET 0x04
#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000)
#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0
#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2
#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
#define OSC32KCTRL_INTENSET_MASK _U_(0x00000005)
/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t XOSC32KRDY:1;
__I uint32_t :1;
__I uint32_t XOSC32KFAIL:1;
__I uint32_t :29;
} bit;
uint32_t reg;
} OSC32KCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTFLAG_OFFSET 0x08
#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000)
#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0
#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2
#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
#define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005)
/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1;
uint32_t :1;
uint32_t XOSC32KFAIL:1;
uint32_t XOSC32KSW:1;
uint32_t :28;
} bit;
uint32_t reg;
} OSC32KCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_STATUS_OFFSET 0x0C
#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000)
#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0
#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2
#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3
#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
#define OSC32KCTRL_STATUS_MASK _U_(0x0000000D)
/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RTCSEL:3;
uint8_t :5;
} bit;
uint8_t reg;
} OSC32KCTRL_RTCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_RTCCTRL_OFFSET 0x10
#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00)
#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0
#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0)
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5)
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_MASK _U_(0x07)
/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1;
uint16_t ENABLE:1;
uint16_t XTALEN:1;
uint16_t EN32K:1;
uint16_t EN1K:1;
uint16_t :1;
uint16_t RUNSTDBY:1;
uint16_t ONDEMAND:1;
uint16_t STARTUP:3;
uint16_t :1;
uint16_t WRTLOCK:1;
uint16_t CGM:2;
uint16_t :1;
} bit;
uint16_t reg;
} OSC32KCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_XOSC32K_OFFSET 0x14
#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080)
#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1
#define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2
#define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
#define OSC32KCTRL_XOSC32K_EN32K_Pos 3
#define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
#define OSC32KCTRL_XOSC32K_EN1K_Pos 4
#define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6
#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7
#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8
#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12
#define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
#define OSC32KCTRL_XOSC32K_CGM_Pos 13
#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1)
#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2)
#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
#define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE)
/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEN:1;
uint8_t SWBACK:1;
uint8_t CFDPRESC:1;
uint8_t :5;
} bit;
uint8_t reg;
} OSC32KCTRL_CFDCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_CFDCTRL_OFFSET 0x16
#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00)
#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0
#define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1
#define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2
#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
#define OSC32KCTRL_CFDCTRL_MASK _U_(0x07)
/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEO:1;
uint8_t :7;
} bit;
uint8_t reg;
} OSC32KCTRL_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_EVCTRL_OFFSET 0x17
#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00)
#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0
#define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
#define OSC32KCTRL_EVCTRL_MASK _U_(0x01)
/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1;
uint32_t EN32K:1;
uint32_t EN1K:1;
uint32_t :5;
uint32_t CALIB:6;
uint32_t :1;
uint32_t WRTLOCK:1;
uint32_t :16;
} bit;
uint32_t reg;
} OSC32KCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C
#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000)
#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1
#define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2
#define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8
#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15
#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
#define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06)
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO OSC32KCTRL_INTENCLR_Type INTENCLR;
__IO OSC32KCTRL_INTENSET_Type INTENSET;
__IO OSC32KCTRL_INTFLAG_Type INTFLAG;
__I OSC32KCTRL_STATUS_Type STATUS;
__IO OSC32KCTRL_RTCCTRL_Type RTCCTRL;
RoReg8 Reserved1[0x3];
__IO OSC32KCTRL_XOSC32K_Type XOSC32K;
__IO OSC32KCTRL_CFDCTRL_Type CFDCTRL;
__IO OSC32KCTRL_EVCTRL_Type EVCTRL;
RoReg8 Reserved2[0x4];
__IO OSC32KCTRL_OSCULP32K_Type OSCULP32K;
} Osc32kctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
OSC32KCTRL_INTFLAG_Type::uint32_t
__I uint32_t
Definition: osc32kctrl.h:91
OSC32KCTRL_INTFLAG_Type::reg
uint32_t reg
Definition: osc32kctrl.h:95
Osc32kctrl
OSC32KCTRL hardware registers.
Definition: osc32kctrl.h:286
OSC32KCTRL_STATUS_Type
Definition: osc32kctrl.h:110
OSC32KCTRL_XOSC32K_Type::reg
uint16_t reg
Definition: osc32kctrl.h:178
OSC32KCTRL_OSCULP32K_Type::CALIB
uint32_t CALIB
Definition: osc32kctrl.h:261
OSC32KCTRL_CFDCTRL_Type::reg
uint8_t reg
Definition: osc32kctrl.h:220
OSC32KCTRL_OSCULP32K_Type::reg
uint32_t reg
Definition: osc32kctrl.h:266
OSC32KCTRL_STATUS_Type::XOSC32KSW
uint32_t XOSC32KSW
Definition: osc32kctrl.h:115
Osc32kctrl::EVCTRL
__IO OSC32KCTRL_EVCTRL_Type EVCTRL
Offset: 0x17 (R/W 8) Event Control.
Definition: osc32kctrl.h:295
OSC32KCTRL_CFDCTRL_Type::CFDPRESC
uint8_t CFDPRESC
Definition: osc32kctrl.h:217
OSC32KCTRL_INTFLAG_Type
Definition: osc32kctrl.h:88
Osc32kctrl::STATUS
__I OSC32KCTRL_STATUS_Type STATUS
Offset: 0x0C (R/ 32) Power and Clocks Status.
Definition: osc32kctrl.h:290
Osc32kctrl::CFDCTRL
__IO OSC32KCTRL_CFDCTRL_Type CFDCTRL
Offset: 0x16 (R/W 8) Clock Failure Detector Control.
Definition: osc32kctrl.h:294
OSC32KCTRL_OSCULP32K_Type
Definition: osc32kctrl.h:255
OSC32KCTRL_CFDCTRL_Type::SWBACK
uint8_t SWBACK
Definition: osc32kctrl.h:216
OSC32KCTRL_INTENSET_Type::XOSC32KFAIL
uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:70
OSC32KCTRL_INTFLAG_Type::XOSC32KRDY
__I uint32_t XOSC32KRDY
Definition: osc32kctrl.h:90
OSC32KCTRL_OSCULP32K_Type::EN32K
uint32_t EN32K
Definition: osc32kctrl.h:258
OSC32KCTRL_OSCULP32K_Type::WRTLOCK
uint32_t WRTLOCK
Definition: osc32kctrl.h:263
OSC32KCTRL_XOSC32K_Type::RUNSTDBY
uint16_t RUNSTDBY
Definition: osc32kctrl.h:170
Osc32kctrl::INTFLAG
__IO OSC32KCTRL_INTFLAG_Type INTFLAG
Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear.
Definition: osc32kctrl.h:289
OSC32KCTRL_XOSC32K_Type::STARTUP
uint16_t STARTUP
Definition: osc32kctrl.h:172
Osc32kctrl::XOSC32K
__IO OSC32KCTRL_XOSC32K_Type XOSC32K
Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control.
Definition: osc32kctrl.h:293
OSC32KCTRL_XOSC32K_Type::ONDEMAND
uint16_t ONDEMAND
Definition: osc32kctrl.h:171
OSC32KCTRL_EVCTRL_Type
Definition: osc32kctrl.h:237
Osc32kctrl::RTCCTRL
__IO OSC32KCTRL_RTCCTRL_Type RTCCTRL
Offset: 0x10 (R/W 8) RTC Clock Selection.
Definition: osc32kctrl.h:291
OSC32KCTRL_XOSC32K_Type::CGM
uint16_t CGM
Definition: osc32kctrl.h:175
OSC32KCTRL_EVCTRL_Type::CFDEO
uint8_t CFDEO
Definition: osc32kctrl.h:239
OSC32KCTRL_STATUS_Type::XOSC32KRDY
uint32_t XOSC32KRDY
Definition: osc32kctrl.h:112
OSC32KCTRL_INTFLAG_Type::XOSC32KFAIL
__I uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:92
OSC32KCTRL_INTENCLR_Type::XOSC32KRDY
uint32_t XOSC32KRDY
Definition: osc32kctrl.h:46
OSC32KCTRL_RTCCTRL_Type::RTCSEL
uint8_t RTCSEL
Definition: osc32kctrl.h:137
Osc32kctrl::OSCULP32K
__IO OSC32KCTRL_OSCULP32K_Type OSCULP32K
Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control.
Definition: osc32kctrl.h:297
OSC32KCTRL_EVCTRL_Type::reg
uint8_t reg
Definition: osc32kctrl.h:242
OSC32KCTRL_INTENSET_Type::XOSC32KRDY
uint32_t XOSC32KRDY
Definition: osc32kctrl.h:68
OSC32KCTRL_XOSC32K_Type::EN32K
uint16_t EN32K
Definition: osc32kctrl.h:167
OSC32KCTRL_CFDCTRL_Type::CFDEN
uint8_t CFDEN
Definition: osc32kctrl.h:215
OSC32KCTRL_XOSC32K_Type::EN1K
uint16_t EN1K
Definition: osc32kctrl.h:168
OSC32KCTRL_INTENCLR_Type
Definition: osc32kctrl.h:44
OSC32KCTRL_XOSC32K_Type
Definition: osc32kctrl.h:162
OSC32KCTRL_OSCULP32K_Type::EN1K
uint32_t EN1K
Definition: osc32kctrl.h:259
OSC32KCTRL_STATUS_Type::XOSC32KFAIL
uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:114
OSC32KCTRL_INTENSET_Type::reg
uint32_t reg
Definition: osc32kctrl.h:73
OSC32KCTRL_STATUS_Type::reg
uint32_t reg
Definition: osc32kctrl.h:118
OSC32KCTRL_CFDCTRL_Type
Definition: osc32kctrl.h:213
OSC32KCTRL_RTCCTRL_Type::reg
uint8_t reg
Definition: osc32kctrl.h:140
Osc32kctrl::INTENSET
__IO OSC32KCTRL_INTENSET_Type INTENSET
Offset: 0x04 (R/W 32) Interrupt Enable Set.
Definition: osc32kctrl.h:288
Osc32kctrl::INTENCLR
__IO OSC32KCTRL_INTENCLR_Type INTENCLR
Offset: 0x00 (R/W 32) Interrupt Enable Clear.
Definition: osc32kctrl.h:287
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
OSC32KCTRL_RTCCTRL_Type
Definition: osc32kctrl.h:135
OSC32KCTRL_INTENCLR_Type::XOSC32KFAIL
uint32_t XOSC32KFAIL
Definition: osc32kctrl.h:48
OSC32KCTRL_XOSC32K_Type::XTALEN
uint16_t XTALEN
Definition: osc32kctrl.h:166
OSC32KCTRL_XOSC32K_Type::ENABLE
uint16_t ENABLE
Definition: osc32kctrl.h:165
OSC32KCTRL_XOSC32K_Type::WRTLOCK
uint16_t WRTLOCK
Definition: osc32kctrl.h:174
OSC32KCTRL_INTENSET_Type
Definition: osc32kctrl.h:66
OSC32KCTRL_INTENCLR_Type::reg
uint32_t reg
Definition: osc32kctrl.h:51