dsu.h
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#ifndef _SAME54_DSU_COMPONENT_
#define _SAME54_DSU_COMPONENT_
/* ========================================================================== */
/* ========================================================================== */
#define DSU_U2410
#define REV_DSU 0x100
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1;
uint8_t :1;
uint8_t CRC:1;
uint8_t MBIST:1;
uint8_t CE:1;
uint8_t :1;
uint8_t ARR:1;
uint8_t SMSA:1;
} bit;
uint8_t reg;
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CTRL_OFFSET 0x0000
#define DSU_CTRL_RESETVALUE _U_(0x00)
#define DSU_CTRL_SWRST_Pos 0
#define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos)
#define DSU_CTRL_CRC_Pos 2
#define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos)
#define DSU_CTRL_MBIST_Pos 3
#define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos)
#define DSU_CTRL_CE_Pos 4
#define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos)
#define DSU_CTRL_ARR_Pos 6
#define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos)
#define DSU_CTRL_SMSA_Pos 7
#define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos)
#define DSU_CTRL_MASK _U_(0xDD)
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1;
uint8_t CRSTEXT:1;
uint8_t BERR:1;
uint8_t FAIL:1;
uint8_t PERR:1;
uint8_t :3;
} bit;
uint8_t reg;
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_STATUSA_OFFSET 0x0001
#define DSU_STATUSA_RESETVALUE _U_(0x00)
#define DSU_STATUSA_DONE_Pos 0
#define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos)
#define DSU_STATUSA_CRSTEXT_Pos 1
#define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)
#define DSU_STATUSA_BERR_Pos 2
#define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos)
#define DSU_STATUSA_FAIL_Pos 3
#define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos)
#define DSU_STATUSA_PERR_Pos 4
#define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos)
#define DSU_STATUSA_MASK _U_(0x1F)
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PROT:1;
uint8_t DBGPRES:1;
uint8_t DCCD0:1;
uint8_t DCCD1:1;
uint8_t HPE:1;
uint8_t CELCK:1;
uint8_t :2;
} bit;
struct {
uint8_t :2;
uint8_t DCCD:2;
uint8_t :4;
} vec;
uint8_t reg;
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_STATUSB_OFFSET 0x0002
#define DSU_STATUSB_RESETVALUE _U_(0x00)
#define DSU_STATUSB_PROT_Pos 0
#define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos)
#define DSU_STATUSB_DBGPRES_Pos 1
#define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)
#define DSU_STATUSB_DCCD0_Pos 2
#define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos)
#define DSU_STATUSB_DCCD1_Pos 3
#define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos)
#define DSU_STATUSB_DCCD_Pos 2
#define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos)
#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
#define DSU_STATUSB_HPE_Pos 4
#define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos)
#define DSU_STATUSB_CELCK_Pos 5
#define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos)
#define DSU_STATUSB_MASK _U_(0x3F)
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AMOD:2;
uint32_t ADDR:30;
} bit;
uint32_t reg;
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ADDR_OFFSET 0x0004
#define DSU_ADDR_RESETVALUE _U_(0x00000000)
#define DSU_ADDR_AMOD_Pos 0
#define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos)
#define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
#define DSU_ADDR_ADDR_Pos 2
#define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
#define DSU_ADDR_MASK _U_(0xFFFFFFFF)
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2;
uint32_t LENGTH:30;
} bit;
uint32_t reg;
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_LENGTH_OFFSET 0x0008
#define DSU_LENGTH_RESETVALUE _U_(0x00000000)
#define DSU_LENGTH_LENGTH_Pos 2
#define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
#define DSU_LENGTH_MASK _U_(0xFFFFFFFC)
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32;
} bit;
uint32_t reg;
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DATA_OFFSET 0x000C
#define DSU_DATA_RESETVALUE _U_(0x00000000)
#define DSU_DATA_DATA_Pos 0
#define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
#define DSU_DATA_MASK _U_(0xFFFFFFFF)
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32;
} bit;
uint32_t reg;
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DCC_OFFSET 0x0010
#define DSU_DCC_RESETVALUE _U_(0x00000000)
#define DSU_DCC_DATA_Pos 0
#define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
#define DSU_DCC_MASK _U_(0xFFFFFFFF)
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DEVSEL:8;
uint32_t REVISION:4;
uint32_t DIE:4;
uint32_t SERIES:6;
uint32_t :1;
uint32_t FAMILY:5;
uint32_t PROCESSOR:4;
} bit;
uint32_t reg;
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DID_OFFSET 0x0018
#define DSU_DID_DEVSEL_Pos 0
#define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos)
#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
#define DSU_DID_REVISION_Pos 8
#define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos)
#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
#define DSU_DID_DIE_Pos 12
#define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos)
#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
#define DSU_DID_SERIES_Pos 16
#define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos)
#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
#define DSU_DID_SERIES_0_Val _U_(0x0)
#define DSU_DID_SERIES_1_Val _U_(0x1)
#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos)
#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos)
#define DSU_DID_FAMILY_Pos 23
#define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos)
#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
#define DSU_DID_FAMILY_0_Val _U_(0x0)
#define DSU_DID_FAMILY_1_Val _U_(0x1)
#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos)
#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos)
#define DSU_DID_PROCESSOR_Pos 28
#define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
#define DSU_DID_PROCESSOR_CM0P_Val _U_(0x1)
#define DSU_DID_PROCESSOR_CM23_Val _U_(0x2)
#define DSU_DID_PROCESSOR_CM3_Val _U_(0x3)
#define DSU_DID_PROCESSOR_CM4_Val _U_(0x5)
#define DSU_DID_PROCESSOR_CM4F_Val _U_(0x6)
#define DSU_DID_PROCESSOR_CM33_Val _U_(0x7)
#define DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_MASK _U_(0xFFBFFFFF)
/* -------- DSU_CFG : (DSU Offset: 0x001C) (R/W 32) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LQOS:2;
uint32_t DCCDMALEVEL:2;
uint32_t ETBRAMEN:1;
uint32_t :27;
} bit;
uint32_t reg;
} DSU_CFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CFG_OFFSET 0x001C
#define DSU_CFG_RESETVALUE _U_(0x00000002)
#define DSU_CFG_LQOS_Pos 0
#define DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos)
#define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos))
#define DSU_CFG_DCCDMALEVEL_Pos 2
#define DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos)
#define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos))
#define DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0)
#define DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1)
#define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos)
#define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos)
#define DSU_CFG_ETBRAMEN_Pos 4
#define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos)
#define DSU_CFG_MASK _U_(0x0000001F)
/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EPRES:1;
uint32_t FMT:1;
uint32_t :10;
uint32_t ADDOFF:20;
} bit;
uint32_t reg;
} DSU_ENTRY0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ENTRY0_OFFSET 0x1000
#define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002)
#define DSU_ENTRY0_EPRES_Pos 0
#define DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)
#define DSU_ENTRY0_FMT_Pos 1
#define DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos)
#define DSU_ENTRY0_ADDOFF_Pos 12
#define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)
#define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
#define DSU_ENTRY0_MASK _U_(0xFFFFF003)
/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/ 32) CoreSight ROM Table Entry 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg;
} DSU_ENTRY1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ENTRY1_OFFSET 0x1004
#define DSU_ENTRY1_RESETVALUE _U_(0x00000000)
#define DSU_ENTRY1_MASK _U_(0xFFFFFFFF)
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) CoreSight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t END:32;
} bit;
uint32_t reg;
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_END_OFFSET 0x1008
#define DSU_END_RESETVALUE _U_(0x00000000)
#define DSU_END_END_Pos 0
#define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos)
#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
#define DSU_END_MASK _U_(0xFFFFFFFF)
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) CoreSight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMEMP:1;
uint32_t :31;
} bit;
uint32_t reg;
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_MEMTYPE_OFFSET 0x1FCC
#define DSU_MEMTYPE_RESETVALUE _U_(0x00000000)
#define DSU_MEMTYPE_SMEMP_Pos 0
#define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)
#define DSU_MEMTYPE_MASK _U_(0x00000001)
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPCC:4;
uint32_t FKBC:4;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID4_OFFSET 0x1FD0
#define DSU_PID4_RESETVALUE _U_(0x00000000)
#define DSU_PID4_JEPCC_Pos 0
#define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos)
#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
#define DSU_PID4_FKBC_Pos 4
#define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos)
#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
#define DSU_PID4_MASK _U_(0x000000FF)
/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg;
} DSU_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID5_OFFSET 0x1FD4
#define DSU_PID5_RESETVALUE _U_(0x00000000)
#define DSU_PID5_MASK _U_(0x00000000)
/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg;
} DSU_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID6_OFFSET 0x1FD8
#define DSU_PID6_RESETVALUE _U_(0x00000000)
#define DSU_PID6_MASK _U_(0x00000000)
/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg;
} DSU_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID7_OFFSET 0x1FDC
#define DSU_PID7_RESETVALUE _U_(0x00000000)
#define DSU_PID7_MASK _U_(0x00000000)
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBL:8;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID0_OFFSET 0x1FE0
#define DSU_PID0_RESETVALUE _U_(0x000000D0)
#define DSU_PID0_PARTNBL_Pos 0
#define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)
#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
#define DSU_PID0_MASK _U_(0x000000FF)
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBH:4;
uint32_t JEPIDCL:4;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID1_OFFSET 0x1FE4
#define DSU_PID1_RESETVALUE _U_(0x000000FC)
#define DSU_PID1_PARTNBH_Pos 0
#define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos)
#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
#define DSU_PID1_JEPIDCL_Pos 4
#define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)
#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
#define DSU_PID1_MASK _U_(0x000000FF)
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPIDCH:3;
uint32_t JEPU:1;
uint32_t REVISION:4;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID2_OFFSET 0x1FE8
#define DSU_PID2_RESETVALUE _U_(0x00000009)
#define DSU_PID2_JEPIDCH_Pos 0
#define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)
#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
#define DSU_PID2_JEPU_Pos 3
#define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos)
#define DSU_PID2_REVISION_Pos 4
#define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos)
#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
#define DSU_PID2_MASK _U_(0x000000FF)
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CUSMOD:4;
uint32_t REVAND:4;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID3_OFFSET 0x1FEC
#define DSU_PID3_RESETVALUE _U_(0x00000000)
#define DSU_PID3_CUSMOD_Pos 0
#define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos)
#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
#define DSU_PID3_REVAND_Pos 4
#define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos)
#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
#define DSU_PID3_MASK _U_(0x000000FF)
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB0:8;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID0_OFFSET 0x1FF0
#define DSU_CID0_RESETVALUE _U_(0x0000000D)
#define DSU_CID0_PREAMBLEB0_Pos 0
#define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
#define DSU_CID0_MASK _U_(0x000000FF)
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLE:4;
uint32_t CCLASS:4;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID1_OFFSET 0x1FF4
#define DSU_CID1_RESETVALUE _U_(0x00000010)
#define DSU_CID1_PREAMBLE_Pos 0
#define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)
#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
#define DSU_CID1_CCLASS_Pos 4
#define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos)
#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
#define DSU_CID1_MASK _U_(0x000000FF)
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB2:8;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID2_OFFSET 0x1FF8
#define DSU_CID2_RESETVALUE _U_(0x00000005)
#define DSU_CID2_PREAMBLEB2_Pos 0
#define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
#define DSU_CID2_MASK _U_(0x000000FF)
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB3:8;
uint32_t :24;
} bit;
uint32_t reg;
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID3_OFFSET 0x1FFC
#define DSU_CID3_RESETVALUE _U_(0x000000B1)
#define DSU_CID3_PREAMBLEB3_Pos 0
#define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
#define DSU_CID3_MASK _U_(0x000000FF)
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O DSU_CTRL_Type CTRL;
__IO DSU_STATUSA_Type STATUSA;
__I DSU_STATUSB_Type STATUSB;
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR;
__IO DSU_LENGTH_Type LENGTH;
__IO DSU_DATA_Type DATA;
__IO DSU_DCC_Type DCC[2];
__I DSU_DID_Type DID;
__IO DSU_CFG_Type CFG;
RoReg8 Reserved2[0xFE0];
__I DSU_ENTRY0_Type ENTRY0;
__I DSU_ENTRY1_Type ENTRY1;
__I DSU_END_Type END;
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE;
__I DSU_PID4_Type PID4;
__I DSU_PID5_Type PID5;
__I DSU_PID6_Type PID6;
__I DSU_PID7_Type PID7;
__I DSU_PID0_Type PID0;
__I DSU_PID1_Type PID1;
__I DSU_PID2_Type PID2;
__I DSU_PID3_Type PID3;
__I DSU_CID0_Type CID0;
__I DSU_CID1_Type CID1;
__I DSU_CID2_Type CID2;
__I DSU_CID3_Type CID3;
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME54_DSU_COMPONENT_ */
DSU_DATA_Type::DATA
uint32_t DATA
Definition: dsu.h:192
DSU_CID3_Type
Definition: dsu.h:594
DSU_ADDR_Type::ADDR
uint32_t ADDR
Definition: dsu.h:152
DSU_PID1_Type::JEPIDCL
uint32_t JEPIDCL
Definition: dsu.h:464
Dsu::CID2
__I DSU_CID2_Type CID2
Offset: 0x1FF8 (R/ 32) Component Identification 2.
Definition: dsu.h:640
DSU_STATUSA_Type::BERR
uint8_t BERR
Definition: dsu.h:82
DSU_PID3_Type
Definition: dsu.h:510
Dsu::PID2
__I DSU_PID2_Type PID2
Offset: 0x1FE8 (R/ 32) Peripheral Identification 2.
Definition: dsu.h:636
DSU_CID1_Type::CCLASS
uint32_t CCLASS
Definition: dsu.h:555
DSU_ENTRY0_Type
Definition: dsu.h:314
DSU_PID3_Type::REVAND
uint32_t REVAND
Definition: dsu.h:513
DSU_CID0_Type
Definition: dsu.h:533
DSU_PID3_Type::reg
uint32_t reg
Definition: dsu.h:516
DSU_CTRL_Type::reg
uint8_t reg
Definition: dsu.h:55
Dsu::PID3
__I DSU_PID3_Type PID3
Offset: 0x1FEC (R/ 32) Peripheral Identification 3.
Definition: dsu.h:637
DSU_DID_Type::DIE
uint32_t DIE
Definition: dsu.h:230
DSU_PID0_Type
Definition: dsu.h:442
DSU_ADDR_Type::reg
uint32_t reg
Definition: dsu.h:154
DSU_CID2_Type::reg
uint32_t reg
Definition: dsu.h:580
DSU_MEMTYPE_Type::reg
uint32_t reg
Definition: dsu.h:373
DSU_CTRL_Type::CRC
uint8_t CRC
Definition: dsu.h:48
Dsu::STATUSB
__I DSU_STATUSB_Type STATUSB
Offset: 0x0002 (R/ 8) Status B.
Definition: dsu.h:616
Dsu::LENGTH
__IO DSU_LENGTH_Type LENGTH
Offset: 0x0008 (R/W 32) Length.
Definition: dsu.h:619
DSU_END_Type::END
uint32_t END
Definition: dsu.h:352
Dsu::ADDR
__IO DSU_ADDR_Type ADDR
Offset: 0x0004 (R/W 32) Address.
Definition: dsu.h:618
DSU_CID3_Type::reg
uint32_t reg
Definition: dsu.h:599
DSU_DID_Type::DEVSEL
uint32_t DEVSEL
Definition: dsu.h:228
Dsu::PID5
__I DSU_PID5_Type PID5
Offset: 0x1FD4 (R/ 32) Peripheral Identification 5.
Definition: dsu.h:631
DSU_ENTRY0_Type::FMT
uint32_t FMT
Definition: dsu.h:317
DSU_PID7_Type
Definition: dsu.h:431
Dsu::PID7
__I DSU_PID7_Type PID7
Offset: 0x1FDC (R/ 32) Peripheral Identification 7.
Definition: dsu.h:633
DSU_CID2_Type::PREAMBLEB2
uint32_t PREAMBLEB2
Definition: dsu.h:577
Dsu::CTRL
__O DSU_CTRL_Type CTRL
Offset: 0x0000 ( /W 8) Control.
Definition: dsu.h:614
DSU_PID6_Type::reg
uint32_t reg
Definition: dsu.h:421
DSU_PID5_Type::reg
uint32_t reg
Definition: dsu.h:410
DSU_PID4_Type::FKBC
uint32_t FKBC
Definition: dsu.h:389
Dsu::ENTRY1
__I DSU_ENTRY1_Type ENTRY1
Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1.
Definition: dsu.h:626
Dsu::PID0
__I DSU_PID0_Type PID0
Offset: 0x1FE0 (R/ 32) Peripheral Identification 0.
Definition: dsu.h:634
DSU_CID2_Type
Definition: dsu.h:575
DSU_CTRL_Type::ARR
uint8_t ARR
Definition: dsu.h:52
Dsu::CID1
__I DSU_CID1_Type CID1
Offset: 0x1FF4 (R/ 32) Component Identification 1.
Definition: dsu.h:639
DSU_PID2_Type::JEPU
uint32_t JEPU
Definition: dsu.h:487
DSU_PID2_Type
Definition: dsu.h:484
DSU_DCC_Type::reg
uint32_t reg
Definition: dsu.h:212
DSU_PID1_Type::PARTNBH
uint32_t PARTNBH
Definition: dsu.h:463
Dsu::DATA
__IO DSU_DATA_Type DATA
Offset: 0x000C (R/W 32) Data.
Definition: dsu.h:620
DSU_ENTRY0_Type::EPRES
uint32_t EPRES
Definition: dsu.h:316
DSU_STATUSB_Type::PROT
uint8_t PROT
Definition: dsu.h:110
Dsu::PID4
__I DSU_PID4_Type PID4
Offset: 0x1FD0 (R/ 32) Peripheral Identification 4.
Definition: dsu.h:630
DSU_STATUSA_Type::reg
uint8_t reg
Definition: dsu.h:87
DSU_PID6_Type
Definition: dsu.h:420
DSU_PID4_Type::JEPCC
uint32_t JEPCC
Definition: dsu.h:388
DSU_ENTRY1_Type
Definition: dsu.h:339
DSU_CTRL_Type::SMSA
uint8_t SMSA
Definition: dsu.h:53
DSU_PID0_Type::reg
uint32_t reg
Definition: dsu.h:447
DSU_CID3_Type::PREAMBLEB3
uint32_t PREAMBLEB3
Definition: dsu.h:596
DSU_CFG_Type::DCCDMALEVEL
uint32_t DCCDMALEVEL
Definition: dsu.h:287
DSU_PID2_Type::reg
uint32_t reg
Definition: dsu.h:491
Dsu::END
__I DSU_END_Type END
Offset: 0x1008 (R/ 32) CoreSight ROM Table End.
Definition: dsu.h:627
DSU_ADDR_Type
Definition: dsu.h:149
DSU_LENGTH_Type::reg
uint32_t reg
Definition: dsu.h:176
DSU_ENTRY0_Type::ADDOFF
uint32_t ADDOFF
Definition: dsu.h:319
DSU_STATUSB_Type::CELCK
uint8_t CELCK
Definition: dsu.h:115
DSU_CFG_Type::ETBRAMEN
uint32_t ETBRAMEN
Definition: dsu.h:288
DSU_PID5_Type
Definition: dsu.h:409
Dsu::ENTRY0
__I DSU_ENTRY0_Type ENTRY0
Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0.
Definition: dsu.h:625
DSU_PID2_Type::JEPIDCH
uint32_t JEPIDCH
Definition: dsu.h:486
DSU_CID0_Type::PREAMBLEB0
uint32_t PREAMBLEB0
Definition: dsu.h:535
DSU_STATUSB_Type::DBGPRES
uint8_t DBGPRES
Definition: dsu.h:111
DSU_STATUSA_Type::FAIL
uint8_t FAIL
Definition: dsu.h:83
DSU_LENGTH_Type::LENGTH
uint32_t LENGTH
Definition: dsu.h:174
DSU_ADDR_Type::AMOD
uint32_t AMOD
Definition: dsu.h:151
DSU_DID_Type::SERIES
uint32_t SERIES
Definition: dsu.h:231
Dsu::MEMTYPE
__I DSU_MEMTYPE_Type MEMTYPE
Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type.
Definition: dsu.h:629
DSU_MEMTYPE_Type
Definition: dsu.h:368
DSU_DCC_Type::DATA
uint32_t DATA
Definition: dsu.h:210
DSU_ENTRY0_Type::reg
uint32_t reg
Definition: dsu.h:321
DSU_STATUSB_Type::DCCD
uint8_t DCCD
Definition: dsu.h:120
DSU_DID_Type
Definition: dsu.h:226
DSU_DATA_Type
Definition: dsu.h:190
Dsu::PID6
__I DSU_PID6_Type PID6
Offset: 0x1FD8 (R/ 32) Peripheral Identification 6.
Definition: dsu.h:632
DSU_PID4_Type
Definition: dsu.h:386
DSU_CID1_Type::PREAMBLE
uint32_t PREAMBLE
Definition: dsu.h:554
DSU_PID0_Type::PARTNBL
uint32_t PARTNBL
Definition: dsu.h:444
DSU_PID2_Type::REVISION
uint32_t REVISION
Definition: dsu.h:488
DSU_STATUSB_Type
Definition: dsu.h:108
DSU_CTRL_Type::CE
uint8_t CE
Definition: dsu.h:50
DSU_PID3_Type::CUSMOD
uint32_t CUSMOD
Definition: dsu.h:512
DSU_PID7_Type::reg
uint32_t reg
Definition: dsu.h:432
DSU_STATUSB_Type::reg
uint8_t reg
Definition: dsu.h:123
DSU_LENGTH_Type
Definition: dsu.h:171
DSU_CFG_Type
Definition: dsu.h:284
DSU_DATA_Type::reg
uint32_t reg
Definition: dsu.h:194
DSU_DID_Type::REVISION
uint32_t REVISION
Definition: dsu.h:229
DSU_STATUSA_Type
Definition: dsu.h:78
DSU_PID1_Type::reg
uint32_t reg
Definition: dsu.h:467
DSU_STATUSA_Type::PERR
uint8_t PERR
Definition: dsu.h:84
DSU_CTRL_Type
Definition: dsu.h:44
DSU_CID0_Type::reg
uint32_t reg
Definition: dsu.h:538
DSU_DCC_Type
Definition: dsu.h:208
DSU_CFG_Type::reg
uint32_t reg
Definition: dsu.h:291
DSU_STATUSB_Type::HPE
uint8_t HPE
Definition: dsu.h:114
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
DSU_ENTRY1_Type::reg
uint32_t reg
Definition: dsu.h:340
DSU_PID4_Type::reg
uint32_t reg
Definition: dsu.h:392
DSU_CFG_Type::LQOS
uint32_t LQOS
Definition: dsu.h:286
DSU_DID_Type::reg
uint32_t reg
Definition: dsu.h:236
DSU_CID1_Type
Definition: dsu.h:552
Dsu
DSU hardware registers.
Definition: dsu.h:613
DSU_CTRL_Type::SWRST
uint8_t SWRST
Definition: dsu.h:46
Dsu::PID1
__I DSU_PID1_Type PID1
Offset: 0x1FE4 (R/ 32) Peripheral Identification 1.
Definition: dsu.h:635
Dsu::CID3
__I DSU_CID3_Type CID3
Offset: 0x1FFC (R/ 32) Component Identification 3.
Definition: dsu.h:641
DSU_PID1_Type
Definition: dsu.h:461
DSU_STATUSB_Type::DCCD1
uint8_t DCCD1
Definition: dsu.h:113
DSU_DID_Type::FAMILY
uint32_t FAMILY
Definition: dsu.h:233
DSU_STATUSB_Type::DCCD0
uint8_t DCCD0
Definition: dsu.h:112
DSU_CID1_Type::reg
uint32_t reg
Definition: dsu.h:558
DSU_END_Type
Definition: dsu.h:350
Dsu::STATUSA
__IO DSU_STATUSA_Type STATUSA
Offset: 0x0001 (R/W 8) Status A.
Definition: dsu.h:615
DSU_STATUSA_Type::DONE
uint8_t DONE
Definition: dsu.h:80
Dsu::CID0
__I DSU_CID0_Type CID0
Offset: 0x1FF0 (R/ 32) Component Identification 0.
Definition: dsu.h:638
Dsu::DID
__I DSU_DID_Type DID
Offset: 0x0018 (R/ 32) Device Identification.
Definition: dsu.h:622
DSU_STATUSA_Type::CRSTEXT
uint8_t CRSTEXT
Definition: dsu.h:81
DSU_MEMTYPE_Type::SMEMP
uint32_t SMEMP
Definition: dsu.h:370
DSU_DID_Type::PROCESSOR
uint32_t PROCESSOR
Definition: dsu.h:234
DSU_CTRL_Type::MBIST
uint8_t MBIST
Definition: dsu.h:49
DSU_END_Type::reg
uint32_t reg
Definition: dsu.h:354
Dsu::CFG
__IO DSU_CFG_Type CFG
Offset: 0x001C (R/W 32) Configuration.
Definition: dsu.h:623