pcc.h File Reference

Component description for PCC. More...

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## Data Structures

union | PCC_MR_Type
union | PCC_IER_Type
union | PCC_IDR_Type
union | PCC_IMR_Type
union | PCC_ISR_Type
union | PCC_RHR_Type
union | PCC_WPMR_Type
union | PCC_WPSR_Type
struct | Pcc
| PCC hardware registers. More...

## Macros

#define | PCC_U2017
#define | REV_PCC 0x110
#define | PCC_MR_OFFSET 0x00
| (PCC_MR offset) Mode Register
#define | PCC_MR_RESETVALUE _U_(0x00000000)
| (PCC_MR reset_value) Mode Register
#define | PCC_MR_PCEN_Pos 0
| (PCC_MR) Parallel Capture Enable
#define | PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos)
#define | PCC_MR_DSIZE_Pos 4
| (PCC_MR) Data size
#define | PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos)
#define | PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos))
#define | PCC_MR_SCALE_Pos 8
| (PCC_MR) Scale data
#define | PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos)
#define | PCC_MR_ALWYS_Pos 9
| (PCC_MR) Always Sampling
#define | PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos)
#define | PCC_MR_HALFS_Pos 10
| (PCC_MR) Half Sampling
#define | PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos)
#define | PCC_MR_FRSTS_Pos 11
| (PCC_MR) First sample
#define | PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos)
#define | PCC_MR_ISIZE_Pos 16
| (PCC_MR) Input Data Size
#define | PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos)
#define | PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos))
#define | PCC_MR_CID_Pos 30
| (PCC_MR) Clear If Disabled
#define | PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos)
#define | PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos))
#define | PCC_MR_MASK _U_(0xC0070F31)
| (PCC_MR) MASK Register
#define | PCC_IER_OFFSET 0x04
| (PCC_IER offset) Interrupt Enable Register
#define | PCC_IER_RESETVALUE _U_(0x00000000)
| (PCC_IER reset_value) Interrupt Enable Register
#define | PCC_IER_DRDY_Pos 0
| (PCC_IER) Data Ready Interrupt Enable
#define | PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos)
#define | PCC_IER_OVRE_Pos 1
| (PCC_IER) Overrun Error Interrupt Enable
#define | PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos)
#define | PCC_IER_MASK _U_(0x00000003)
| (PCC_IER) MASK Register
#define | PCC_IDR_OFFSET 0x08
| (PCC_IDR offset) Interrupt Disable Register
#define | PCC_IDR_RESETVALUE _U_(0x00000000)
| (PCC_IDR reset_value) Interrupt Disable Register
#define | PCC_IDR_DRDY_Pos 0
| (PCC_IDR) Data Ready Interrupt Disable
#define | PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos)
#define | PCC_IDR_OVRE_Pos 1
| (PCC_IDR) Overrun Error Interrupt Disable
#define | PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos)
#define | PCC_IDR_MASK _U_(0x00000003)
| (PCC_IDR) MASK Register
#define | PCC_IMR_OFFSET 0x0C
| (PCC_IMR offset) Interrupt Mask Register
#define | PCC_IMR_RESETVALUE _U_(0x00000000)
| (PCC_IMR reset_value) Interrupt Mask Register
#define | PCC_IMR_DRDY_Pos 0
| (PCC_IMR) Data Ready Interrupt Mask
#define | PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos)
#define | PCC_IMR_OVRE_Pos 1
| (PCC_IMR) Overrun Error Interrupt Mask
#define | PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos)
#define | PCC_IMR_MASK _U_(0x00000003)
| (PCC_IMR) MASK Register
#define | PCC_ISR_OFFSET 0x10
| (PCC_ISR offset) Interrupt Status Register
#define | PCC_ISR_RESETVALUE _U_(0x00000000)
| (PCC_ISR reset_value) Interrupt Status Register
#define | PCC_ISR_DRDY_Pos 0
| (PCC_ISR) Data Ready Interrupt Status
#define | PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos)
#define | PCC_ISR_OVRE_Pos 1
| (PCC_ISR) Overrun Error Interrupt Status
#define | PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos)
#define | PCC_ISR_MASK _U_(0x00000003)
| (PCC_ISR) MASK Register
#define | PCC_RHR_OFFSET 0x14
| (PCC_RHR offset) Reception Holding Register
#define | PCC_RHR_RESETVALUE _U_(0x00000000)
| (PCC_RHR reset_value) Reception Holding Register
#define | PCC_RHR_RDATA_Pos 0
| (PCC_RHR) Reception Data
#define | PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos)
#define | PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos))
#define | PCC_RHR_MASK _U_(0xFFFFFFFF)
| (PCC_RHR) MASK Register
#define | PCC_WPMR_OFFSET 0xE0
| (PCC_WPMR offset) Write Protection Mode Register
#define | PCC_WPMR_RESETVALUE _U_(0x00000000)
| (PCC_WPMR reset_value) Write Protection Mode Register
#define | PCC_WPMR_WPEN_Pos 0
| (PCC_WPMR) Write Protection Enable
#define | PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos)
#define | PCC_WPMR_WPKEY_Pos 8
| (PCC_WPMR) Write Protection Key
#define | PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos)
#define | PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos))
#define | PCC_WPMR_MASK _U_(0xFFFFFF01)
| (PCC_WPMR) MASK Register
#define | PCC_WPSR_OFFSET 0xE4
| (PCC_WPSR offset) Write Protection Status Register
#define | PCC_WPSR_RESETVALUE _U_(0x00000000)
| (PCC_WPSR reset_value) Write Protection Status Register
#define | PCC_WPSR_WPVS_Pos 0
| (PCC_WPSR) Write Protection Violation Source
#define | PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos)
#define | PCC_WPSR_WPVSRC_Pos 8
| (PCC_WPSR) Write Protection Violation Status
#define | PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos)
#define | PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos))
#define | PCC_WPSR_MASK _U_(0x00FFFF01)
| (PCC_WPSR) MASK Register

## Detailed Description

Component description for PCC.

Copyright (c) 2019 Microchip Technology Inc.

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Definition in file pcc.h.