SERCOM_SPI_INTENSET_Type Union Reference

## Data Fields

struct {
uint8_t DRE:1
uint8_t TXC:1
uint8_t RXC:1
uint8_t SSL:1
uint8_t __pad0__:3
uint8_t ERROR:1
} | bit
uint8_t | reg

## Detailed Description

Definition at line 834 of file sercom.h.

## Field Documentation

## __pad0__

uint8_t SERCOM_SPI_INTENSET_Type::__pad0__

bit: 4.. 6 Reserved

Definition at line 840 of file sercom.h.

## bit

struct { ... } SERCOM_SPI_INTENSET_Type::bit

Structure used for bit access

## DRE

uint8_t SERCOM_SPI_INTENSET_Type::DRE

bit: 0 Data Register Empty Interrupt Enable

Definition at line 836 of file sercom.h.

## ERROR

uint8_t SERCOM_SPI_INTENSET_Type::ERROR

bit: 7 Combined Error Interrupt Enable

Definition at line 841 of file sercom.h.

## reg

uint8_t SERCOM_SPI_INTENSET_Type::reg

Type used for register access

Definition at line 843 of file sercom.h.

## RXC

uint8_t SERCOM_SPI_INTENSET_Type::RXC

bit: 2 Receive Complete Interrupt Enable

Definition at line 838 of file sercom.h.

## SSL

uint8_t SERCOM_SPI_INTENSET_Type::SSL

bit: 3 Slave Select Low Interrupt Enable

Definition at line 839 of file sercom.h.

## TXC

uint8_t SERCOM_SPI_INTENSET_Type::TXC

bit: 1 Transmit Complete Interrupt Enable

Definition at line 837 of file sercom.h.

The documentation for this union was generated from the following file:

- /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/sercom.h