nvmctrl.h
Go to the documentation of this file.
#ifndef _SAME54_NVMCTRL_COMPONENT_
#define _SAME54_NVMCTRL_COMPONENT_
/* ========================================================================== */
/* ========================================================================== */
#define NVMCTRL_U2409
#define REV_NVMCTRL 0x100
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :2;
uint16_t AUTOWS:1;
uint16_t SUSPEN:1;
uint16_t WMODE:2;
uint16_t PRM:2;
uint16_t RWS:4;
uint16_t AHBNS0:1;
uint16_t AHBNS1:1;
uint16_t CACHEDIS0:1;
uint16_t CACHEDIS1:1;
} bit;
uint16_t reg;
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLA_OFFSET 0x00
#define NVMCTRL_CTRLA_RESETVALUE _U_(0x0004)
#define NVMCTRL_CTRLA_AUTOWS_Pos 2
#define NVMCTRL_CTRLA_AUTOWS (_U_(0x1) << NVMCTRL_CTRLA_AUTOWS_Pos)
#define NVMCTRL_CTRLA_SUSPEN_Pos 3
#define NVMCTRL_CTRLA_SUSPEN (_U_(0x1) << NVMCTRL_CTRLA_SUSPEN_Pos)
#define NVMCTRL_CTRLA_WMODE_Pos 4
#define NVMCTRL_CTRLA_WMODE_Msk (_U_(0x3) << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE(value) (NVMCTRL_CTRLA_WMODE_Msk & ((value) << NVMCTRL_CTRLA_WMODE_Pos))
#define NVMCTRL_CTRLA_WMODE_MAN_Val _U_(0x0)
#define NVMCTRL_CTRLA_WMODE_ADW_Val _U_(0x1)
#define NVMCTRL_CTRLA_WMODE_AQW_Val _U_(0x2)
#define NVMCTRL_CTRLA_WMODE_AP_Val _U_(0x3)
#define NVMCTRL_CTRLA_WMODE_MAN (NVMCTRL_CTRLA_WMODE_MAN_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE_ADW (NVMCTRL_CTRLA_WMODE_ADW_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE_AQW (NVMCTRL_CTRLA_WMODE_AQW_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_WMODE_AP (NVMCTRL_CTRLA_WMODE_AP_Val << NVMCTRL_CTRLA_WMODE_Pos)
#define NVMCTRL_CTRLA_PRM_Pos 6
#define NVMCTRL_CTRLA_PRM_Msk (_U_(0x3) << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_PRM(value) (NVMCTRL_CTRLA_PRM_Msk & ((value) << NVMCTRL_CTRLA_PRM_Pos))
#define NVMCTRL_CTRLA_PRM_SEMIAUTO_Val _U_(0x0)
#define NVMCTRL_CTRLA_PRM_FULLAUTO_Val _U_(0x1)
#define NVMCTRL_CTRLA_PRM_MANUAL_Val _U_(0x3)
#define NVMCTRL_CTRLA_PRM_SEMIAUTO (NVMCTRL_CTRLA_PRM_SEMIAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_PRM_FULLAUTO (NVMCTRL_CTRLA_PRM_FULLAUTO_Val << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_PRM_MANUAL (NVMCTRL_CTRLA_PRM_MANUAL_Val << NVMCTRL_CTRLA_PRM_Pos)
#define NVMCTRL_CTRLA_RWS_Pos 8
#define NVMCTRL_CTRLA_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLA_RWS_Pos)
#define NVMCTRL_CTRLA_RWS(value) (NVMCTRL_CTRLA_RWS_Msk & ((value) << NVMCTRL_CTRLA_RWS_Pos))
#define NVMCTRL_CTRLA_AHBNS0_Pos 12
#define NVMCTRL_CTRLA_AHBNS0 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS0_Pos)
#define NVMCTRL_CTRLA_AHBNS1_Pos 13
#define NVMCTRL_CTRLA_AHBNS1 (_U_(0x1) << NVMCTRL_CTRLA_AHBNS1_Pos)
#define NVMCTRL_CTRLA_CACHEDIS0_Pos 14
#define NVMCTRL_CTRLA_CACHEDIS0 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS0_Pos)
#define NVMCTRL_CTRLA_CACHEDIS1_Pos 15
#define NVMCTRL_CTRLA_CACHEDIS1 (_U_(0x1) << NVMCTRL_CTRLA_CACHEDIS1_Pos)
#define NVMCTRL_CTRLA_MASK _U_(0xFFFC)
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CMD:7;
uint16_t :1;
uint16_t CMDEX:8;
} bit;
uint16_t reg;
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLB_OFFSET 0x04
#define NVMCTRL_CTRLB_RESETVALUE _U_(0x0000)
#define NVMCTRL_CTRLB_CMD_Pos 0
#define NVMCTRL_CTRLB_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD(value) (NVMCTRL_CTRLB_CMD_Msk & ((value) << NVMCTRL_CTRLB_CMD_Pos))
#define NVMCTRL_CTRLB_CMD_EP_Val _U_(0x0)
#define NVMCTRL_CTRLB_CMD_EB_Val _U_(0x1)
#define NVMCTRL_CTRLB_CMD_WP_Val _U_(0x3)
#define NVMCTRL_CTRLB_CMD_WQW_Val _U_(0x4)
#define NVMCTRL_CTRLB_CMD_SWRST_Val _U_(0x10)
#define NVMCTRL_CTRLB_CMD_LR_Val _U_(0x11)
#define NVMCTRL_CTRLB_CMD_UR_Val _U_(0x12)
#define NVMCTRL_CTRLB_CMD_SPRM_Val _U_(0x13)
#define NVMCTRL_CTRLB_CMD_CPRM_Val _U_(0x14)
#define NVMCTRL_CTRLB_CMD_PBC_Val _U_(0x15)
#define NVMCTRL_CTRLB_CMD_SSB_Val _U_(0x16)
#define NVMCTRL_CTRLB_CMD_BKSWRST_Val _U_(0x17)
#define NVMCTRL_CTRLB_CMD_CELCK_Val _U_(0x18)
#define NVMCTRL_CTRLB_CMD_CEULCK_Val _U_(0x19)
#define NVMCTRL_CTRLB_CMD_SBPDIS_Val _U_(0x1A)
#define NVMCTRL_CTRLB_CMD_CBPDIS_Val _U_(0x1B)
#define NVMCTRL_CTRLB_CMD_ASEES0_Val _U_(0x30)
#define NVMCTRL_CTRLB_CMD_ASEES1_Val _U_(0x31)
#define NVMCTRL_CTRLB_CMD_SEERALOC_Val _U_(0x32)
#define NVMCTRL_CTRLB_CMD_SEEFLUSH_Val _U_(0x33)
#define NVMCTRL_CTRLB_CMD_LSEE_Val _U_(0x34)
#define NVMCTRL_CTRLB_CMD_USEE_Val _U_(0x35)
#define NVMCTRL_CTRLB_CMD_LSEER_Val _U_(0x36)
#define NVMCTRL_CTRLB_CMD_USEER_Val _U_(0x37)
#define NVMCTRL_CTRLB_CMD_EP (NVMCTRL_CTRLB_CMD_EP_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_EB (NVMCTRL_CTRLB_CMD_EB_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_WP (NVMCTRL_CTRLB_CMD_WP_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_WQW (NVMCTRL_CTRLB_CMD_WQW_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SWRST (NVMCTRL_CTRLB_CMD_SWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_LR (NVMCTRL_CTRLB_CMD_LR_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_UR (NVMCTRL_CTRLB_CMD_UR_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SPRM (NVMCTRL_CTRLB_CMD_SPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CPRM (NVMCTRL_CTRLB_CMD_CPRM_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_PBC (NVMCTRL_CTRLB_CMD_PBC_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SSB (NVMCTRL_CTRLB_CMD_SSB_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_BKSWRST (NVMCTRL_CTRLB_CMD_BKSWRST_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CELCK (NVMCTRL_CTRLB_CMD_CELCK_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CEULCK (NVMCTRL_CTRLB_CMD_CEULCK_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SBPDIS (NVMCTRL_CTRLB_CMD_SBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_CBPDIS (NVMCTRL_CTRLB_CMD_CBPDIS_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_ASEES0 (NVMCTRL_CTRLB_CMD_ASEES0_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_ASEES1 (NVMCTRL_CTRLB_CMD_ASEES1_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SEERALOC (NVMCTRL_CTRLB_CMD_SEERALOC_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_SEEFLUSH (NVMCTRL_CTRLB_CMD_SEEFLUSH_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_LSEE (NVMCTRL_CTRLB_CMD_LSEE_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_USEE (NVMCTRL_CTRLB_CMD_USEE_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_LSEER (NVMCTRL_CTRLB_CMD_LSEER_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMD_USEER (NVMCTRL_CTRLB_CMD_USEER_Val << NVMCTRL_CTRLB_CMD_Pos)
#define NVMCTRL_CTRLB_CMDEX_Pos 8
#define NVMCTRL_CTRLB_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLB_CMDEX_Pos)
#define NVMCTRL_CTRLB_CMDEX(value) (NVMCTRL_CTRLB_CMDEX_Msk & ((value) << NVMCTRL_CTRLB_CMDEX_Pos))
#define NVMCTRL_CTRLB_CMDEX_KEY_Val _U_(0xA5)
#define NVMCTRL_CTRLB_CMDEX_KEY (NVMCTRL_CTRLB_CMDEX_KEY_Val << NVMCTRL_CTRLB_CMDEX_Pos)
#define NVMCTRL_CTRLB_MASK _U_(0xFF7F)
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/ 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVMP:16;
uint32_t PSZ:3;
uint32_t :12;
uint32_t SEE:1;
} bit;
uint32_t reg;
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PARAM_OFFSET 0x08
#define NVMCTRL_PARAM_RESETVALUE _U_(0x00060000)
#define NVMCTRL_PARAM_NVMP_Pos 0
#define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
#define NVMCTRL_PARAM_PSZ_Pos 16
#define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
#define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0)
#define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1)
#define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2)
#define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3)
#define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4)
#define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5)
#define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6)
#define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7)
#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_SEE_Pos 31
#define NVMCTRL_PARAM_SEE (_U_(0x1) << NVMCTRL_PARAM_SEE_Pos)
#define NVMCTRL_PARAM_MASK _U_(0x8007FFFF)
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DONE:1;
uint16_t ADDRE:1;
uint16_t PROGE:1;
uint16_t LOCKE:1;
uint16_t ECCSE:1;
uint16_t ECCDE:1;
uint16_t NVME:1;
uint16_t SUSP:1;
uint16_t SEESFULL:1;
uint16_t SEESOVF:1;
uint16_t SEEWRC:1;
uint16_t :5;
} bit;
uint16_t reg;
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENCLR_OFFSET 0x0C
#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x0000)
#define NVMCTRL_INTENCLR_DONE_Pos 0
#define NVMCTRL_INTENCLR_DONE (_U_(0x1) << NVMCTRL_INTENCLR_DONE_Pos)
#define NVMCTRL_INTENCLR_ADDRE_Pos 1
#define NVMCTRL_INTENCLR_ADDRE (_U_(0x1) << NVMCTRL_INTENCLR_ADDRE_Pos)
#define NVMCTRL_INTENCLR_PROGE_Pos 2
#define NVMCTRL_INTENCLR_PROGE (_U_(0x1) << NVMCTRL_INTENCLR_PROGE_Pos)
#define NVMCTRL_INTENCLR_LOCKE_Pos 3
#define NVMCTRL_INTENCLR_LOCKE (_U_(0x1) << NVMCTRL_INTENCLR_LOCKE_Pos)
#define NVMCTRL_INTENCLR_ECCSE_Pos 4
#define NVMCTRL_INTENCLR_ECCSE (_U_(0x1) << NVMCTRL_INTENCLR_ECCSE_Pos)
#define NVMCTRL_INTENCLR_ECCDE_Pos 5
#define NVMCTRL_INTENCLR_ECCDE (_U_(0x1) << NVMCTRL_INTENCLR_ECCDE_Pos)
#define NVMCTRL_INTENCLR_NVME_Pos 6
#define NVMCTRL_INTENCLR_NVME (_U_(0x1) << NVMCTRL_INTENCLR_NVME_Pos)
#define NVMCTRL_INTENCLR_SUSP_Pos 7
#define NVMCTRL_INTENCLR_SUSP (_U_(0x1) << NVMCTRL_INTENCLR_SUSP_Pos)
#define NVMCTRL_INTENCLR_SEESFULL_Pos 8
#define NVMCTRL_INTENCLR_SEESFULL (_U_(0x1) << NVMCTRL_INTENCLR_SEESFULL_Pos)
#define NVMCTRL_INTENCLR_SEESOVF_Pos 9
#define NVMCTRL_INTENCLR_SEESOVF (_U_(0x1) << NVMCTRL_INTENCLR_SEESOVF_Pos)
#define NVMCTRL_INTENCLR_SEEWRC_Pos 10
#define NVMCTRL_INTENCLR_SEEWRC (_U_(0x1) << NVMCTRL_INTENCLR_SEEWRC_Pos)
#define NVMCTRL_INTENCLR_MASK _U_(0x07FF)
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DONE:1;
uint16_t ADDRE:1;
uint16_t PROGE:1;
uint16_t LOCKE:1;
uint16_t ECCSE:1;
uint16_t ECCDE:1;
uint16_t NVME:1;
uint16_t SUSP:1;
uint16_t SEESFULL:1;
uint16_t SEESOVF:1;
uint16_t SEEWRC:1;
uint16_t :5;
} bit;
uint16_t reg;
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENSET_OFFSET 0x0E
#define NVMCTRL_INTENSET_RESETVALUE _U_(0x0000)
#define NVMCTRL_INTENSET_DONE_Pos 0
#define NVMCTRL_INTENSET_DONE (_U_(0x1) << NVMCTRL_INTENSET_DONE_Pos)
#define NVMCTRL_INTENSET_ADDRE_Pos 1
#define NVMCTRL_INTENSET_ADDRE (_U_(0x1) << NVMCTRL_INTENSET_ADDRE_Pos)
#define NVMCTRL_INTENSET_PROGE_Pos 2
#define NVMCTRL_INTENSET_PROGE (_U_(0x1) << NVMCTRL_INTENSET_PROGE_Pos)
#define NVMCTRL_INTENSET_LOCKE_Pos 3
#define NVMCTRL_INTENSET_LOCKE (_U_(0x1) << NVMCTRL_INTENSET_LOCKE_Pos)
#define NVMCTRL_INTENSET_ECCSE_Pos 4
#define NVMCTRL_INTENSET_ECCSE (_U_(0x1) << NVMCTRL_INTENSET_ECCSE_Pos)
#define NVMCTRL_INTENSET_ECCDE_Pos 5
#define NVMCTRL_INTENSET_ECCDE (_U_(0x1) << NVMCTRL_INTENSET_ECCDE_Pos)
#define NVMCTRL_INTENSET_NVME_Pos 6
#define NVMCTRL_INTENSET_NVME (_U_(0x1) << NVMCTRL_INTENSET_NVME_Pos)
#define NVMCTRL_INTENSET_SUSP_Pos 7
#define NVMCTRL_INTENSET_SUSP (_U_(0x1) << NVMCTRL_INTENSET_SUSP_Pos)
#define NVMCTRL_INTENSET_SEESFULL_Pos 8
#define NVMCTRL_INTENSET_SEESFULL (_U_(0x1) << NVMCTRL_INTENSET_SEESFULL_Pos)
#define NVMCTRL_INTENSET_SEESOVF_Pos 9
#define NVMCTRL_INTENSET_SEESOVF (_U_(0x1) << NVMCTRL_INTENSET_SEESOVF_Pos)
#define NVMCTRL_INTENSET_SEEWRC_Pos 10
#define NVMCTRL_INTENSET_SEEWRC (_U_(0x1) << NVMCTRL_INTENSET_SEEWRC_Pos)
#define NVMCTRL_INTENSET_MASK _U_(0x07FF)
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint16_t DONE:1;
__I uint16_t ADDRE:1;
__I uint16_t PROGE:1;
__I uint16_t LOCKE:1;
__I uint16_t ECCSE:1;
__I uint16_t ECCDE:1;
__I uint16_t NVME:1;
__I uint16_t SUSP:1;
__I uint16_t SEESFULL:1;
__I uint16_t SEESOVF:1;
__I uint16_t SEEWRC:1;
__I uint16_t :5;
} bit;
uint16_t reg;
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTFLAG_OFFSET 0x10
#define NVMCTRL_INTFLAG_RESETVALUE _U_(0x0000)
#define NVMCTRL_INTFLAG_DONE_Pos 0
#define NVMCTRL_INTFLAG_DONE (_U_(0x1) << NVMCTRL_INTFLAG_DONE_Pos)
#define NVMCTRL_INTFLAG_ADDRE_Pos 1
#define NVMCTRL_INTFLAG_ADDRE (_U_(0x1) << NVMCTRL_INTFLAG_ADDRE_Pos)
#define NVMCTRL_INTFLAG_PROGE_Pos 2
#define NVMCTRL_INTFLAG_PROGE (_U_(0x1) << NVMCTRL_INTFLAG_PROGE_Pos)
#define NVMCTRL_INTFLAG_LOCKE_Pos 3
#define NVMCTRL_INTFLAG_LOCKE (_U_(0x1) << NVMCTRL_INTFLAG_LOCKE_Pos)
#define NVMCTRL_INTFLAG_ECCSE_Pos 4
#define NVMCTRL_INTFLAG_ECCSE (_U_(0x1) << NVMCTRL_INTFLAG_ECCSE_Pos)
#define NVMCTRL_INTFLAG_ECCDE_Pos 5
#define NVMCTRL_INTFLAG_ECCDE (_U_(0x1) << NVMCTRL_INTFLAG_ECCDE_Pos)
#define NVMCTRL_INTFLAG_NVME_Pos 6
#define NVMCTRL_INTFLAG_NVME (_U_(0x1) << NVMCTRL_INTFLAG_NVME_Pos)
#define NVMCTRL_INTFLAG_SUSP_Pos 7
#define NVMCTRL_INTFLAG_SUSP (_U_(0x1) << NVMCTRL_INTFLAG_SUSP_Pos)
#define NVMCTRL_INTFLAG_SEESFULL_Pos 8
#define NVMCTRL_INTFLAG_SEESFULL (_U_(0x1) << NVMCTRL_INTFLAG_SEESFULL_Pos)
#define NVMCTRL_INTFLAG_SEESOVF_Pos 9
#define NVMCTRL_INTFLAG_SEESOVF (_U_(0x1) << NVMCTRL_INTFLAG_SEESOVF_Pos)
#define NVMCTRL_INTFLAG_SEEWRC_Pos 10
#define NVMCTRL_INTFLAG_SEEWRC (_U_(0x1) << NVMCTRL_INTFLAG_SEEWRC_Pos)
#define NVMCTRL_INTFLAG_MASK _U_(0x07FF)
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) (R/ 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t READY:1;
uint16_t PRM:1;
uint16_t LOAD:1;
uint16_t SUSP:1;
uint16_t AFIRST:1;
uint16_t BPDIS:1;
uint16_t :2;
uint16_t BOOTPROT:4;
uint16_t :4;
} bit;
uint16_t reg;
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_STATUS_OFFSET 0x12
#define NVMCTRL_STATUS_RESETVALUE _U_(0x0000)
#define NVMCTRL_STATUS_READY_Pos 0
#define NVMCTRL_STATUS_READY (_U_(0x1) << NVMCTRL_STATUS_READY_Pos)
#define NVMCTRL_STATUS_PRM_Pos 1
#define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
#define NVMCTRL_STATUS_LOAD_Pos 2
#define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
#define NVMCTRL_STATUS_SUSP_Pos 3
#define NVMCTRL_STATUS_SUSP (_U_(0x1) << NVMCTRL_STATUS_SUSP_Pos)
#define NVMCTRL_STATUS_AFIRST_Pos 4
#define NVMCTRL_STATUS_AFIRST (_U_(0x1) << NVMCTRL_STATUS_AFIRST_Pos)
#define NVMCTRL_STATUS_BPDIS_Pos 5
#define NVMCTRL_STATUS_BPDIS (_U_(0x1) << NVMCTRL_STATUS_BPDIS_Pos)
#define NVMCTRL_STATUS_BOOTPROT_Pos 8
#define NVMCTRL_STATUS_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_STATUS_BOOTPROT_Pos)
#define NVMCTRL_STATUS_BOOTPROT(value) (NVMCTRL_STATUS_BOOTPROT_Msk & ((value) << NVMCTRL_STATUS_BOOTPROT_Pos))
#define NVMCTRL_STATUS_MASK _U_(0x0F3F)
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:24;
uint32_t :8;
} bit;
uint32_t reg;
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_ADDR_OFFSET 0x14
#define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000)
#define NVMCTRL_ADDR_ADDR_Pos 0
#define NVMCTRL_ADDR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ADDR_ADDR_Pos)
#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
#define NVMCTRL_ADDR_MASK _U_(0x00FFFFFF)
/* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) (R/ 32) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RUNLOCK:32;
} bit;
uint32_t reg;
} NVMCTRL_RUNLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_RUNLOCK_OFFSET 0x18
#define NVMCTRL_RUNLOCK_RESETVALUE _U_(0x00000000)
#define NVMCTRL_RUNLOCK_RUNLOCK_Pos 0
#define NVMCTRL_RUNLOCK_RUNLOCK_Msk (_U_(0xFFFFFFFF) << NVMCTRL_RUNLOCK_RUNLOCK_Pos)
#define NVMCTRL_RUNLOCK_RUNLOCK(value) (NVMCTRL_RUNLOCK_RUNLOCK_Msk & ((value) << NVMCTRL_RUNLOCK_RUNLOCK_Pos))
#define NVMCTRL_RUNLOCK_MASK _U_(0xFFFFFFFF)
/* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) (R/ 32) Page Buffer Load Data x -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32;
} bit;
uint32_t reg;
} NVMCTRL_PBLDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PBLDATA_OFFSET 0x1C
#define NVMCTRL_PBLDATA_RESETVALUE _U_(0xFFFFFFFF)
#define NVMCTRL_PBLDATA_DATA_Pos 0
#define NVMCTRL_PBLDATA_DATA_Msk (_U_(0xFFFFFFFF) << NVMCTRL_PBLDATA_DATA_Pos)
#define NVMCTRL_PBLDATA_DATA(value) (NVMCTRL_PBLDATA_DATA_Msk & ((value) << NVMCTRL_PBLDATA_DATA_Pos))
#define NVMCTRL_PBLDATA_MASK _U_(0xFFFFFFFF)
/* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) (R/ 32) ECC Error Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:24;
uint32_t :4;
uint32_t TYPEL:2;
uint32_t TYPEH:2;
} bit;
uint32_t reg;
} NVMCTRL_ECCERR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_ECCERR_OFFSET 0x24
#define NVMCTRL_ECCERR_RESETVALUE _U_(0x00000000)
#define NVMCTRL_ECCERR_ADDR_Pos 0
#define NVMCTRL_ECCERR_ADDR_Msk (_U_(0xFFFFFF) << NVMCTRL_ECCERR_ADDR_Pos)
#define NVMCTRL_ECCERR_ADDR(value) (NVMCTRL_ECCERR_ADDR_Msk & ((value) << NVMCTRL_ECCERR_ADDR_Pos))
#define NVMCTRL_ECCERR_TYPEL_Pos 28
#define NVMCTRL_ECCERR_TYPEL_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEL(value) (NVMCTRL_ECCERR_TYPEL_Msk & ((value) << NVMCTRL_ECCERR_TYPEL_Pos))
#define NVMCTRL_ECCERR_TYPEL_NONE_Val _U_(0x0)
#define NVMCTRL_ECCERR_TYPEL_SINGLE_Val _U_(0x1)
#define NVMCTRL_ECCERR_TYPEL_DUAL_Val _U_(0x2)
#define NVMCTRL_ECCERR_TYPEL_NONE (NVMCTRL_ECCERR_TYPEL_NONE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEL_SINGLE (NVMCTRL_ECCERR_TYPEL_SINGLE_Val << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEL_DUAL (NVMCTRL_ECCERR_TYPEL_DUAL_Val << NVMCTRL_ECCERR_TYPEL_Pos)
#define NVMCTRL_ECCERR_TYPEH_Pos 30
#define NVMCTRL_ECCERR_TYPEH_Msk (_U_(0x3) << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_TYPEH(value) (NVMCTRL_ECCERR_TYPEH_Msk & ((value) << NVMCTRL_ECCERR_TYPEH_Pos))
#define NVMCTRL_ECCERR_TYPEH_NONE_Val _U_(0x0)
#define NVMCTRL_ECCERR_TYPEH_SINGLE_Val _U_(0x1)
#define NVMCTRL_ECCERR_TYPEH_DUAL_Val _U_(0x2)
#define NVMCTRL_ECCERR_TYPEH_NONE (NVMCTRL_ECCERR_TYPEH_NONE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_TYPEH_SINGLE (NVMCTRL_ECCERR_TYPEH_SINGLE_Val << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_TYPEH_DUAL (NVMCTRL_ECCERR_TYPEH_DUAL_Val << NVMCTRL_ECCERR_TYPEH_Pos)
#define NVMCTRL_ECCERR_MASK _U_(0xF0FFFFFF)
/* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ECCDIS:1;
uint8_t ECCELOG:1;
uint8_t :6;
} bit;
uint8_t reg;
} NVMCTRL_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_DBGCTRL_OFFSET 0x28
#define NVMCTRL_DBGCTRL_RESETVALUE _U_(0x00)
#define NVMCTRL_DBGCTRL_ECCDIS_Pos 0
#define NVMCTRL_DBGCTRL_ECCDIS (_U_(0x1) << NVMCTRL_DBGCTRL_ECCDIS_Pos)
#define NVMCTRL_DBGCTRL_ECCELOG_Pos 1
#define NVMCTRL_DBGCTRL_ECCELOG (_U_(0x1) << NVMCTRL_DBGCTRL_ECCELOG_Pos)
#define NVMCTRL_DBGCTRL_MASK _U_(0x03)
/* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W 8) SmartEEPROM Configuration Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WMODE:1;
uint8_t APRDIS:1;
uint8_t :6;
} bit;
uint8_t reg;
} NVMCTRL_SEECFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_SEECFG_OFFSET 0x2A
#define NVMCTRL_SEECFG_RESETVALUE _U_(0x00)
#define NVMCTRL_SEECFG_WMODE_Pos 0
#define NVMCTRL_SEECFG_WMODE (_U_(0x1) << NVMCTRL_SEECFG_WMODE_Pos)
#define NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val _U_(0x0)
#define NVMCTRL_SEECFG_WMODE_BUFFERED_Val _U_(0x1)
#define NVMCTRL_SEECFG_WMODE_UNBUFFERED (NVMCTRL_SEECFG_WMODE_UNBUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
#define NVMCTRL_SEECFG_WMODE_BUFFERED (NVMCTRL_SEECFG_WMODE_BUFFERED_Val << NVMCTRL_SEECFG_WMODE_Pos)
#define NVMCTRL_SEECFG_APRDIS_Pos 1
#define NVMCTRL_SEECFG_APRDIS (_U_(0x1) << NVMCTRL_SEECFG_APRDIS_Pos)
#define NVMCTRL_SEECFG_MASK _U_(0x03)
/* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) (R/ 32) SmartEEPROM Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ASEES:1;
uint32_t LOAD:1;
uint32_t BUSY:1;
uint32_t LOCK:1;
uint32_t RLOCK:1;
uint32_t :3;
uint32_t SBLK:4;
uint32_t :4;
uint32_t PSZ:3;
uint32_t :13;
} bit;
uint32_t reg;
} NVMCTRL_SEESTAT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_SEESTAT_OFFSET 0x2C
#define NVMCTRL_SEESTAT_RESETVALUE _U_(0x00000000)
#define NVMCTRL_SEESTAT_ASEES_Pos 0
#define NVMCTRL_SEESTAT_ASEES (_U_(0x1) << NVMCTRL_SEESTAT_ASEES_Pos)
#define NVMCTRL_SEESTAT_LOAD_Pos 1
#define NVMCTRL_SEESTAT_LOAD (_U_(0x1) << NVMCTRL_SEESTAT_LOAD_Pos)
#define NVMCTRL_SEESTAT_BUSY_Pos 2
#define NVMCTRL_SEESTAT_BUSY (_U_(0x1) << NVMCTRL_SEESTAT_BUSY_Pos)
#define NVMCTRL_SEESTAT_LOCK_Pos 3
#define NVMCTRL_SEESTAT_LOCK (_U_(0x1) << NVMCTRL_SEESTAT_LOCK_Pos)
#define NVMCTRL_SEESTAT_RLOCK_Pos 4
#define NVMCTRL_SEESTAT_RLOCK (_U_(0x1) << NVMCTRL_SEESTAT_RLOCK_Pos)
#define NVMCTRL_SEESTAT_SBLK_Pos 8
#define NVMCTRL_SEESTAT_SBLK_Msk (_U_(0xF) << NVMCTRL_SEESTAT_SBLK_Pos)
#define NVMCTRL_SEESTAT_SBLK(value) (NVMCTRL_SEESTAT_SBLK_Msk & ((value) << NVMCTRL_SEESTAT_SBLK_Pos))
#define NVMCTRL_SEESTAT_PSZ_Pos 16
#define NVMCTRL_SEESTAT_PSZ_Msk (_U_(0x7) << NVMCTRL_SEESTAT_PSZ_Pos)
#define NVMCTRL_SEESTAT_PSZ(value) (NVMCTRL_SEESTAT_PSZ_Msk & ((value) << NVMCTRL_SEESTAT_PSZ_Pos))
#define NVMCTRL_SEESTAT_MASK _U_(0x00070F1F)
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO NVMCTRL_CTRLA_Type CTRLA;
RoReg8 Reserved1[0x2];
__O NVMCTRL_CTRLB_Type CTRLB;
RoReg8 Reserved2[0x2];
__I NVMCTRL_PARAM_Type PARAM;
__IO NVMCTRL_INTENCLR_Type INTENCLR;
__IO NVMCTRL_INTENSET_Type INTENSET;
__IO NVMCTRL_INTFLAG_Type INTFLAG;
__I NVMCTRL_STATUS_Type STATUS;
__IO NVMCTRL_ADDR_Type ADDR;
__I NVMCTRL_RUNLOCK_Type RUNLOCK;
__I NVMCTRL_PBLDATA_Type PBLDATA[2];
__I NVMCTRL_ECCERR_Type ECCERR;
__IO NVMCTRL_DBGCTRL_Type DBGCTRL;
RoReg8 Reserved3[0x1];
__IO NVMCTRL_SEECFG_Type SEECFG;
RoReg8 Reserved4[0x1];
__I NVMCTRL_SEESTAT_Type SEESTAT;
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_SW0
#define SECTION_NVMCTRL_TEMP_LOG
#define SECTION_NVMCTRL_USER
/* ************************************************************************** */
/* ************************************************************************** */
#define AC_FUSES_BIAS0_ADDR NVMCTRL_SW0
#define AC_FUSES_BIAS0_Pos 0
#define AC_FUSES_BIAS0_Msk (_U_(0x3) << AC_FUSES_BIAS0_Pos)
#define AC_FUSES_BIAS0(value) (AC_FUSES_BIAS0_Msk & ((value) << AC_FUSES_BIAS0_Pos))
#define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
#define ADC0_FUSES_BIASCOMP_Pos 2
#define ADC0_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos)
#define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos))
#define ADC0_FUSES_BIASR2R_ADDR NVMCTRL_SW0
#define ADC0_FUSES_BIASR2R_Pos 8
#define ADC0_FUSES_BIASR2R_Msk (_U_(0x7) << ADC0_FUSES_BIASR2R_Pos)
#define ADC0_FUSES_BIASR2R(value) (ADC0_FUSES_BIASR2R_Msk & ((value) << ADC0_FUSES_BIASR2R_Pos))
#define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
#define ADC0_FUSES_BIASREFBUF_Pos 5
#define ADC0_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos)
#define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos))
#define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_SW0
#define ADC1_FUSES_BIASCOMP_Pos 16
#define ADC1_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos)
#define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos))
#define ADC1_FUSES_BIASR2R_ADDR NVMCTRL_SW0
#define ADC1_FUSES_BIASR2R_Pos 22
#define ADC1_FUSES_BIASR2R_Msk (_U_(0x7) << ADC1_FUSES_BIASR2R_Pos)
#define ADC1_FUSES_BIASR2R(value) (ADC1_FUSES_BIASR2R_Msk & ((value) << ADC1_FUSES_BIASR2R_Pos))
#define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_SW0
#define ADC1_FUSES_BIASREFBUF_Pos 19
#define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
#define FUSES_BOD33USERLEVEL_Pos 1
#define FUSES_BOD33USERLEVEL_Msk (_U_(0xFF) << FUSES_BOD33USERLEVEL_Pos)
#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
#define FUSES_BOD33_ACTION_Pos 9
#define FUSES_BOD33_ACTION_Msk (_U_(0x3) << FUSES_BOD33_ACTION_Pos)
#define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
#define FUSES_BOD33_DIS_ADDR NVMCTRL_USER
#define FUSES_BOD33_DIS_Pos 0
#define FUSES_BOD33_DIS_Msk (_U_(0x1) << FUSES_BOD33_DIS_Pos)
#define FUSES_BOD33_HYST_ADDR NVMCTRL_USER
#define FUSES_BOD33_HYST_Pos 11
#define FUSES_BOD33_HYST_Msk (_U_(0xF) << FUSES_BOD33_HYST_Pos)
#define FUSES_BOD33_HYST(value) (FUSES_BOD33_HYST_Msk & ((value) << FUSES_BOD33_HYST_Pos))
#define FUSES_HOT_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
#define FUSES_HOT_ADC_VAL_CTAT_Pos 12
#define FUSES_HOT_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_CTAT_Pos)
#define FUSES_HOT_ADC_VAL_CTAT(value) (FUSES_HOT_ADC_VAL_CTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_CTAT_Pos))
#define FUSES_HOT_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
#define FUSES_HOT_ADC_VAL_PTAT_Pos 20
#define FUSES_HOT_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_HOT_ADC_VAL_PTAT_Pos)
#define FUSES_HOT_ADC_VAL_PTAT(value) (FUSES_HOT_ADC_VAL_PTAT_Msk & ((value) << FUSES_HOT_ADC_VAL_PTAT_Pos))
#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
#define FUSES_HOT_INT1V_VAL_Pos 0
#define FUSES_HOT_INT1V_VAL_Msk (_U_(0xFF) << FUSES_HOT_INT1V_VAL_Pos)
#define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
#define FUSES_HOT_TEMP_VAL_DEC_Pos 20
#define FUSES_HOT_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_HOT_TEMP_VAL_DEC_Pos)
#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
#define FUSES_HOT_TEMP_VAL_INT_Pos 12
#define FUSES_HOT_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_HOT_TEMP_VAL_INT_Pos)
#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
#define FUSES_ROOM_ADC_VAL_CTAT_ADDR (NVMCTRL_TEMP_LOG + 8)
#define FUSES_ROOM_ADC_VAL_CTAT_Pos 0
#define FUSES_ROOM_ADC_VAL_CTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_CTAT_Pos)
#define FUSES_ROOM_ADC_VAL_CTAT(value) (FUSES_ROOM_ADC_VAL_CTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_CTAT_Pos))
#define FUSES_ROOM_ADC_VAL_PTAT_ADDR (NVMCTRL_TEMP_LOG + 4)
#define FUSES_ROOM_ADC_VAL_PTAT_Pos 8
#define FUSES_ROOM_ADC_VAL_PTAT_Msk (_U_(0xFFF) << FUSES_ROOM_ADC_VAL_PTAT_Pos)
#define FUSES_ROOM_ADC_VAL_PTAT(value) (FUSES_ROOM_ADC_VAL_PTAT_Msk & ((value) << FUSES_ROOM_ADC_VAL_PTAT_Pos))
#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
#define FUSES_ROOM_INT1V_VAL_Pos 24
#define FUSES_ROOM_INT1V_VAL_Msk (_U_(0xFF) << FUSES_ROOM_INT1V_VAL_Pos)
#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8
#define FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << FUSES_ROOM_TEMP_VAL_DEC_Pos)
#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
#define FUSES_ROOM_TEMP_VAL_INT_Pos 0
#define FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << FUSES_ROOM_TEMP_VAL_INT_Pos)
#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
#define NVMCTRL_FUSES_BOOTPROT_Pos 26
#define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0xF) << NVMCTRL_FUSES_BOOTPROT_Pos)
#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 8)
#define NVMCTRL_FUSES_REGION_LOCKS_Pos 0
#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFFFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
#define NVMCTRL_FUSES_SEEPSZ_ADDR (NVMCTRL_USER + 4)
#define NVMCTRL_FUSES_SEEPSZ_Pos 4
#define NVMCTRL_FUSES_SEEPSZ_Msk (_U_(0x7) << NVMCTRL_FUSES_SEEPSZ_Pos)
#define NVMCTRL_FUSES_SEEPSZ(value) (NVMCTRL_FUSES_SEEPSZ_Msk & ((value) << NVMCTRL_FUSES_SEEPSZ_Pos))
#define NVMCTRL_FUSES_SEESBLK_ADDR (NVMCTRL_USER + 4)
#define NVMCTRL_FUSES_SEESBLK_Pos 0
#define NVMCTRL_FUSES_SEESBLK_Msk (_U_(0xF) << NVMCTRL_FUSES_SEESBLK_Pos)
#define NVMCTRL_FUSES_SEESBLK(value) (NVMCTRL_FUSES_SEESBLK_Msk & ((value) << NVMCTRL_FUSES_SEESBLK_Pos))
#define RAMECC_FUSES_ECCDIS_ADDR (NVMCTRL_USER + 4)
#define RAMECC_FUSES_ECCDIS_Pos 7
#define RAMECC_FUSES_ECCDIS_Msk (_U_(0x1) << RAMECC_FUSES_ECCDIS_Pos)
#define USB_FUSES_TRANSN_ADDR (NVMCTRL_SW0 + 4)
#define USB_FUSES_TRANSN_Pos 0
#define USB_FUSES_TRANSN_Msk (_U_(0x1F) << USB_FUSES_TRANSN_Pos)
#define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
#define USB_FUSES_TRANSP_ADDR (NVMCTRL_SW0 + 4)
#define USB_FUSES_TRANSP_Pos 5
#define USB_FUSES_TRANSP_Msk (_U_(0x1F) << USB_FUSES_TRANSP_Pos)
#define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
#define USB_FUSES_TRIM_ADDR (NVMCTRL_SW0 + 4)
#define USB_FUSES_TRIM_Pos 10
#define USB_FUSES_TRIM_Msk (_U_(0x7) << USB_FUSES_TRIM_Pos)
#define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
#define WDT_FUSES_ALWAYSON_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_ALWAYSON_Pos 17
#define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
#define WDT_FUSES_ENABLE_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_ENABLE_Pos 16
#define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_EWOFFSET_Pos 26
#define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
#define WDT_FUSES_PER_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_PER_Pos 18
#define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos)
#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WEN_Pos 30
#define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos)
#define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WINDOW_Pos 22
#define WDT_FUSES_WINDOW_Msk (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
#define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
#endif /* _SAME54_NVMCTRL_COMPONENT_ */
NVMCTRL_PARAM_Type::NVMP
uint32_t NVMP
Definition: nvmctrl.h:178
NVMCTRL_SEESTAT_Type::LOAD
uint32_t LOAD
Definition: nvmctrl.h:543
NVMCTRL_INTENCLR_Type::DONE
uint16_t DONE
Definition: nvmctrl.h:220
NVMCTRL_INTENCLR_Type
Definition: nvmctrl.h:218
NVMCTRL_PARAM_Type
Definition: nvmctrl.h:176
NVMCTRL_INTENSET_Type::NVME
uint16_t NVME
Definition: nvmctrl.h:274
NVMCTRL_INTFLAG_Type::LOCKE
__I uint16_t LOCKE
Definition: nvmctrl.h:319
NVMCTRL_CTRLA_Type::AHBNS1
uint16_t AHBNS1
Definition: nvmctrl.h:53
NVMCTRL_INTENSET_Type::ECCDE
uint16_t ECCDE
Definition: nvmctrl.h:273
NVMCTRL_INTENCLR_Type::SEESOVF
uint16_t SEESOVF
Definition: nvmctrl.h:229
NVMCTRL_INTFLAG_Type::uint16_t
__I uint16_t
Definition: nvmctrl.h:327
NVMCTRL_DBGCTRL_Type
Definition: nvmctrl.h:494
NVMCTRL_SEESTAT_Type::LOCK
uint32_t LOCK
Definition: nvmctrl.h:545
NVMCTRL_CTRLB_Type
Definition: nvmctrl.h:103
NVMCTRL_ECCERR_Type::TYPEL
uint32_t TYPEL
Definition: nvmctrl.h:459
NVMCTRL_RUNLOCK_Type::reg
uint32_t reg
Definition: nvmctrl.h:423
NVMCTRL_PARAM_Type::reg
uint32_t reg
Definition: nvmctrl.h:183
Nvmctrl::INTFLAG
__IO NVMCTRL_INTFLAG_Type INTFLAG
Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear.
Definition: nvmctrl.h:588
NVMCTRL_ECCERR_Type
Definition: nvmctrl.h:455
Nvmctrl::CTRLB
__O NVMCTRL_CTRLB_Type CTRLB
Offset: 0x04 ( /W 16) Control B.
Definition: nvmctrl.h:583
NVMCTRL_STATUS_Type::PRM
uint16_t PRM
Definition: nvmctrl.h:365
NVMCTRL_CTRLB_Type::CMD
uint16_t CMD
Definition: nvmctrl.h:105
NVMCTRL_CTRLA_Type
Definition: nvmctrl.h:44
NVMCTRL_INTFLAG_Type::ECCDE
__I uint16_t ECCDE
Definition: nvmctrl.h:321
NVMCTRL_INTENCLR_Type::NVME
uint16_t NVME
Definition: nvmctrl.h:226
NVMCTRL_DBGCTRL_Type::reg
uint8_t reg
Definition: nvmctrl.h:500
NVMCTRL_CTRLA_Type::reg
uint16_t reg
Definition: nvmctrl.h:57
NVMCTRL_INTENCLR_Type::reg
uint16_t reg
Definition: nvmctrl.h:233
NVMCTRL_INTENSET_Type::ADDRE
uint16_t ADDRE
Definition: nvmctrl.h:269
NVMCTRL_STATUS_Type::READY
uint16_t READY
Definition: nvmctrl.h:364
NVMCTRL_SEESTAT_Type::RLOCK
uint32_t RLOCK
Definition: nvmctrl.h:546
NVMCTRL_INTFLAG_Type::reg
uint16_t reg
Definition: nvmctrl.h:329
Nvmctrl::DBGCTRL
__IO NVMCTRL_DBGCTRL_Type DBGCTRL
Offset: 0x28 (R/W 8) Debug Control.
Definition: nvmctrl.h:594
NVMCTRL_ADDR_Type::ADDR
uint32_t ADDR
Definition: nvmctrl.h:402
NVMCTRL_ADDR_Type::reg
uint32_t reg
Definition: nvmctrl.h:405
NVMCTRL_CTRLA_Type::CACHEDIS1
uint16_t CACHEDIS1
Definition: nvmctrl.h:55
Nvmctrl::RUNLOCK
__I NVMCTRL_RUNLOCK_Type RUNLOCK
Offset: 0x18 (R/ 32) Lock Section.
Definition: nvmctrl.h:591
NVMCTRL_INTFLAG_Type::NVME
__I uint16_t NVME
Definition: nvmctrl.h:322
NVMCTRL_CTRLA_Type::SUSPEN
uint16_t SUSPEN
Definition: nvmctrl.h:48
NVMCTRL_INTENSET_Type::ECCSE
uint16_t ECCSE
Definition: nvmctrl.h:272
NVMCTRL_INTFLAG_Type
Definition: nvmctrl.h:314
NVMCTRL_INTENSET_Type::SEESFULL
uint16_t SEESFULL
Definition: nvmctrl.h:276
NVMCTRL_STATUS_Type::LOAD
uint16_t LOAD
Definition: nvmctrl.h:366
NVMCTRL_PBLDATA_Type::DATA
uint32_t DATA
Definition: nvmctrl.h:439
NVMCTRL_INTENCLR_Type::ECCDE
uint16_t ECCDE
Definition: nvmctrl.h:225
NVMCTRL_SEECFG_Type
Definition: nvmctrl.h:515
NVMCTRL_SEECFG_Type::WMODE
uint8_t WMODE
Definition: nvmctrl.h:517
NVMCTRL_ECCERR_Type::reg
uint32_t reg
Definition: nvmctrl.h:462
NVMCTRL_INTENSET_Type::reg
uint16_t reg
Definition: nvmctrl.h:281
NVMCTRL_CTRLA_Type::AUTOWS
uint16_t AUTOWS
Definition: nvmctrl.h:47
NVMCTRL_CTRLA_Type::CACHEDIS0
uint16_t CACHEDIS0
Definition: nvmctrl.h:54
NVMCTRL_INTFLAG_Type::SEESFULL
__I uint16_t SEESFULL
Definition: nvmctrl.h:324
Nvmctrl::ADDR
__IO NVMCTRL_ADDR_Type ADDR
Offset: 0x14 (R/W 32) Address.
Definition: nvmctrl.h:590
NVMCTRL_RUNLOCK_Type
Definition: nvmctrl.h:419
NVMCTRL_CTRLA_Type::RWS
uint16_t RWS
Definition: nvmctrl.h:51
NVMCTRL_INTFLAG_Type::DONE
__I uint16_t DONE
Definition: nvmctrl.h:316
NVMCTRL_CTRLA_Type::PRM
uint16_t PRM
Definition: nvmctrl.h:50
NVMCTRL_STATUS_Type::reg
uint16_t reg
Definition: nvmctrl.h:374
NVMCTRL_INTENSET_Type::SEEWRC
uint16_t SEEWRC
Definition: nvmctrl.h:278
NVMCTRL_SEESTAT_Type
Definition: nvmctrl.h:540
NVMCTRL_INTENSET_Type::PROGE
uint16_t PROGE
Definition: nvmctrl.h:270
Nvmctrl::SEECFG
__IO NVMCTRL_SEECFG_Type SEECFG
Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register.
Definition: nvmctrl.h:596
NVMCTRL_STATUS_Type
Definition: nvmctrl.h:362
NVMCTRL_STATUS_Type::BOOTPROT
uint16_t BOOTPROT
Definition: nvmctrl.h:371
NVMCTRL_INTENCLR_Type::SUSP
uint16_t SUSP
Definition: nvmctrl.h:227
NVMCTRL_SEESTAT_Type::reg
uint32_t reg
Definition: nvmctrl.h:553
Nvmctrl::STATUS
__I NVMCTRL_STATUS_Type STATUS
Offset: 0x12 (R/ 16) Status.
Definition: nvmctrl.h:589
NVMCTRL_INTENSET_Type::LOCKE
uint16_t LOCKE
Definition: nvmctrl.h:271
NVMCTRL_STATUS_Type::SUSP
uint16_t SUSP
Definition: nvmctrl.h:367
NVMCTRL_CTRLA_Type::WMODE
uint16_t WMODE
Definition: nvmctrl.h:49
NVMCTRL_SEECFG_Type::reg
uint8_t reg
Definition: nvmctrl.h:521
NVMCTRL_INTENCLR_Type::SEEWRC
uint16_t SEEWRC
Definition: nvmctrl.h:230
NVMCTRL_INTFLAG_Type::ECCSE
__I uint16_t ECCSE
Definition: nvmctrl.h:320
NVMCTRL_STATUS_Type::BPDIS
uint16_t BPDIS
Definition: nvmctrl.h:369
Nvmctrl::INTENSET
__IO NVMCTRL_INTENSET_Type INTENSET
Offset: 0x0E (R/W 16) Interrupt Enable Set.
Definition: nvmctrl.h:587
NVMCTRL_STATUS_Type::AFIRST
uint16_t AFIRST
Definition: nvmctrl.h:368
Nvmctrl::ECCERR
__I NVMCTRL_ECCERR_Type ECCERR
Offset: 0x24 (R/ 32) ECC Error Status Register.
Definition: nvmctrl.h:593
NVMCTRL_SEESTAT_Type::BUSY
uint32_t BUSY
Definition: nvmctrl.h:544
Nvmctrl::PARAM
__I NVMCTRL_PARAM_Type PARAM
Offset: 0x08 (R/ 32) NVM Parameter.
Definition: nvmctrl.h:585
NVMCTRL_INTENCLR_Type::LOCKE
uint16_t LOCKE
Definition: nvmctrl.h:223
NVMCTRL_PARAM_Type::PSZ
uint32_t PSZ
Definition: nvmctrl.h:179
NVMCTRL_INTENCLR_Type::ECCSE
uint16_t ECCSE
Definition: nvmctrl.h:224
NVMCTRL_SEECFG_Type::APRDIS
uint8_t APRDIS
Definition: nvmctrl.h:518
NVMCTRL_PARAM_Type::SEE
uint32_t SEE
Definition: nvmctrl.h:181
NVMCTRL_INTFLAG_Type::SUSP
__I uint16_t SUSP
Definition: nvmctrl.h:323
NVMCTRL_ECCERR_Type::TYPEH
uint32_t TYPEH
Definition: nvmctrl.h:460
NVMCTRL_INTENCLR_Type::SEESFULL
uint16_t SEESFULL
Definition: nvmctrl.h:228
NVMCTRL_ECCERR_Type::ADDR
uint32_t ADDR
Definition: nvmctrl.h:457
NVMCTRL_SEESTAT_Type::ASEES
uint32_t ASEES
Definition: nvmctrl.h:542
Nvmctrl
NVMCTRL APB hardware registers.
Definition: nvmctrl.h:580
Nvmctrl::CTRLA
__IO NVMCTRL_CTRLA_Type CTRLA
Offset: 0x00 (R/W 16) Control A.
Definition: nvmctrl.h:581
NVMCTRL_INTENSET_Type
Definition: nvmctrl.h:266
NVMCTRL_INTENSET_Type::SUSP
uint16_t SUSP
Definition: nvmctrl.h:275
NVMCTRL_PBLDATA_Type::reg
uint32_t reg
Definition: nvmctrl.h:441
NVMCTRL_ADDR_Type
Definition: nvmctrl.h:400
NVMCTRL_SEESTAT_Type::PSZ
uint32_t PSZ
Definition: nvmctrl.h:550
NVMCTRL_INTFLAG_Type::PROGE
__I uint16_t PROGE
Definition: nvmctrl.h:318
NVMCTRL_DBGCTRL_Type::ECCDIS
uint8_t ECCDIS
Definition: nvmctrl.h:496
NVMCTRL_SEESTAT_Type::SBLK
uint32_t SBLK
Definition: nvmctrl.h:548
NVMCTRL_DBGCTRL_Type::ECCELOG
uint8_t ECCELOG
Definition: nvmctrl.h:497
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
NVMCTRL_CTRLB_Type::reg
uint16_t reg
Definition: nvmctrl.h:109
NVMCTRL_INTENSET_Type::SEESOVF
uint16_t SEESOVF
Definition: nvmctrl.h:277
Nvmctrl::INTENCLR
__IO NVMCTRL_INTENCLR_Type INTENCLR
Offset: 0x0C (R/W 16) Interrupt Enable Clear.
Definition: nvmctrl.h:586
NVMCTRL_INTFLAG_Type::SEESOVF
__I uint16_t SEESOVF
Definition: nvmctrl.h:325
NVMCTRL_INTENCLR_Type::ADDRE
uint16_t ADDRE
Definition: nvmctrl.h:221
NVMCTRL_INTFLAG_Type::ADDRE
__I uint16_t ADDRE
Definition: nvmctrl.h:317
NVMCTRL_RUNLOCK_Type::RUNLOCK
uint32_t RUNLOCK
Definition: nvmctrl.h:421
NVMCTRL_CTRLB_Type::CMDEX
uint16_t CMDEX
Definition: nvmctrl.h:107
NVMCTRL_INTENSET_Type::DONE
uint16_t DONE
Definition: nvmctrl.h:268
NVMCTRL_INTENCLR_Type::PROGE
uint16_t PROGE
Definition: nvmctrl.h:222
NVMCTRL_PBLDATA_Type
Definition: nvmctrl.h:437
Nvmctrl::SEESTAT
__I NVMCTRL_SEESTAT_Type SEESTAT
Offset: 0x2C (R/ 32) SmartEEPROM Status Register.
Definition: nvmctrl.h:598
NVMCTRL_CTRLA_Type::AHBNS0
uint16_t AHBNS0
Definition: nvmctrl.h:52
NVMCTRL_INTFLAG_Type::SEEWRC
__I uint16_t SEEWRC
Definition: nvmctrl.h:326