/**
 * @file conf_core.h
 * @author Penguin
 *
 * @section Description
 *
 * This is the master config for the core module for this mcu. This file is *required*
 * for the core module to function.
 */
#ifndef _CONF_CLOCKS_H_
#define _CONF_CLOCKS_H_
#include "clocks.h"

/**
 * Define the number of wait states for the master clock.
 * Can be [0-15].
 */
#define CONF_CORE_MCLK_NVM_WAIT_STATE		0x5

/**
 * Define the master clock divisor.
 * - 0x1		=> Clock Divide by 1
 * - 0x2		=> Clock Divide by 2
 * - 0x4		=> Clock Divide by 4
 * - 0x8		=> Clock Divide by 8
 * - 0x10		=> Clock Divide by 16
 * - 0x20		=> Clock Divide by 32
 * - 0x40		=> Clock Divide by 64
 * - 0x80		=> Clock Divide by 128
 */
#define CONF_CORE_MCLK_CPUDIV				0x1

/**
 * Define whether the DMAC is enabled or not.
 * - 0 => Disabled
 * - 1 => Enabled
 */
#define CONF_CORE_DMA_ENABLE				(0)

/**
 * Define whether the CMCC (Cortex-M Cache Controller) is enabled or not.
 * - 0 => Disabled
 * - 1 => Enabled
 */
#define CONF_CORE_CMCC_ENABLE				(0)

#define CONF_CORE_PORT_EVCTRL_0_ENABLE		(0)
#define CONF_CORE_PORT_EVCTRL_1_ENABLE		(0)
#define CONF_CORE_PORT_EVCTRL_2_ENABLE		(0)
// XOSC0 Config
#define CONF_CORE_CLK_XOSC0_ENABLE			(1)
#define CONF_CORE_CLK_XOSC0_XTALEN			(1)
#define CONF_CORE_CLK_XOSC0_RUNSTDBY		(0)
#define CONF_CORE_CLK_XOSC0_ONDEMAND		(0)
#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN		(0)
#define CONF_CORE_CLK_XOSC0_ENALC			(1)
#define CONF_CORE_CLK_XOSC0_CFDEN			(1)
#define CONF_CORE_CLK_XOSC0_SWBEN			(0)
#define CONF_CORE_CLK_XOSC0_STARTUP_TIME	CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
#define CONF_CORE_CLK_XOSC0_FREQUENCY		12000000

// XOSC1 Config
#define CONF_CORE_CLK_XOSC1_ENABLE			(0)
#define CONF_CORE_CLK_XOSC1_XTALEN			(0)
#define CONF_CORE_CLK_XOSC1_RUNSTDBY		(0)
#define CONF_CORE_CLK_XOSC1_ONDEMAND		(0)
#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN		(0)
#define CONF_CORE_CLK_XOSC1_ENALC			(0)
#define CONF_CORE_CLK_XOSC1_CFDEN			(0)
#define CONF_CORE_CLK_XOSC1_SWBEN			(0)
#define CONF_CORE_CLK_XOSC1_STARTUP_TIME	CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
#define CONF_CORE_CLK_XOSC1_FREQUENCY		12000000

// XOSC32K Config
#define CONF_CORE_CLK_XOSC32K_ENABLE		(1)
#define CONF_CORE_CLK_XOSC32K_CGM			CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME	CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
#define CONF_CORE_CLK_XOSC32K_ONDEMAND		(1)
#define CONF_CORE_CLK_XOSC32K_RUNSTDBY		(0)
#define CONF_CORE_CLK_XOSC32K_EN1K			(0)
#define CONF_CORE_CLK_XOSC32K_EN32K		(1)
#define CONF_CORE_CLK_XOSC32K_XTALEN		(1)
#define CONF_CORE_CLK_XOSC32K_CFDPRESC		(0)
#define CONF_CORE_CLK_XOSC32K_CFDEN		(0)
#define CONF_CORE_CLK_XOSC32K_SWBACK		(0)
#define CONF_CORE_CLK_XOSC32K_WRTLOCK		(0)

/** @name Core-DFLL48M-Configuration
 * Configuration options for DFLL48M
 */
/** @{ */
/**
 * DFLL48M Enable
 * @brief Enables or Disables the DFLL48M Clock
 * - 0 => Disables DFLL48M
 * - 1 => Enables DFLL48M
 * <br>pg. 724 of datasheet
 */
#define CONF_CORE_CLK_DFLL_ENABLE			(1)
/**
 * DFLL48M On Demand Control
 * @brief Enables or Disables on-demand operation
 * - 0 => Disables On Demand Operation
 * - 1 => Enables On Demand Operation
 * <br>pg. 724 of datasheet
 */
#define CONF_CORE_CLK_DFLL_ONDEMAND		(0)
/**
 * DFLL48M Run in Standby Control
 * @brief Enables or Disables run-in-standby operation
 * - 0 => Disables run-in-standby operation
 * - 1 => Enables run-in-standby operation
 * <br>pg. 724 of datasheet
 */
#define CONF_CORE_CLK_DFLL_RUNSTDBY		(0)
/**
 * DFLL48M Wait Lock Control
 @brief This bit controls the DFLL output clock, depending on the lock status:
 * - 0 => Output clock before the DFLL is locked.
 * - 1 => Output clock when DFLL is locked (Fine lock).
 * <br>pg. 725 of datasheet
 */
#define CONF_CORE_CLK_DFLL_WAITLOCK		(0)
#define CONF_CORE_CLK_DFLL_BPLKC			(0)
#define CONF_CORE_CLK_DFLL_QLDIS			(0)
#define CONF_CORE_CLK_DFLL_CCDIS			(1)
#define CONF_CORE_CLK_DFLL_USBCRM			(1)
#define CONF_CORE_CLK_DFLL_LLAW			(0)
#define CONF_CORE_CLK_DFLL_STABLE_FCALIB	CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
#define CONF_CORE_CLK_DFLL_MODE			0x01
#define CONF_CORE_CLK_DFLL_DIFF_VAL		0
#define CONF_CORE_CLK_DFLL_COARSE_VAL		(0x1f / 4)
#define CONF_CORE_CLK_DFLL_FINE_VAL		128
#define CONF_CORE_CLK_DFLL_CSTEP_VAL		1
#define CONF_CORE_CLK_DFLL_FSTEP_VAL		1
#define CONF_CORE_CLK_DFLL_MUL_VAL			(48000000)
/**
 * DFLL48M GCLK Source
 * @brief GCLK Source used to generate DFLL48M
 * - 0 => Generic clock generator 0
 * - 1 => Generic clock generator 1
 * - 2 => Generic clock generator 2
 * - 3 => Generic clock generator 3
 * - 4 => Generic clock generator 4
 * - 5 => Generic clock generator 5
 * - 6 => Generic clock generator 6
 * - 7 => Generic clock generator 7
 * - 8 => Generic clock generator 8
 * - 9 => Generic clock generator 9
 * - 10 => Generic clock generator 10
 * - 11 => Generic clock generator 11
 */
#define CONF_CORE_CLK_DFLL_GCLK_SRC		3
#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL	0
/** @} */

// DPLL0 Config
#define CONF_CORE_CLK_DPLL0_ENABLE			(1)
#define CONF_CORE_CLK_DPLL0_ONDEMAND		(0)
#define CONF_CORE_CLK_DPLL0_RUNSTDBY		(0)
#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL	0
#define CONF_CORE_CLK_DPLL0_LDR_VAL		(119)
#define CONF_CORE_CLK_DPLL0_DIV_VAL		(5)
#define CONF_CORE_CLK_DPLL0_DCOEN			0
#define CONF_CORE_CLK_DPLL0_DCOFILTER		CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
#define CONF_CORE_CLK_DPLL0_LBYPASS		1
#define CONF_CORE_CLK_DPLL0_LTIME			0
#define CONF_CORE_CLK_DPLL0_WUF			0
#define CONF_CORE_CLK_DPLL0_GCLK_SRC		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_CLK_DPLL0_REFCLK			CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
/**
 * pg. 732 of the datasheet
 * FILTER[3:0]	| PLL Bandwidth (fn)	| Damping Factor
 * 0x0			| 92.7 kHz				| 0.76
 * 0x1			| 131 kHz				| 1.08
 * 0x2			| 46.4 kHz				| 0.38
 * 0x3			| 65.6 kHz				| 0.54
 * 0x4			| 131 kHz				| 0.56
 * 0x5			| 185 kHz				| 0.79
 * 0x6			| 65.6 kHz				| 0.28
 * 0x7			| 92.7 kHz				| 0.39
 * 0x8			| 46.4 kHz				| 1.49
 * 0x9			| 65.6 kHz				| 2.11
 * 0xA			| 23.2 kHz				| 0.75
 * 0xB			| 32.8 kHz				| 1.06
 * 0xC			| 65.6 kHz				| 1.07
 * 0xD			| 92.7 kHz				| 1.51
 * 0xE			| 32.8 kHz				| 0.53
 * 0xF			| 46.4 kHz				| 0.75
 *
 * When in doubt, leave this at its default.
 */
#define CONF_CORE_CLK_DPLL0_FILTER			0x0

// DPLL1 Config
#define CONF_CORE_CLK_DPLL1_ENABLE			(0)
#define CONF_CORE_CLK_DPLL1_ONDEMAND		(0)
#define CONF_CORE_CLK_DPLL1_RUNSTDBY		(0)
#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL	0
#define CONF_CORE_CLK_DPLL1_LDR_VAL		(0)
#define CONF_CORE_CLK_DPLL1_DIV_VAL		(0)
#define CONF_CORE_CLK_DPLL1_DCOEN			0
#define CONF_CORE_CLK_DPLL1_DCOFILTER		CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
#define CONF_CORE_CLK_DPLL1_LBYPASS		0
#define CONF_CORE_CLK_DPLL1_LTIME			0
#define CONF_CORE_CLK_DPLL1_WUF			0
#define CONF_CORE_CLK_DPLL1_GCLK_SRC		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_CLK_DPLL1_REFCLK			CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
/**
 * pg. 732 of the datasheet
 * ~~~
 * FILTER[3:0]	| PLL Bandwidth (fn)	| Damping Factor
 * 0x0			| 92.7 kHz				| 0.76
 * 0x1			| 131 kHz				| 1.08
 * 0x2			| 46.4 kHz				| 0.38
 * 0x3			| 65.6 kHz				| 0.54
 * 0x4			| 131 kHz				| 0.56
 * 0x5			| 185 kHz				| 0.79
 * 0x6			| 65.6 kHz				| 0.28
 * 0x7			| 92.7 kHz				| 0.39
 * 0x8			| 46.4 kHz				| 1.49
 * 0x9			| 65.6 kHz				| 2.11
 * 0xA			| 23.2 kHz				| 0.75
 * 0xB			| 32.8 kHz				| 1.06
 * 0xC			| 65.6 kHz				| 1.07
 * 0xD			| 92.7 kHz				| 1.51
 * 0xE			| 32.8 kHz				| 0.53
 * 0xF			| 46.4 kHz				| 0.75
 * ~~~
 *
 * When in doubt, leave this at its default.
 */
#define CONF_CORE_CLK_DPLL1_FILTER			0x0

// GCLK Generators Config
#define CONF_CORE_GCLK_0_ENABLE			1
#define CONF_CORE_GCLK_0_RUN_IN_STANDBY	1
#define CONF_CORE_GCLK_0_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_0_DIV_VAL			1
#define CONF_CORE_GCLK_0_DIVSEL			0
#define CONF_CORE_GCLK_0_OUTPUT_ENABLE		1
#define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE	1
#define CONF_CORE_GCLK_0_IDC				1

#define CONF_CORE_GCLK_1_ENABLE			0
#define CONF_CORE_GCLK_1_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_1_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_1_DIV_VAL			1
#define CONF_CORE_GCLK_1_DIVSEL			0
#define CONF_CORE_GCLK_1_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_1_IDC				0

#define CONF_CORE_GCLK_2_ENABLE			0
#define CONF_CORE_GCLK_2_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_2_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_2_DIV_VAL			1
#define CONF_CORE_GCLK_2_DIVSEL			0
#define CONF_CORE_GCLK_2_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_2_IDC				0

#define CONF_CORE_GCLK_3_ENABLE			1
#define CONF_CORE_GCLK_3_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_3_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC32K
#define CONF_CORE_GCLK_3_DIV_VAL			1
#define CONF_CORE_GCLK_3_DIVSEL			0
#define CONF_CORE_GCLK_3_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_3_IDC				0

#define CONF_CORE_GCLK_4_ENABLE			0
#define CONF_CORE_GCLK_4_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_4_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_4_DIV_VAL			1
#define CONF_CORE_GCLK_4_DIVSEL			1
#define CONF_CORE_GCLK_4_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_4_IDC				0

#define CONF_CORE_GCLK_5_ENABLE			0
#define CONF_CORE_GCLK_5_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_5_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_5_DIV_VAL			1
#define CONF_CORE_GCLK_5_DIVSEL			0
#define CONF_CORE_GCLK_5_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_5_IDC				0

#define CONF_CORE_GCLK_6_ENABLE			0
#define CONF_CORE_GCLK_6_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_6_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_6_DIV_VAL			1
#define CONF_CORE_GCLK_6_DIVSEL			0
#define CONF_CORE_GCLK_6_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_6_IDC				0

#define CONF_CORE_GCLK_7_ENABLE			0
#define CONF_CORE_GCLK_7_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_7_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_7_DIV_VAL			1
#define CONF_CORE_GCLK_7_DIVSEL			0
#define CONF_CORE_GCLK_7_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_7_IDC				0

#define CONF_CORE_GCLK_8_ENABLE			0
#define CONF_CORE_GCLK_8_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_8_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_8_DIV_VAL			1
#define CONF_CORE_GCLK_8_DIVSEL			0
#define CONF_CORE_GCLK_8_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_8_IDC				0

#define CONF_CORE_GCLK_9_ENABLE			0
#define CONF_CORE_GCLK_9_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_9_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_9_DIV_VAL			1
#define CONF_CORE_GCLK_9_DIVSEL			0
#define CONF_CORE_GCLK_9_OUTPUT_ENABLE		0
#define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_9_IDC				0

#define CONF_CORE_GCLK_10_ENABLE			0
#define CONF_CORE_GCLK_10_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_10_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_10_DIV_VAL			1
#define CONF_CORE_GCLK_10_DIVSEL			0
#define CONF_CORE_GCLK_10_OUTPUT_ENABLE	0
#define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_10_IDC				0

#define CONF_CORE_GCLK_11_ENABLE			0
#define CONF_CORE_GCLK_11_RUN_IN_STANDBY	0
#define CONF_CORE_GCLK_11_CLOCK_SOURCE		GCLK_GENCTRL_SRC_XOSC0
#define CONF_CORE_GCLK_11_DIV_VAL			1
#define CONF_CORE_GCLK_11_DIVSEL			0
#define CONF_CORE_GCLK_11_OUTPUT_ENABLE	0
#define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE	0
#define CONF_CORE_GCLK_11_IDC				0



#endif
