tc3.h
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#ifndef _SAME54_TC3_INSTANCE_
#define _SAME54_TC3_INSTANCE_
/* ========== Register definition for TC3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC3_CTRLA (0x4101C000)
#define REG_TC3_CTRLBCLR (0x4101C004)
#define REG_TC3_CTRLBSET (0x4101C005)
#define REG_TC3_EVCTRL (0x4101C006)
#define REG_TC3_INTENCLR (0x4101C008)
#define REG_TC3_INTENSET (0x4101C009)
#define REG_TC3_INTFLAG (0x4101C00A)
#define REG_TC3_STATUS (0x4101C00B)
#define REG_TC3_WAVE (0x4101C00C)
#define REG_TC3_DRVCTRL (0x4101C00D)
#define REG_TC3_DBGCTRL (0x4101C00F)
#define REG_TC3_SYNCBUSY (0x4101C010)
#define REG_TC3_COUNT16_COUNT (0x4101C014)
#define REG_TC3_COUNT16_CC0 (0x4101C01C)
#define REG_TC3_COUNT16_CC1 (0x4101C01E)
#define REG_TC3_COUNT16_CCBUF0 (0x4101C030)
#define REG_TC3_COUNT16_CCBUF1 (0x4101C032)
#define REG_TC3_COUNT32_COUNT (0x4101C014)
#define REG_TC3_COUNT32_CC0 (0x4101C01C)
#define REG_TC3_COUNT32_CC1 (0x4101C020)
#define REG_TC3_COUNT32_CCBUF0 (0x4101C030)
#define REG_TC3_COUNT32_CCBUF1 (0x4101C034)
#define REG_TC3_COUNT8_COUNT (0x4101C014)
#define REG_TC3_COUNT8_PER (0x4101C01B)
#define REG_TC3_COUNT8_CC0 (0x4101C01C)
#define REG_TC3_COUNT8_CC1 (0x4101C01D)
#define REG_TC3_COUNT8_PERBUF (0x4101C02F)
#define REG_TC3_COUNT8_CCBUF0 (0x4101C030)
#define REG_TC3_COUNT8_CCBUF1 (0x4101C031)
#else
#define REG_TC3_CTRLA (*(RwReg *)0x4101C000UL)
#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x4101C004UL)
#define REG_TC3_CTRLBSET (*(RwReg8 *)0x4101C005UL)
#define REG_TC3_EVCTRL (*(RwReg16*)0x4101C006UL)
#define REG_TC3_INTENCLR (*(RwReg8 *)0x4101C008UL)
#define REG_TC3_INTENSET (*(RwReg8 *)0x4101C009UL)
#define REG_TC3_INTFLAG (*(RwReg8 *)0x4101C00AUL)
#define REG_TC3_STATUS (*(RwReg8 *)0x4101C00BUL)
#define REG_TC3_WAVE (*(RwReg8 *)0x4101C00CUL)
#define REG_TC3_DRVCTRL (*(RwReg8 *)0x4101C00DUL)
#define REG_TC3_DBGCTRL (*(RwReg8 *)0x4101C00FUL)
#define REG_TC3_SYNCBUSY (*(RoReg *)0x4101C010UL)
#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x4101C014UL)
#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x4101C01CUL)
#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x4101C01EUL)
#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x4101C030UL)
#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x4101C032UL)
#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x4101C014UL)
#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x4101C01CUL)
#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x4101C020UL)
#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x4101C030UL)
#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x4101C034UL)
#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x4101C014UL)
#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x4101C01BUL)
#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x4101C01CUL)
#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x4101C01DUL)
#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x4101C02FUL)
#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x4101C030UL)
#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x4101C031UL)
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC3 peripheral ========== */
#define TC3_CC_NUM 2
#define TC3_DMAC_ID_MC_0 54
#define TC3_DMAC_ID_MC_1 55
#define TC3_DMAC_ID_MC_LSB 54
#define TC3_DMAC_ID_MC_MSB 55
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 53 // Indexes of DMA Overflow trigger
#define TC3_EXT 0 // Coding of implemented extended features (keep 0 value)
#define TC3_GCLK_ID 26 // Index of Generic Clock
#define TC3_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave
#define TC3_OW_NUM 2 // Number of Output Waveforms
#endif /* _SAME54_TC3_INSTANCE_ */