dmac.h File Reference

Component description for DMAC. More...

Go to the source code of this file.

## Data Structures

union | DMAC_CTRL_Type
union | DMAC_CRCCTRL_Type
union | DMAC_CRCDATAIN_Type
union | DMAC_CRCCHKSUM_Type
union | DMAC_CRCSTATUS_Type
union | DMAC_DBGCTRL_Type
union | DMAC_SWTRIGCTRL_Type
union | DMAC_PRICTRL0_Type
union | DMAC_INTPEND_Type
union | DMAC_INTSTATUS_Type
union | DMAC_BUSYCH_Type
union | DMAC_PENDCH_Type
union | DMAC_ACTIVE_Type
union | DMAC_BASEADDR_Type
union | DMAC_WRBADDR_Type
union | DMAC_CHCTRLA_Type
union | DMAC_CHCTRLB_Type
union | DMAC_CHPRILVL_Type
union | DMAC_CHEVCTRL_Type
union | DMAC_CHINTENCLR_Type
union | DMAC_CHINTENSET_Type
union | DMAC_CHINTFLAG_Type
union | DMAC_CHSTATUS_Type
union | DMAC_BTCTRL_Type
union | DMAC_BTCNT_Type
union | DMAC_SRCADDR_Type
union | DMAC_DSTADDR_Type
union | DMAC_DESCADDR_Type
struct | DmacChannel
| DmacChannel hardware registers. More...
struct | Dmac
| DMAC APB hardware registers. More...
struct | DmacDescriptor
| DMAC Descriptor SRAM registers. More...

## Macros

#define | DMAC_U2503
#define | REV_DMAC 0x101
#define | DMAC_CTRL_OFFSET 0x00
| (DMAC_CTRL offset) Control
#define | DMAC_CTRL_RESETVALUE _U_(0x0000)
| (DMAC_CTRL reset_value) Control
#define | DMAC_CTRL_SWRST_Pos 0
| (DMAC_CTRL) Software Reset
#define | DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos)
#define | DMAC_CTRL_DMAENABLE_Pos 1
| (DMAC_CTRL) DMA Enable
#define | DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos)
#define | DMAC_CTRL_LVLEN0_Pos 8
| (DMAC_CTRL) Priority Level 0 Enable
#define | DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos)
#define | DMAC_CTRL_LVLEN1_Pos 9
| (DMAC_CTRL) Priority Level 1 Enable
#define | DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos)
#define | DMAC_CTRL_LVLEN2_Pos 10
| (DMAC_CTRL) Priority Level 2 Enable
#define | DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos)
#define | DMAC_CTRL_LVLEN3_Pos 11
| (DMAC_CTRL) Priority Level 3 Enable
#define | DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos)
#define | DMAC_CTRL_LVLEN_Pos 8
| (DMAC_CTRL) Priority Level x Enable
#define | DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos)
#define | DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
#define | DMAC_CTRL_MASK _U_(0x0F03)
| (DMAC_CTRL) MASK Register
#define | DMAC_CRCCTRL_OFFSET 0x02
| (DMAC_CRCCTRL offset) CRC Control
#define | DMAC_CRCCTRL_RESETVALUE _U_(0x0000)
| (DMAC_CRCCTRL reset_value) CRC Control
#define | DMAC_CRCCTRL_CRCBEATSIZE_Pos 0
| (DMAC_CRCCTRL) CRC Beat Size
#define | DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define | DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
#define | DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0)
| (DMAC_CRCCTRL) 8-bit bus transfer
#define | DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1)
| (DMAC_CRCCTRL) 16-bit bus transfer
#define | DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2)
| (DMAC_CRCCTRL) 32-bit bus transfer
#define | DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define | DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define | DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define | DMAC_CRCCTRL_CRCPOLY_Pos 2
| (DMAC_CRCCTRL) CRC Polynomial Type
#define | DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos)
#define | DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
#define | DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0)
| (DMAC_CRCCTRL) CRC-16 (CRC-CCITT)
#define | DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1)
| (DMAC_CRCCTRL) CRC32 (IEEE 802.3)
#define | DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
#define | DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
#define | DMAC_CRCCTRL_CRCSRC_Pos 8
| (DMAC_CRCCTRL) CRC Input Source
#define | DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos)
#define | DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
#define | DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0)
| (DMAC_CRCCTRL) CRC Disabled
#define | DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1)
| (DMAC_CRCCTRL) I/O interface
#define | DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos)
#define | DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos)
#define | DMAC_CRCCTRL_CRCMODE_Pos 14
| (DMAC_CRCCTRL) CRC Operating Mode
#define | DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos)
#define | DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos))
#define | DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0)
| (DMAC_CRCCTRL) Default operating mode
#define | DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2)
| (DMAC_CRCCTRL) Memory CRC monitor operating mode
#define | DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3)
| (DMAC_CRCCTRL) Memory CRC generation operating mode
#define | DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos)
#define | DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos)
#define | DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos)
#define | DMAC_CRCCTRL_MASK _U_(0xFF0F)
| (DMAC_CRCCTRL) MASK Register
#define | DMAC_CRCDATAIN_OFFSET 0x04
| (DMAC_CRCDATAIN offset) CRC Data Input
#define | DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000)
| (DMAC_CRCDATAIN reset_value) CRC Data Input
#define | DMAC_CRCDATAIN_CRCDATAIN_Pos 0
| (DMAC_CRCDATAIN) CRC Data Input
#define | DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos)
#define | DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
#define | DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF)
| (DMAC_CRCDATAIN) MASK Register
#define | DMAC_CRCCHKSUM_OFFSET 0x08
| (DMAC_CRCCHKSUM offset) CRC Checksum
#define | DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000)
| (DMAC_CRCCHKSUM reset_value) CRC Checksum
#define | DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0
| (DMAC_CRCCHKSUM) CRC Checksum
#define | DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
#define | DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
#define | DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF)
| (DMAC_CRCCHKSUM) MASK Register
#define | DMAC_CRCSTATUS_OFFSET 0x0C
| (DMAC_CRCSTATUS offset) CRC Status
#define | DMAC_CRCSTATUS_RESETVALUE _U_(0x00)
| (DMAC_CRCSTATUS reset_value) CRC Status
#define | DMAC_CRCSTATUS_CRCBUSY_Pos 0
| (DMAC_CRCSTATUS) CRC Module Busy
#define | DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos)
#define | DMAC_CRCSTATUS_CRCZERO_Pos 1
| (DMAC_CRCSTATUS) CRC Zero
#define | DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos)
#define | DMAC_CRCSTATUS_CRCERR_Pos 2
| (DMAC_CRCSTATUS) CRC Error
#define | DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos)
#define | DMAC_CRCSTATUS_MASK _U_(0x07)
| (DMAC_CRCSTATUS) MASK Register
#define | DMAC_DBGCTRL_OFFSET 0x0D
| (DMAC_DBGCTRL offset) Debug Control
#define | DMAC_DBGCTRL_RESETVALUE _U_(0x00)
| (DMAC_DBGCTRL reset_value) Debug Control
#define | DMAC_DBGCTRL_DBGRUN_Pos 0
| (DMAC_DBGCTRL) Debug Run
#define | DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos)
#define | DMAC_DBGCTRL_MASK _U_(0x01)
| (DMAC_DBGCTRL) MASK Register
#define | DMAC_SWTRIGCTRL_OFFSET 0x10
| (DMAC_SWTRIGCTRL offset) Software Trigger Control
#define | DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000)
| (DMAC_SWTRIGCTRL reset_value) Software Trigger Control
#define | DMAC_SWTRIGCTRL_SWTRIG0_Pos 0
| (DMAC_SWTRIGCTRL) Channel 0 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG1_Pos 1
| (DMAC_SWTRIGCTRL) Channel 1 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG2_Pos 2
| (DMAC_SWTRIGCTRL) Channel 2 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG3_Pos 3
| (DMAC_SWTRIGCTRL) Channel 3 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG4_Pos 4
| (DMAC_SWTRIGCTRL) Channel 4 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG5_Pos 5
| (DMAC_SWTRIGCTRL) Channel 5 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG6_Pos 6
| (DMAC_SWTRIGCTRL) Channel 6 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG7_Pos 7
| (DMAC_SWTRIGCTRL) Channel 7 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG8_Pos 8
| (DMAC_SWTRIGCTRL) Channel 8 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG9_Pos 9
| (DMAC_SWTRIGCTRL) Channel 9 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG10_Pos 10
| (DMAC_SWTRIGCTRL) Channel 10 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG11_Pos 11
| (DMAC_SWTRIGCTRL) Channel 11 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG12_Pos 12
| (DMAC_SWTRIGCTRL) Channel 12 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG13_Pos 13
| (DMAC_SWTRIGCTRL) Channel 13 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG14_Pos 14
| (DMAC_SWTRIGCTRL) Channel 14 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG15_Pos 15
| (DMAC_SWTRIGCTRL) Channel 15 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG16_Pos 16
| (DMAC_SWTRIGCTRL) Channel 16 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG17_Pos 17
| (DMAC_SWTRIGCTRL) Channel 17 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG18_Pos 18
| (DMAC_SWTRIGCTRL) Channel 18 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG19_Pos 19
| (DMAC_SWTRIGCTRL) Channel 19 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG20_Pos 20
| (DMAC_SWTRIGCTRL) Channel 20 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG21_Pos 21
| (DMAC_SWTRIGCTRL) Channel 21 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG22_Pos 22
| (DMAC_SWTRIGCTRL) Channel 22 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG23_Pos 23
| (DMAC_SWTRIGCTRL) Channel 23 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG24_Pos 24
| (DMAC_SWTRIGCTRL) Channel 24 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG25_Pos 25
| (DMAC_SWTRIGCTRL) Channel 25 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG26_Pos 26
| (DMAC_SWTRIGCTRL) Channel 26 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG27_Pos 27
| (DMAC_SWTRIGCTRL) Channel 27 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG28_Pos 28
| (DMAC_SWTRIGCTRL) Channel 28 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG29_Pos 29
| (DMAC_SWTRIGCTRL) Channel 29 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG30_Pos 30
| (DMAC_SWTRIGCTRL) Channel 30 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG31_Pos 31
| (DMAC_SWTRIGCTRL) Channel 31 Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG_Pos 0
| (DMAC_SWTRIGCTRL) Channel x Software Trigger
#define | DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos)
#define | DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
#define | DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF)
| (DMAC_SWTRIGCTRL) MASK Register
#define | DMAC_PRICTRL0_OFFSET 0x14
| (DMAC_PRICTRL0 offset) Priority Control 0
#define | DMAC_PRICTRL0_RESETVALUE _U_(0x40404040)
| (DMAC_PRICTRL0 reset_value) Priority Control 0
#define | DMAC_PRICTRL0_LVLPRI0_Pos 0
| (DMAC_PRICTRL0) Level 0 Channel Priority Number
#define | DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos)
#define | DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
#define | DMAC_PRICTRL0_QOS0_Pos 5
| (DMAC_PRICTRL0) Level 0 Quality of Service
#define | DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos)
#define | DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos))
#define | DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0)
| (DMAC_PRICTRL0) Regular delivery
#define | DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1)
| (DMAC_PRICTRL0) Bandwidth shortage
#define | DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2)
| (DMAC_PRICTRL0) Latency sensitive
#define | DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3)
| (DMAC_PRICTRL0) Latency critical
#define | DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos)
#define | DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos)
#define | DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos)
#define | DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos)
#define | DMAC_PRICTRL0_RRLVLEN0_Pos 7
| (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable
#define | DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos)
#define | DMAC_PRICTRL0_LVLPRI1_Pos 8
| (DMAC_PRICTRL0) Level 1 Channel Priority Number
#define | DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos)
#define | DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
#define | DMAC_PRICTRL0_QOS1_Pos 13
| (DMAC_PRICTRL0) Level 1 Quality of Service
#define | DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos)
#define | DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos))
#define | DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0)
| (DMAC_PRICTRL0) Regular delivery
#define | DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1)
| (DMAC_PRICTRL0) Bandwidth shortage
#define | DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2)
| (DMAC_PRICTRL0) Latency sensitive
#define | DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3)
| (DMAC_PRICTRL0) Latency critical
#define | DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos)
#define | DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos)
#define | DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos)
#define | DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos)
#define | DMAC_PRICTRL0_RRLVLEN1_Pos 15
| (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable
#define | DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos)
#define | DMAC_PRICTRL0_LVLPRI2_Pos 16
| (DMAC_PRICTRL0) Level 2 Channel Priority Number
#define | DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos)
#define | DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
#define | DMAC_PRICTRL0_QOS2_Pos 21
| (DMAC_PRICTRL0) Level 2 Quality of Service
#define | DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos)
#define | DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos))
#define | DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0)
| (DMAC_PRICTRL0) Regular delivery
#define | DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1)
| (DMAC_PRICTRL0) Bandwidth shortage
#define | DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2)
| (DMAC_PRICTRL0) Latency sensitive
#define | DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3)
| (DMAC_PRICTRL0) Latency critical
#define | DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos)
#define | DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos)
#define | DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos)
#define | DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos)
#define | DMAC_PRICTRL0_RRLVLEN2_Pos 23
| (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable
#define | DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos)
#define | DMAC_PRICTRL0_LVLPRI3_Pos 24
| (DMAC_PRICTRL0) Level 3 Channel Priority Number
#define | DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos)
#define | DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
#define | DMAC_PRICTRL0_QOS3_Pos 29
| (DMAC_PRICTRL0) Level 3 Quality of Service
#define | DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos)
#define | DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos))
#define | DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0)
| (DMAC_PRICTRL0) Regular delivery
#define | DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1)
| (DMAC_PRICTRL0) Bandwidth shortage
#define | DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2)
| (DMAC_PRICTRL0) Latency sensitive
#define | DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3)
| (DMAC_PRICTRL0) Latency critical
#define | DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos)
#define | DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos)
#define | DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos)
#define | DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos)
#define | DMAC_PRICTRL0_RRLVLEN3_Pos 31
| (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable
#define | DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos)
#define | DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF)
| (DMAC_PRICTRL0) MASK Register
#define | DMAC_INTPEND_OFFSET 0x20
| (DMAC_INTPEND offset) Interrupt Pending
#define | DMAC_INTPEND_RESETVALUE _U_(0x0000)
| (DMAC_INTPEND reset_value) Interrupt Pending
#define | DMAC_INTPEND_ID_Pos 0
| (DMAC_INTPEND) Channel ID
#define | DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos)
#define | DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
#define | DMAC_INTPEND_TERR_Pos 8
| (DMAC_INTPEND) Transfer Error
#define | DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos)
#define | DMAC_INTPEND_TCMPL_Pos 9
| (DMAC_INTPEND) Transfer Complete
#define | DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos)
#define | DMAC_INTPEND_SUSP_Pos 10
| (DMAC_INTPEND) Channel Suspend
#define | DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos)
#define | DMAC_INTPEND_CRCERR_Pos 12
| (DMAC_INTPEND) CRC Error
#define | DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos)
#define | DMAC_INTPEND_FERR_Pos 13
| (DMAC_INTPEND) Fetch Error
#define | DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos)
#define | DMAC_INTPEND_BUSY_Pos 14
| (DMAC_INTPEND) Busy
#define | DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos)
#define | DMAC_INTPEND_PEND_Pos 15
| (DMAC_INTPEND) Pending
#define | DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos)
#define | DMAC_INTPEND_MASK _U_(0xF71F)
| (DMAC_INTPEND) MASK Register
#define | DMAC_INTSTATUS_OFFSET 0x24
| (DMAC_INTSTATUS offset) Interrupt Status
#define | DMAC_INTSTATUS_RESETVALUE _U_(0x00000000)
| (DMAC_INTSTATUS reset_value) Interrupt Status
#define | DMAC_INTSTATUS_CHINT0_Pos 0
| (DMAC_INTSTATUS) Channel 0 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos)
#define | DMAC_INTSTATUS_CHINT1_Pos 1
| (DMAC_INTSTATUS) Channel 1 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos)
#define | DMAC_INTSTATUS_CHINT2_Pos 2
| (DMAC_INTSTATUS) Channel 2 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos)
#define | DMAC_INTSTATUS_CHINT3_Pos 3
| (DMAC_INTSTATUS) Channel 3 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos)
#define | DMAC_INTSTATUS_CHINT4_Pos 4
| (DMAC_INTSTATUS) Channel 4 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos)
#define | DMAC_INTSTATUS_CHINT5_Pos 5
| (DMAC_INTSTATUS) Channel 5 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos)
#define | DMAC_INTSTATUS_CHINT6_Pos 6
| (DMAC_INTSTATUS) Channel 6 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos)
#define | DMAC_INTSTATUS_CHINT7_Pos 7
| (DMAC_INTSTATUS) Channel 7 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos)
#define | DMAC_INTSTATUS_CHINT8_Pos 8
| (DMAC_INTSTATUS) Channel 8 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos)
#define | DMAC_INTSTATUS_CHINT9_Pos 9
| (DMAC_INTSTATUS) Channel 9 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos)
#define | DMAC_INTSTATUS_CHINT10_Pos 10
| (DMAC_INTSTATUS) Channel 10 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos)
#define | DMAC_INTSTATUS_CHINT11_Pos 11
| (DMAC_INTSTATUS) Channel 11 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos)
#define | DMAC_INTSTATUS_CHINT12_Pos 12
| (DMAC_INTSTATUS) Channel 12 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos)
#define | DMAC_INTSTATUS_CHINT13_Pos 13
| (DMAC_INTSTATUS) Channel 13 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos)
#define | DMAC_INTSTATUS_CHINT14_Pos 14
| (DMAC_INTSTATUS) Channel 14 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos)
#define | DMAC_INTSTATUS_CHINT15_Pos 15
| (DMAC_INTSTATUS) Channel 15 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos)
#define | DMAC_INTSTATUS_CHINT16_Pos 16
| (DMAC_INTSTATUS) Channel 16 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos)
#define | DMAC_INTSTATUS_CHINT17_Pos 17
| (DMAC_INTSTATUS) Channel 17 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos)
#define | DMAC_INTSTATUS_CHINT18_Pos 18
| (DMAC_INTSTATUS) Channel 18 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos)
#define | DMAC_INTSTATUS_CHINT19_Pos 19
| (DMAC_INTSTATUS) Channel 19 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos)
#define | DMAC_INTSTATUS_CHINT20_Pos 20
| (DMAC_INTSTATUS) Channel 20 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos)
#define | DMAC_INTSTATUS_CHINT21_Pos 21
| (DMAC_INTSTATUS) Channel 21 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos)
#define | DMAC_INTSTATUS_CHINT22_Pos 22
| (DMAC_INTSTATUS) Channel 22 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos)
#define | DMAC_INTSTATUS_CHINT23_Pos 23
| (DMAC_INTSTATUS) Channel 23 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos)
#define | DMAC_INTSTATUS_CHINT24_Pos 24
| (DMAC_INTSTATUS) Channel 24 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos)
#define | DMAC_INTSTATUS_CHINT25_Pos 25
| (DMAC_INTSTATUS) Channel 25 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos)
#define | DMAC_INTSTATUS_CHINT26_Pos 26
| (DMAC_INTSTATUS) Channel 26 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos)
#define | DMAC_INTSTATUS_CHINT27_Pos 27
| (DMAC_INTSTATUS) Channel 27 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos)
#define | DMAC_INTSTATUS_CHINT28_Pos 28
| (DMAC_INTSTATUS) Channel 28 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos)
#define | DMAC_INTSTATUS_CHINT29_Pos 29
| (DMAC_INTSTATUS) Channel 29 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos)
#define | DMAC_INTSTATUS_CHINT30_Pos 30
| (DMAC_INTSTATUS) Channel 30 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos)
#define | DMAC_INTSTATUS_CHINT31_Pos 31
| (DMAC_INTSTATUS) Channel 31 Pending Interrupt
#define | DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos)
#define | DMAC_INTSTATUS_CHINT_Pos 0
| (DMAC_INTSTATUS) Channel x Pending Interrupt
#define | DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos)
#define | DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
#define | DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF)
| (DMAC_INTSTATUS) MASK Register
#define | DMAC_BUSYCH_OFFSET 0x28
| (DMAC_BUSYCH offset) Busy Channels
#define | DMAC_BUSYCH_RESETVALUE _U_(0x00000000)
| (DMAC_BUSYCH reset_value) Busy Channels
#define | DMAC_BUSYCH_BUSYCH0_Pos 0
| (DMAC_BUSYCH) Busy Channel 0
#define | DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos)
#define | DMAC_BUSYCH_BUSYCH1_Pos 1
| (DMAC_BUSYCH) Busy Channel 1
#define | DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos)
#define | DMAC_BUSYCH_BUSYCH2_Pos 2
| (DMAC_BUSYCH) Busy Channel 2
#define | DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos)
#define | DMAC_BUSYCH_BUSYCH3_Pos 3
| (DMAC_BUSYCH) Busy Channel 3
#define | DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos)
#define | DMAC_BUSYCH_BUSYCH4_Pos 4
| (DMAC_BUSYCH) Busy Channel 4
#define | DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos)
#define | DMAC_BUSYCH_BUSYCH5_Pos 5
| (DMAC_BUSYCH) Busy Channel 5
#define | DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos)
#define | DMAC_BUSYCH_BUSYCH6_Pos 6
| (DMAC_BUSYCH) Busy Channel 6
#define | DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos)
#define | DMAC_BUSYCH_BUSYCH7_Pos 7
| (DMAC_BUSYCH) Busy Channel 7
#define | DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos)
#define | DMAC_BUSYCH_BUSYCH8_Pos 8
| (DMAC_BUSYCH) Busy Channel 8
#define | DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos)
#define | DMAC_BUSYCH_BUSYCH9_Pos 9
| (DMAC_BUSYCH) Busy Channel 9
#define | DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos)
#define | DMAC_BUSYCH_BUSYCH10_Pos 10
| (DMAC_BUSYCH) Busy Channel 10
#define | DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos)
#define | DMAC_BUSYCH_BUSYCH11_Pos 11
| (DMAC_BUSYCH) Busy Channel 11
#define | DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos)
#define | DMAC_BUSYCH_BUSYCH12_Pos 12
| (DMAC_BUSYCH) Busy Channel 12
#define | DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos)
#define | DMAC_BUSYCH_BUSYCH13_Pos 13
| (DMAC_BUSYCH) Busy Channel 13
#define | DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos)
#define | DMAC_BUSYCH_BUSYCH14_Pos 14
| (DMAC_BUSYCH) Busy Channel 14
#define | DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos)
#define | DMAC_BUSYCH_BUSYCH15_Pos 15
| (DMAC_BUSYCH) Busy Channel 15
#define | DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos)
#define | DMAC_BUSYCH_BUSYCH16_Pos 16
| (DMAC_BUSYCH) Busy Channel 16
#define | DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos)
#define | DMAC_BUSYCH_BUSYCH17_Pos 17
| (DMAC_BUSYCH) Busy Channel 17
#define | DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos)
#define | DMAC_BUSYCH_BUSYCH18_Pos 18
| (DMAC_BUSYCH) Busy Channel 18
#define | DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos)
#define | DMAC_BUSYCH_BUSYCH19_Pos 19
| (DMAC_BUSYCH) Busy Channel 19
#define | DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos)
#define | DMAC_BUSYCH_BUSYCH20_Pos 20
| (DMAC_BUSYCH) Busy Channel 20
#define | DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos)
#define | DMAC_BUSYCH_BUSYCH21_Pos 21
| (DMAC_BUSYCH) Busy Channel 21
#define | DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos)
#define | DMAC_BUSYCH_BUSYCH22_Pos 22
| (DMAC_BUSYCH) Busy Channel 22
#define | DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos)
#define | DMAC_BUSYCH_BUSYCH23_Pos 23
| (DMAC_BUSYCH) Busy Channel 23
#define | DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos)
#define | DMAC_BUSYCH_BUSYCH24_Pos 24
| (DMAC_BUSYCH) Busy Channel 24
#define | DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos)
#define | DMAC_BUSYCH_BUSYCH25_Pos 25
| (DMAC_BUSYCH) Busy Channel 25
#define | DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos)
#define | DMAC_BUSYCH_BUSYCH26_Pos 26
| (DMAC_BUSYCH) Busy Channel 26
#define | DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos)
#define | DMAC_BUSYCH_BUSYCH27_Pos 27
| (DMAC_BUSYCH) Busy Channel 27
#define | DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos)
#define | DMAC_BUSYCH_BUSYCH28_Pos 28
| (DMAC_BUSYCH) Busy Channel 28
#define | DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos)
#define | DMAC_BUSYCH_BUSYCH29_Pos 29
| (DMAC_BUSYCH) Busy Channel 29
#define | DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos)
#define | DMAC_BUSYCH_BUSYCH30_Pos 30
| (DMAC_BUSYCH) Busy Channel 30
#define | DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos)
#define | DMAC_BUSYCH_BUSYCH31_Pos 31
| (DMAC_BUSYCH) Busy Channel 31
#define | DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos)
#define | DMAC_BUSYCH_BUSYCH_Pos 0
| (DMAC_BUSYCH) Busy Channel x
#define | DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos)
#define | DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
#define | DMAC_BUSYCH_MASK _U_(0xFFFFFFFF)
| (DMAC_BUSYCH) MASK Register
#define | DMAC_PENDCH_OFFSET 0x2C
| (DMAC_PENDCH offset) Pending Channels
#define | DMAC_PENDCH_RESETVALUE _U_(0x00000000)
| (DMAC_PENDCH reset_value) Pending Channels
#define | DMAC_PENDCH_PENDCH0_Pos 0
| (DMAC_PENDCH) Pending Channel 0
#define | DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos)
#define | DMAC_PENDCH_PENDCH1_Pos 1
| (DMAC_PENDCH) Pending Channel 1
#define | DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos)
#define | DMAC_PENDCH_PENDCH2_Pos 2
| (DMAC_PENDCH) Pending Channel 2
#define | DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos)
#define | DMAC_PENDCH_PENDCH3_Pos 3
| (DMAC_PENDCH) Pending Channel 3
#define | DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos)
#define | DMAC_PENDCH_PENDCH4_Pos 4
| (DMAC_PENDCH) Pending Channel 4
#define | DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos)
#define | DMAC_PENDCH_PENDCH5_Pos 5
| (DMAC_PENDCH) Pending Channel 5
#define | DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos)
#define | DMAC_PENDCH_PENDCH6_Pos 6
| (DMAC_PENDCH) Pending Channel 6
#define | DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos)
#define | DMAC_PENDCH_PENDCH7_Pos 7
| (DMAC_PENDCH) Pending Channel 7
#define | DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos)
#define | DMAC_PENDCH_PENDCH8_Pos 8
| (DMAC_PENDCH) Pending Channel 8
#define | DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos)
#define | DMAC_PENDCH_PENDCH9_Pos 9
| (DMAC_PENDCH) Pending Channel 9
#define | DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos)
#define | DMAC_PENDCH_PENDCH10_Pos 10
| (DMAC_PENDCH) Pending Channel 10
#define | DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos)
#define | DMAC_PENDCH_PENDCH11_Pos 11
| (DMAC_PENDCH) Pending Channel 11
#define | DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos)
#define | DMAC_PENDCH_PENDCH12_Pos 12
| (DMAC_PENDCH) Pending Channel 12
#define | DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos)
#define | DMAC_PENDCH_PENDCH13_Pos 13
| (DMAC_PENDCH) Pending Channel 13
#define | DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos)
#define | DMAC_PENDCH_PENDCH14_Pos 14
| (DMAC_PENDCH) Pending Channel 14
#define | DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos)
#define | DMAC_PENDCH_PENDCH15_Pos 15
| (DMAC_PENDCH) Pending Channel 15
#define | DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos)
#define | DMAC_PENDCH_PENDCH16_Pos 16
| (DMAC_PENDCH) Pending Channel 16
#define | DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos)
#define | DMAC_PENDCH_PENDCH17_Pos 17
| (DMAC_PENDCH) Pending Channel 17
#define | DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos)
#define | DMAC_PENDCH_PENDCH18_Pos 18
| (DMAC_PENDCH) Pending Channel 18
#define | DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos)
#define | DMAC_PENDCH_PENDCH19_Pos 19
| (DMAC_PENDCH) Pending Channel 19
#define | DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos)
#define | DMAC_PENDCH_PENDCH20_Pos 20
| (DMAC_PENDCH) Pending Channel 20
#define | DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos)
#define | DMAC_PENDCH_PENDCH21_Pos 21
| (DMAC_PENDCH) Pending Channel 21
#define | DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos)
#define | DMAC_PENDCH_PENDCH22_Pos 22
| (DMAC_PENDCH) Pending Channel 22
#define | DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos)
#define | DMAC_PENDCH_PENDCH23_Pos 23
| (DMAC_PENDCH) Pending Channel 23
#define | DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos)
#define | DMAC_PENDCH_PENDCH24_Pos 24
| (DMAC_PENDCH) Pending Channel 24
#define | DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos)
#define | DMAC_PENDCH_PENDCH25_Pos 25
| (DMAC_PENDCH) Pending Channel 25
#define | DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos)
#define | DMAC_PENDCH_PENDCH26_Pos 26
| (DMAC_PENDCH) Pending Channel 26
#define | DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos)
#define | DMAC_PENDCH_PENDCH27_Pos 27
| (DMAC_PENDCH) Pending Channel 27
#define | DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos)
#define | DMAC_PENDCH_PENDCH28_Pos 28
| (DMAC_PENDCH) Pending Channel 28
#define | DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos)
#define | DMAC_PENDCH_PENDCH29_Pos 29
| (DMAC_PENDCH) Pending Channel 29
#define | DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos)
#define | DMAC_PENDCH_PENDCH30_Pos 30
| (DMAC_PENDCH) Pending Channel 30
#define | DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos)
#define | DMAC_PENDCH_PENDCH31_Pos 31
| (DMAC_PENDCH) Pending Channel 31
#define | DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos)
#define | DMAC_PENDCH_PENDCH_Pos 0
| (DMAC_PENDCH) Pending Channel x
#define | DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos)
#define | DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
#define | DMAC_PENDCH_MASK _U_(0xFFFFFFFF)
| (DMAC_PENDCH) MASK Register
#define | DMAC_ACTIVE_OFFSET 0x30
| (DMAC_ACTIVE offset) Active Channel and Levels
#define | DMAC_ACTIVE_RESETVALUE _U_(0x00000000)
| (DMAC_ACTIVE reset_value) Active Channel and Levels
#define | DMAC_ACTIVE_LVLEX0_Pos 0
| (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing
#define | DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos)
#define | DMAC_ACTIVE_LVLEX1_Pos 1
| (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing
#define | DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos)
#define | DMAC_ACTIVE_LVLEX2_Pos 2
| (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing
#define | DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos)
#define | DMAC_ACTIVE_LVLEX3_Pos 3
| (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing
#define | DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos)
#define | DMAC_ACTIVE_LVLEX_Pos 0
| (DMAC_ACTIVE) Level x Channel Trigger Request Executing
#define | DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos)
#define | DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
#define | DMAC_ACTIVE_ID_Pos 8
| (DMAC_ACTIVE) Active Channel ID
#define | DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos)
#define | DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
#define | DMAC_ACTIVE_ABUSY_Pos 15
| (DMAC_ACTIVE) Active Channel Busy
#define | DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos)
#define | DMAC_ACTIVE_BTCNT_Pos 16
| (DMAC_ACTIVE) Active Channel Block Transfer Count
#define | DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos)
#define | DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
#define | DMAC_ACTIVE_MASK _U_(0xFFFF9F0F)
| (DMAC_ACTIVE) MASK Register
#define | DMAC_BASEADDR_OFFSET 0x34
| (DMAC_BASEADDR offset) Descriptor Memory Section Base Address
#define | DMAC_BASEADDR_RESETVALUE _U_(0x00000000)
| (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address
#define | DMAC_BASEADDR_BASEADDR_Pos 0
| (DMAC_BASEADDR) Descriptor Memory Base Address
#define | DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos)
#define | DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
#define | DMAC_BASEADDR_MASK _U_(0xFFFFFFFF)
| (DMAC_BASEADDR) MASK Register
#define | DMAC_WRBADDR_OFFSET 0x38
| (DMAC_WRBADDR offset) Write-Back Memory Section Base Address
#define | DMAC_WRBADDR_RESETVALUE _U_(0x00000000)
| (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address
#define | DMAC_WRBADDR_WRBADDR_Pos 0
| (DMAC_WRBADDR) Write-Back Memory Base Address
#define | DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos)
#define | DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
#define | DMAC_WRBADDR_MASK _U_(0xFFFFFFFF)
| (DMAC_WRBADDR) MASK Register
#define | DMAC_CHCTRLA_OFFSET 0x40
| (DMAC_CHCTRLA offset) Channel n Control A
#define | DMAC_CHCTRLA_RESETVALUE _U_(0x00000000)
| (DMAC_CHCTRLA reset_value) Channel n Control A
#define | DMAC_CHCTRLA_SWRST_Pos 0
| (DMAC_CHCTRLA) Channel Software Reset
#define | DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos)
#define | DMAC_CHCTRLA_ENABLE_Pos 1
| (DMAC_CHCTRLA) Channel Enable
#define | DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos)
#define | DMAC_CHCTRLA_RUNSTDBY_Pos 6
| (DMAC_CHCTRLA) Channel Run in Standby
#define | DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos)
#define | DMAC_CHCTRLA_TRIGSRC_Pos 8
| (DMAC_CHCTRLA) Trigger Source
#define | DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos)
#define | DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos))
#define | DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0)
| (DMAC_CHCTRLA) Only software/event triggers
#define | DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos)
#define | DMAC_CHCTRLA_TRIGACT_Pos 20
| (DMAC_CHCTRLA) Trigger Action
#define | DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos)
#define | DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos))
#define | DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0)
| (DMAC_CHCTRLA) One trigger required for each block transfer
#define | DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2)
| (DMAC_CHCTRLA) One trigger required for each burst transfer
#define | DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3)
| (DMAC_CHCTRLA) One trigger required for each transaction
#define | DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos)
#define | DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos)
#define | DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_Pos 24
| (DMAC_CHCTRLA) Burst Length
#define | DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos))
#define | DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0)
| (DMAC_CHCTRLA) Single-beat burst length
#define | DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1)
| (DMAC_CHCTRLA) 2-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2)
| (DMAC_CHCTRLA) 3-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3)
| (DMAC_CHCTRLA) 4-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4)
| (DMAC_CHCTRLA) 5-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5)
| (DMAC_CHCTRLA) 6-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6)
| (DMAC_CHCTRLA) 7-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7)
| (DMAC_CHCTRLA) 8-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8)
| (DMAC_CHCTRLA) 9-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9)
| (DMAC_CHCTRLA) 10-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA)
| (DMAC_CHCTRLA) 11-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB)
| (DMAC_CHCTRLA) 12-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC)
| (DMAC_CHCTRLA) 13-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD)
| (DMAC_CHCTRLA) 14-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE)
| (DMAC_CHCTRLA) 15-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF)
| (DMAC_CHCTRLA) 16-beats burst length
#define | DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos)
#define | DMAC_CHCTRLA_THRESHOLD_Pos 28
| (DMAC_CHCTRLA) FIFO Threshold
#define | DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos)
#define | DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos))
#define | DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0)
| (DMAC_CHCTRLA) Destination write starts after each beat source address read
#define | DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1)
| (DMAC_CHCTRLA) Destination write starts after 2-beats source address read
#define | DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2)
| (DMAC_CHCTRLA) Destination write starts after 4-beats source address read
#define | DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3)
| (DMAC_CHCTRLA) Destination write starts after 8-beats source address read
#define | DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
#define | DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
#define | DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
#define | DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos)
#define | DMAC_CHCTRLA_MASK _U_(0x3F307F43)
| (DMAC_CHCTRLA) MASK Register
#define | DMAC_CHCTRLB_OFFSET 0x44
| (DMAC_CHCTRLB offset) Channel n Control B
#define | DMAC_CHCTRLB_RESETVALUE _U_(0x00)
| (DMAC_CHCTRLB reset_value) Channel n Control B
#define | DMAC_CHCTRLB_CMD_Pos 0
| (DMAC_CHCTRLB) Software Command
#define | DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos)
#define | DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
#define | DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0)
| (DMAC_CHCTRLB) No action
#define | DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1)
| (DMAC_CHCTRLB) Channel suspend operation
#define | DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2)
| (DMAC_CHCTRLB) Channel resume operation
#define | DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos)
#define | DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos)
#define | DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos)
#define | DMAC_CHCTRLB_MASK _U_(0x03)
| (DMAC_CHCTRLB) MASK Register
#define | DMAC_CHPRILVL_OFFSET 0x45
| (DMAC_CHPRILVL offset) Channel n Priority Level
#define | DMAC_CHPRILVL_RESETVALUE _U_(0x00)
| (DMAC_CHPRILVL reset_value) Channel n Priority Level
#define | DMAC_CHPRILVL_PRILVL_Pos 0
| (DMAC_CHPRILVL) Channel Priority Level
#define | DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos))
#define | DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0)
| (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level)
#define | DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1)
| (DMAC_CHPRILVL) Channel Priority Level 1
#define | DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2)
| (DMAC_CHPRILVL) Channel Priority Level 2
#define | DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3)
| (DMAC_CHPRILVL) Channel Priority Level 3
#define | DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4)
| (DMAC_CHPRILVL) Channel Priority Level 4
#define | DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5)
| (DMAC_CHPRILVL) Channel Priority Level 5
#define | DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6)
| (DMAC_CHPRILVL) Channel Priority Level 6
#define | DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7)
| (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level)
#define | DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos)
#define | DMAC_CHPRILVL_MASK _U_(0x03)
| (DMAC_CHPRILVL) MASK Register
#define | DMAC_CHEVCTRL_OFFSET 0x46
| (DMAC_CHEVCTRL offset) Channel n Event Control
#define | DMAC_CHEVCTRL_RESETVALUE _U_(0x00)
| (DMAC_CHEVCTRL reset_value) Channel n Event Control
#define | DMAC_CHEVCTRL_EVACT_Pos 0
| (DMAC_CHEVCTRL) Channel Event Input Action
#define | DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos))
#define | DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0)
| (DMAC_CHEVCTRL) No action
#define | DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1)
| (DMAC_CHEVCTRL) Transfer and periodic transfer trigger
#define | DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2)
| (DMAC_CHEVCTRL) Conditional transfer trigger
#define | DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3)
| (DMAC_CHEVCTRL) Conditional block transfer
#define | DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4)
| (DMAC_CHEVCTRL) Channel suspend operation
#define | DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5)
| (DMAC_CHEVCTRL) Channel resume operation
#define | DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6)
| (DMAC_CHEVCTRL) Skip next block suspend action
#define | DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7)
| (DMAC_CHEVCTRL) Increase priority
#define | DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos)
#define | DMAC_CHEVCTRL_EVOMODE_Pos 4
| (DMAC_CHEVCTRL) Channel Event Output Mode
#define | DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos)
#define | DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos))
#define | DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0)
| (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
#define | DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1)
| (DMAC_CHEVCTRL) Ongoing trigger action
#define | DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
#define | DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos)
#define | DMAC_CHEVCTRL_EVIE_Pos 6
| (DMAC_CHEVCTRL) Channel Event Input Enable
#define | DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos)
#define | DMAC_CHEVCTRL_EVOE_Pos 7
| (DMAC_CHEVCTRL) Channel Event Output Enable
#define | DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos)
#define | DMAC_CHEVCTRL_MASK _U_(0xF7)
| (DMAC_CHEVCTRL) MASK Register
#define | DMAC_CHINTENCLR_OFFSET 0x4C
| (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear
#define | DMAC_CHINTENCLR_RESETVALUE _U_(0x00)
| (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear
#define | DMAC_CHINTENCLR_TERR_Pos 0
| (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable
#define | DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos)
#define | DMAC_CHINTENCLR_TCMPL_Pos 1
| (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable
#define | DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos)
#define | DMAC_CHINTENCLR_SUSP_Pos 2
| (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable
#define | DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos)
#define | DMAC_CHINTENCLR_MASK _U_(0x07)
| (DMAC_CHINTENCLR) MASK Register
#define | DMAC_CHINTENSET_OFFSET 0x4D
| (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set
#define | DMAC_CHINTENSET_RESETVALUE _U_(0x00)
| (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set
#define | DMAC_CHINTENSET_TERR_Pos 0
| (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable
#define | DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos)
#define | DMAC_CHINTENSET_TCMPL_Pos 1
| (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable
#define | DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos)
#define | DMAC_CHINTENSET_SUSP_Pos 2
| (DMAC_CHINTENSET) Channel Suspend Interrupt Enable
#define | DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos)
#define | DMAC_CHINTENSET_MASK _U_(0x07)
| (DMAC_CHINTENSET) MASK Register
#define | DMAC_CHINTFLAG_OFFSET 0x4E
| (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear
#define | DMAC_CHINTFLAG_RESETVALUE _U_(0x00)
| (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear
#define | DMAC_CHINTFLAG_TERR_Pos 0
| (DMAC_CHINTFLAG) Channel Transfer Error
#define | DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos)
#define | DMAC_CHINTFLAG_TCMPL_Pos 1
| (DMAC_CHINTFLAG) Channel Transfer Complete
#define | DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos)
#define | DMAC_CHINTFLAG_SUSP_Pos 2
| (DMAC_CHINTFLAG) Channel Suspend
#define | DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos)
#define | DMAC_CHINTFLAG_MASK _U_(0x07)
| (DMAC_CHINTFLAG) MASK Register
#define | DMAC_CHSTATUS_OFFSET 0x4F
| (DMAC_CHSTATUS offset) Channel n Status
#define | DMAC_CHSTATUS_RESETVALUE _U_(0x00)
| (DMAC_CHSTATUS reset_value) Channel n Status
#define | DMAC_CHSTATUS_PEND_Pos 0
| (DMAC_CHSTATUS) Channel Pending
#define | DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos)
#define | DMAC_CHSTATUS_BUSY_Pos 1
| (DMAC_CHSTATUS) Channel Busy
#define | DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos)
#define | DMAC_CHSTATUS_FERR_Pos 2
| (DMAC_CHSTATUS) Channel Fetch Error
#define | DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos)
#define | DMAC_CHSTATUS_CRCERR_Pos 3
| (DMAC_CHSTATUS) Channel CRC Error
#define | DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos)
#define | DMAC_CHSTATUS_MASK _U_(0x0F)
| (DMAC_CHSTATUS) MASK Register
#define | DMAC_BTCTRL_OFFSET 0x00
| (DMAC_BTCTRL offset) Block Transfer Control
#define | DMAC_BTCTRL_RESETVALUE _U_(0x0000)
| (DMAC_BTCTRL reset_value) Block Transfer Control
#define | DMAC_BTCTRL_VALID_Pos 0
| (DMAC_BTCTRL) Descriptor Valid
#define | DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos)
#define | DMAC_BTCTRL_EVOSEL_Pos 1
| (DMAC_BTCTRL) Block Event Output Selection
#define | DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos)
#define | DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
#define | DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0)
| (DMAC_BTCTRL) Event generation disabled
#define | DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1)
| (DMAC_BTCTRL) Block event strobe
#define | DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3)
| (DMAC_BTCTRL) Burst event strobe
#define | DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
#define | DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos)
#define | DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos)
#define | DMAC_BTCTRL_BLOCKACT_Pos 3
| (DMAC_BTCTRL) Block Action
#define | DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos)
#define | DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
#define | DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0)
| (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction
#define | DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1)
| (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt
#define | DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2)
| (DMAC_BTCTRL) Channel suspend operation is completed
#define | DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3)
| (DMAC_BTCTRL) Both channel suspend operation and block interrupt
#define | DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
#define | DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
#define | DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
#define | DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
#define | DMAC_BTCTRL_BEATSIZE_Pos 8
| (DMAC_BTCTRL) Beat Size
#define | DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos)
#define | DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
#define | DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0)
| (DMAC_BTCTRL) 8-bit bus transfer
#define | DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1)
| (DMAC_BTCTRL) 16-bit bus transfer
#define | DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2)
| (DMAC_BTCTRL) 32-bit bus transfer
#define | DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
#define | DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
#define | DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
#define | DMAC_BTCTRL_SRCINC_Pos 10
| (DMAC_BTCTRL) Source Address Increment Enable
#define | DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos)
#define | DMAC_BTCTRL_DSTINC_Pos 11
| (DMAC_BTCTRL) Destination Address Increment Enable
#define | DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos)
#define | DMAC_BTCTRL_STEPSEL_Pos 12
| (DMAC_BTCTRL) Step Selection
#define | DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos)
#define | DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0)
| (DMAC_BTCTRL) Step size settings apply to the destination address
#define | DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1)
| (DMAC_BTCTRL) Step size settings apply to the source address
#define | DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos)
#define | DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
#define | DMAC_BTCTRL_STEPSIZE_Pos 13
| (DMAC_BTCTRL) Address Increment Step Size
#define | DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
#define | DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 1
#define | DMAC_BTCTRL_STEPSIZE_X2_Val _U_(0x1)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 2
#define | DMAC_BTCTRL_STEPSIZE_X4_Val _U_(0x2)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 4
#define | DMAC_BTCTRL_STEPSIZE_X8_Val _U_(0x3)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 8
#define | DMAC_BTCTRL_STEPSIZE_X16_Val _U_(0x4)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 16
#define | DMAC_BTCTRL_STEPSIZE_X32_Val _U_(0x5)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 32
#define | DMAC_BTCTRL_STEPSIZE_X64_Val _U_(0x6)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 64
#define | DMAC_BTCTRL_STEPSIZE_X128_Val _U_(0x7)
| (DMAC_BTCTRL) Next ADDR = ADDR + (1<<BEATSIZE) * 128
#define | DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE_X8 (DMAC_BTCTRL_STEPSIZE_X8_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE_X16 (DMAC_BTCTRL_STEPSIZE_X16_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE_X32 (DMAC_BTCTRL_STEPSIZE_X32_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE_X64 (DMAC_BTCTRL_STEPSIZE_X64_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_STEPSIZE_X128 (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define | DMAC_BTCTRL_MASK _U_(0xFF1F)
| (DMAC_BTCTRL) MASK Register
#define | DMAC_BTCNT_OFFSET 0x02
| (DMAC_BTCNT offset) Block Transfer Count
#define | DMAC_BTCNT_RESETVALUE _U_(0x0000)
| (DMAC_BTCNT reset_value) Block Transfer Count
#define | DMAC_BTCNT_BTCNT_Pos 0
| (DMAC_BTCNT) Block Transfer Count
#define | DMAC_BTCNT_BTCNT_Msk (_U_(0xFFFF) << DMAC_BTCNT_BTCNT_Pos)
#define | DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
#define | DMAC_BTCNT_MASK _U_(0xFFFF)
| (DMAC_BTCNT) MASK Register
#define | DMAC_SRCADDR_OFFSET 0x04
| (DMAC_SRCADDR offset) Block Transfer Source Address
#define | DMAC_SRCADDR_RESETVALUE _U_(0x00000000)
| (DMAC_SRCADDR reset_value) Block Transfer Source Address
#define | DMAC_SRCADDR_SRCADDR_Pos 0
| (DMAC_SRCADDR) Transfer Source Address
#define | DMAC_SRCADDR_SRCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_SRCADDR_SRCADDR_Pos)
#define | DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
#define | DMAC_SRCADDR_MASK _U_(0xFFFFFFFF)
| (DMAC_SRCADDR) MASK Register
#define | DMAC_DSTADDR_OFFSET 0x08
| (DMAC_DSTADDR offset) Block Transfer Destination Address
#define | DMAC_DSTADDR_CRC_CHKINIT_Pos 0
| (DMAC_DSTADDR_CRC) CRC Checksum Initial Value
#define | DMAC_DSTADDR_CRC_CHKINIT_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_CRC_CHKINIT_Pos)
#define | DMAC_DSTADDR_CRC_CHKINIT(value) (DMAC_DSTADDR_CRC_CHKINIT_Msk & ((value) << DMAC_DSTADDR_CRC_CHKINIT_Pos))
#define | DMAC_DSTADDR_CRC_MASK _U_(0xFFFFFFFF)
| (DMAC_DSTADDR_CRC) MASK Register
#define | DMAC_DSTADDR_DSTADDR_Pos 0
| (DMAC_DSTADDR) Transfer Destination Address
#define | DMAC_DSTADDR_DSTADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DSTADDR_DSTADDR_Pos)
#define | DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
#define | DMAC_DSTADDR_MASK _U_(0xFFFFFFFF)
| (DMAC_DSTADDR) MASK Register
#define | DMAC_DESCADDR_OFFSET 0x0C
| (DMAC_DESCADDR offset) Next Descriptor Address
#define | DMAC_DESCADDR_DESCADDR_Pos 0
| (DMAC_DESCADDR) Next Descriptor Address
#define | DMAC_DESCADDR_DESCADDR_Msk (_U_(0xFFFFFFFF) << DMAC_DESCADDR_DESCADDR_Pos)
#define | DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
#define | DMAC_DESCADDR_MASK _U_(0xFFFFFFFF)
| (DMAC_DESCADDR) MASK Register

## Detailed Description

Component description for DMAC.

Copyright (c) 2019 Microchip Technology Inc.

\asf_license_start

Definition in file dmac.h.