gclk.h
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#ifndef _SAME54_GCLK_COMPONENT_
#define _SAME54_GCLK_COMPONENT_
/* ========================================================================== */
/* ========================================================================== */
#define GCLK_U2122
#define REV_GCLK 0x120
/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1;
uint8_t :7;
} bit;
uint8_t reg;
} GCLK_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_CTRLA_OFFSET 0x00
#define GCLK_CTRLA_RESETVALUE _U_(0x00)
#define GCLK_CTRLA_SWRST_Pos 0
#define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
#define GCLK_CTRLA_MASK _U_(0x01)
/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1;
uint32_t :1;
uint32_t GENCTRL0:1;
uint32_t GENCTRL1:1;
uint32_t GENCTRL2:1;
uint32_t GENCTRL3:1;
uint32_t GENCTRL4:1;
uint32_t GENCTRL5:1;
uint32_t GENCTRL6:1;
uint32_t GENCTRL7:1;
uint32_t GENCTRL8:1;
uint32_t GENCTRL9:1;
uint32_t GENCTRL10:1;
uint32_t GENCTRL11:1;
uint32_t :18;
} bit;
struct {
uint32_t :2;
uint32_t GENCTRL:12;
uint32_t :18;
} vec;
uint32_t reg;
} GCLK_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_SYNCBUSY_OFFSET 0x04
#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000)
#define GCLK_SYNCBUSY_SWRST_Pos 0
#define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
#define GCLK_SYNCBUSY_GENCTRL0_Pos 2
#define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
#define GCLK_SYNCBUSY_GENCTRL1_Pos 3
#define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
#define GCLK_SYNCBUSY_GENCTRL2_Pos 4
#define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
#define GCLK_SYNCBUSY_GENCTRL3_Pos 5
#define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
#define GCLK_SYNCBUSY_GENCTRL4_Pos 6
#define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
#define GCLK_SYNCBUSY_GENCTRL5_Pos 7
#define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
#define GCLK_SYNCBUSY_GENCTRL6_Pos 8
#define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
#define GCLK_SYNCBUSY_GENCTRL7_Pos 9
#define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
#define GCLK_SYNCBUSY_GENCTRL8_Pos 10
#define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
#define GCLK_SYNCBUSY_GENCTRL9_Pos 11
#define GCLK_SYNCBUSY_GENCTRL9 (_U_(1) << GCLK_SYNCBUSY_GENCTRL9_Pos)
#define GCLK_SYNCBUSY_GENCTRL10_Pos 12
#define GCLK_SYNCBUSY_GENCTRL10 (_U_(1) << GCLK_SYNCBUSY_GENCTRL10_Pos)
#define GCLK_SYNCBUSY_GENCTRL11_Pos 13
#define GCLK_SYNCBUSY_GENCTRL11 (_U_(1) << GCLK_SYNCBUSY_GENCTRL11_Pos)
#define GCLK_SYNCBUSY_GENCTRL_Pos 2
#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0xFFF) << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1)
#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2)
#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4)
#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8)
#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10)
#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20)
#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40)
#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80)
#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100)
#define GCLK_SYNCBUSY_GENCTRL_GCLK9_Val _U_(0x200)
#define GCLK_SYNCBUSY_GENCTRL_GCLK10_Val _U_(0x400)
#define GCLK_SYNCBUSY_GENCTRL_GCLK11_Val _U_(0x800)
#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK9 (GCLK_SYNCBUSY_GENCTRL_GCLK9_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK10 (GCLK_SYNCBUSY_GENCTRL_GCLK10_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK11 (GCLK_SYNCBUSY_GENCTRL_GCLK11_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_MASK _U_(0x00003FFD)
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SRC:4;
uint32_t :4;
uint32_t GENEN:1;
uint32_t IDC:1;
uint32_t OOV:1;
uint32_t OE:1;
uint32_t DIVSEL:1;
uint32_t RUNSTDBY:1;
uint32_t :2;
uint32_t DIV:16;
} bit;
uint32_t reg;
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_GENCTRL_OFFSET 0x20
#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000)
#define GCLK_GENCTRL_SRC_Pos 0
#define GCLK_GENCTRL_SRC_Msk (_U_(0xF) << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
#define GCLK_GENCTRL_SRC_XOSC0_Val _U_(0x0)
#define GCLK_GENCTRL_SRC_XOSC1_Val _U_(0x1)
#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x2)
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x3)
#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x4)
#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5)
#define GCLK_GENCTRL_SRC_DFLL_Val _U_(0x6)
#define GCLK_GENCTRL_SRC_DPLL0_Val _U_(0x7)
#define GCLK_GENCTRL_SRC_DPLL1_Val _U_(0x8)
#define GCLK_GENCTRL_SRC_XOSC0 (GCLK_GENCTRL_SRC_XOSC0_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_XOSC1 (GCLK_GENCTRL_SRC_XOSC1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DFLL (GCLK_GENCTRL_SRC_DFLL_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DPLL0 (GCLK_GENCTRL_SRC_DPLL0_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DPLL1 (GCLK_GENCTRL_SRC_DPLL1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_GENEN_Pos 8
#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
#define GCLK_GENCTRL_IDC_Pos 9
#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
#define GCLK_GENCTRL_OOV_Pos 10
#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
#define GCLK_GENCTRL_OE_Pos 11
#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
#define GCLK_GENCTRL_DIVSEL_Pos 12
#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
#define GCLK_GENCTRL_RUNSTDBY_Pos 13
#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
#define GCLK_GENCTRL_DIV_Pos 16
#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
#define GCLK_GENCTRL_MASK _U_(0xFFFF3F0F)
/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t GEN:4;
uint32_t :2;
uint32_t CHEN:1;
uint32_t WRTLOCK:1;
uint32_t :24;
} bit;
uint32_t reg;
} GCLK_PCHCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_PCHCTRL_OFFSET 0x80
#define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000)
#define GCLK_PCHCTRL_GEN_Pos 0
#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0)
#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1)
#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2)
#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3)
#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4)
#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5)
#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6)
#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7)
#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8)
#define GCLK_PCHCTRL_GEN_GCLK9_Val _U_(0x9)
#define GCLK_PCHCTRL_GEN_GCLK10_Val _U_(0xA)
#define GCLK_PCHCTRL_GEN_GCLK11_Val _U_(0xB)
#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK9 (GCLK_PCHCTRL_GEN_GCLK9_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK10 (GCLK_PCHCTRL_GEN_GCLK10_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK11 (GCLK_PCHCTRL_GEN_GCLK11_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_CHEN_Pos 6
#define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
#define GCLK_PCHCTRL_WRTLOCK_Pos 7
#define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
#define GCLK_PCHCTRL_MASK _U_(0x000000CF)
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO GCLK_CTRLA_Type CTRLA;
RoReg8 Reserved1[0x3];
__I GCLK_SYNCBUSY_Type SYNCBUSY;
RoReg8 Reserved2[0x18];
__IO GCLK_GENCTRL_Type GENCTRL[12];
RoReg8 Reserved3[0x30];
__IO GCLK_PCHCTRL_Type PCHCTRL[48];
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME54_GCLK_COMPONENT_ */
GCLK_GENCTRL_Type::reg
uint32_t reg
Definition: gclk.h:162
GCLK_GENCTRL_Type::GENEN
uint32_t GENEN
Definition: gclk.h:153
GCLK_SYNCBUSY_Type::GENCTRL10
uint32_t GENCTRL10
Definition: gclk.h:76
GCLK_GENCTRL_Type::DIV
uint32_t DIV
Definition: gclk.h:160
GCLK_PCHCTRL_Type::reg
uint32_t reg
Definition: gclk.h:217
GCLK_GENCTRL_Type::OOV
uint32_t OOV
Definition: gclk.h:155
GCLK_PCHCTRL_Type::GEN
uint32_t GEN
Definition: gclk.h:211
GCLK_PCHCTRL_Type::WRTLOCK
uint32_t WRTLOCK
Definition: gclk.h:214
GCLK_SYNCBUSY_Type::GENCTRL0
uint32_t GENCTRL0
Definition: gclk.h:66
GCLK_PCHCTRL_Type
Definition: gclk.h:209
GCLK_SYNCBUSY_Type::SWRST
uint32_t SWRST
Definition: gclk.h:64
GCLK_SYNCBUSY_Type::GENCTRL2
uint32_t GENCTRL2
Definition: gclk.h:68
GCLK_SYNCBUSY_Type
Definition: gclk.h:62
Gclk
GCLK hardware registers.
Definition: gclk.h:259
GCLK_SYNCBUSY_Type::GENCTRL9
uint32_t GENCTRL9
Definition: gclk.h:75
GCLK_SYNCBUSY_Type::GENCTRL8
uint32_t GENCTRL8
Definition: gclk.h:74
GCLK_SYNCBUSY_Type::GENCTRL4
uint32_t GENCTRL4
Definition: gclk.h:70
GCLK_SYNCBUSY_Type::GENCTRL5
uint32_t GENCTRL5
Definition: gclk.h:71
GCLK_GENCTRL_Type::IDC
uint32_t IDC
Definition: gclk.h:154
Gclk::SYNCBUSY
__I GCLK_SYNCBUSY_Type SYNCBUSY
Offset: 0x04 (R/ 32) Synchronization Busy.
Definition: gclk.h:262
GCLK_CTRLA_Type::reg
uint8_t reg
Definition: gclk.h:49
Gclk::CTRLA
__IO GCLK_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control.
Definition: gclk.h:260
GCLK_GENCTRL_Type::DIVSEL
uint32_t DIVSEL
Definition: gclk.h:157
GCLK_PCHCTRL_Type::CHEN
uint32_t CHEN
Definition: gclk.h:213
GCLK_SYNCBUSY_Type::GENCTRL7
uint32_t GENCTRL7
Definition: gclk.h:73
GCLK_CTRLA_Type::SWRST
uint8_t SWRST
Definition: gclk.h:46
GCLK_GENCTRL_Type
Definition: gclk.h:149
GCLK_SYNCBUSY_Type::GENCTRL1
uint32_t GENCTRL1
Definition: gclk.h:67
GCLK_SYNCBUSY_Type::GENCTRL3
uint32_t GENCTRL3
Definition: gclk.h:69
GCLK_GENCTRL_Type::OE
uint32_t OE
Definition: gclk.h:156
GCLK_CTRLA_Type
Definition: gclk.h:44
GCLK_GENCTRL_Type::SRC
uint32_t SRC
Definition: gclk.h:151
GCLK_SYNCBUSY_Type::GENCTRL6
uint32_t GENCTRL6
Definition: gclk.h:72
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
GCLK_SYNCBUSY_Type::reg
uint32_t reg
Definition: gclk.h:85
GCLK_SYNCBUSY_Type::GENCTRL
uint32_t GENCTRL
Definition: gclk.h:82
GCLK_SYNCBUSY_Type::GENCTRL11
uint32_t GENCTRL11
Definition: gclk.h:77
GCLK_GENCTRL_Type::RUNSTDBY
uint32_t RUNSTDBY
Definition: gclk.h:158