tcc.h File Reference

Component description for TCC. More...

Go to the source code of this file.

## Data Structures

union | TCC_CTRLA_Type
union | TCC_CTRLBCLR_Type
union | TCC_CTRLBSET_Type
union | TCC_SYNCBUSY_Type
union | TCC_FCTRLA_Type
union | TCC_FCTRLB_Type
union | TCC_WEXCTRL_Type
union | TCC_DRVCTRL_Type
union | TCC_DBGCTRL_Type
union | TCC_EVCTRL_Type
union | TCC_INTENCLR_Type
union | TCC_INTENSET_Type
union | TCC_INTFLAG_Type
union | TCC_STATUS_Type
union | TCC_COUNT_Type
union | TCC_PATT_Type
union | TCC_WAVE_Type
union | TCC_PER_Type
union | TCC_CC_Type
union | TCC_PATTBUF_Type
union | TCC_PERBUF_Type
union | TCC_CCBUF_Type
struct | Tcc
| TCC hardware registers. More...

## Macros

#define | TCC_U2213
#define | REV_TCC 0x310
#define | TCC_CTRLA_OFFSET 0x00
| (TCC_CTRLA offset) Control A
#define | TCC_CTRLA_RESETVALUE _U_(0x00000000)
| (TCC_CTRLA reset_value) Control A
#define | TCC_CTRLA_SWRST_Pos 0
| (TCC_CTRLA) Software Reset
#define | TCC_CTRLA_SWRST (_U_(0x1) << TCC_CTRLA_SWRST_Pos)
#define | TCC_CTRLA_ENABLE_Pos 1
| (TCC_CTRLA) Enable
#define | TCC_CTRLA_ENABLE (_U_(0x1) << TCC_CTRLA_ENABLE_Pos)
#define | TCC_CTRLA_RESOLUTION_Pos 5
| (TCC_CTRLA) Enhanced Resolution
#define | TCC_CTRLA_RESOLUTION_Msk (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos)
#define | TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
#define | TCC_CTRLA_RESOLUTION_NONE_Val _U_(0x0)
| (TCC_CTRLA) Dithering is disabled
#define | TCC_CTRLA_RESOLUTION_DITH4_Val _U_(0x1)
| (TCC_CTRLA) Dithering is done every 16 PWM frames
#define | TCC_CTRLA_RESOLUTION_DITH5_Val _U_(0x2)
| (TCC_CTRLA) Dithering is done every 32 PWM frames
#define | TCC_CTRLA_RESOLUTION_DITH6_Val _U_(0x3)
| (TCC_CTRLA) Dithering is done every 64 PWM frames
#define | TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos)
#define | TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos)
#define | TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos)
#define | TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
#define | TCC_CTRLA_PRESCALER_Pos 8
| (TCC_CTRLA) Prescaler
#define | TCC_CTRLA_PRESCALER_Msk (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
#define | TCC_CTRLA_PRESCALER_DIV1_Val _U_(0x0)
| (TCC_CTRLA) No division
#define | TCC_CTRLA_PRESCALER_DIV2_Val _U_(0x1)
| (TCC_CTRLA) Divide by 2
#define | TCC_CTRLA_PRESCALER_DIV4_Val _U_(0x2)
| (TCC_CTRLA) Divide by 4
#define | TCC_CTRLA_PRESCALER_DIV8_Val _U_(0x3)
| (TCC_CTRLA) Divide by 8
#define | TCC_CTRLA_PRESCALER_DIV16_Val _U_(0x4)
| (TCC_CTRLA) Divide by 16
#define | TCC_CTRLA_PRESCALER_DIV64_Val _U_(0x5)
| (TCC_CTRLA) Divide by 64
#define | TCC_CTRLA_PRESCALER_DIV256_Val _U_(0x6)
| (TCC_CTRLA) Divide by 256
#define | TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7)
| (TCC_CTRLA) Divide by 1024
#define | TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos)
#define | TCC_CTRLA_RUNSTDBY_Pos 11
| (TCC_CTRLA) Run in Standby
#define | TCC_CTRLA_RUNSTDBY (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos)
#define | TCC_CTRLA_PRESCSYNC_Pos 12
| (TCC_CTRLA) Prescaler and Counter Synchronization Selection
#define | TCC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos)
#define | TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
#define | TCC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0)
| (TCC_CTRLA) Reload or reset counter on next GCLK
#define | TCC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1)
| (TCC_CTRLA) Reload or reset counter on next prescaler clock
#define | TCC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2)
| (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter
#define | TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos)
#define | TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos)
#define | TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos)
#define | TCC_CTRLA_ALOCK_Pos 14
| (TCC_CTRLA) Auto Lock
#define | TCC_CTRLA_ALOCK (_U_(0x1) << TCC_CTRLA_ALOCK_Pos)
#define | TCC_CTRLA_MSYNC_Pos 15
| (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance)
#define | TCC_CTRLA_MSYNC (_U_(0x1) << TCC_CTRLA_MSYNC_Pos)
#define | TCC_CTRLA_DMAOS_Pos 23
| (TCC_CTRLA) DMA One-shot Trigger Mode
#define | TCC_CTRLA_DMAOS (_U_(0x1) << TCC_CTRLA_DMAOS_Pos)
#define | TCC_CTRLA_CPTEN0_Pos 24
| (TCC_CTRLA) Capture Channel 0 Enable
#define | TCC_CTRLA_CPTEN0 (_U_(1) << TCC_CTRLA_CPTEN0_Pos)
#define | TCC_CTRLA_CPTEN1_Pos 25
| (TCC_CTRLA) Capture Channel 1 Enable
#define | TCC_CTRLA_CPTEN1 (_U_(1) << TCC_CTRLA_CPTEN1_Pos)
#define | TCC_CTRLA_CPTEN2_Pos 26
| (TCC_CTRLA) Capture Channel 2 Enable
#define | TCC_CTRLA_CPTEN2 (_U_(1) << TCC_CTRLA_CPTEN2_Pos)
#define | TCC_CTRLA_CPTEN3_Pos 27
| (TCC_CTRLA) Capture Channel 3 Enable
#define | TCC_CTRLA_CPTEN3 (_U_(1) << TCC_CTRLA_CPTEN3_Pos)
#define | TCC_CTRLA_CPTEN4_Pos 28
| (TCC_CTRLA) Capture Channel 4 Enable
#define | TCC_CTRLA_CPTEN4 (_U_(1) << TCC_CTRLA_CPTEN4_Pos)
#define | TCC_CTRLA_CPTEN5_Pos 29
| (TCC_CTRLA) Capture Channel 5 Enable
#define | TCC_CTRLA_CPTEN5 (_U_(1) << TCC_CTRLA_CPTEN5_Pos)
#define | TCC_CTRLA_CPTEN_Pos 24
| (TCC_CTRLA) Capture Channel x Enable
#define | TCC_CTRLA_CPTEN_Msk (_U_(0x3F) << TCC_CTRLA_CPTEN_Pos)
#define | TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
#define | TCC_CTRLA_MASK _U_(0x3F80FF63)
| (TCC_CTRLA) MASK Register
#define | TCC_CTRLBCLR_OFFSET 0x04
| (TCC_CTRLBCLR offset) Control B Clear
#define | TCC_CTRLBCLR_RESETVALUE _U_(0x00)
| (TCC_CTRLBCLR reset_value) Control B Clear
#define | TCC_CTRLBCLR_DIR_Pos 0
| (TCC_CTRLBCLR) Counter Direction
#define | TCC_CTRLBCLR_DIR (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos)
#define | TCC_CTRLBCLR_LUPD_Pos 1
| (TCC_CTRLBCLR) Lock Update
#define | TCC_CTRLBCLR_LUPD (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos)
#define | TCC_CTRLBCLR_ONESHOT_Pos 2
| (TCC_CTRLBCLR) One-Shot
#define | TCC_CTRLBCLR_ONESHOT (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos)
#define | TCC_CTRLBCLR_IDXCMD_Pos 3
| (TCC_CTRLBCLR) Ramp Index Command
#define | TCC_CTRLBCLR_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos)
#define | TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
#define | TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0)
| (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B
#define | TCC_CTRLBCLR_IDXCMD_SET_Val _U_(0x1)
| (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle
#define | TCC_CTRLBCLR_IDXCMD_CLEAR_Val _U_(0x2)
| (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle
#define | TCC_CTRLBCLR_IDXCMD_HOLD_Val _U_(0x3)
| (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle
#define | TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos)
#define | TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos)
#define | TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos)
#define | TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
#define | TCC_CTRLBCLR_CMD_Pos 5
| (TCC_CTRLBCLR) TCC Command
#define | TCC_CTRLBCLR_CMD_Msk (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos)
#define | TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
#define | TCC_CTRLBCLR_CMD_NONE_Val _U_(0x0)
| (TCC_CTRLBCLR) No action
#define | TCC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1)
| (TCC_CTRLBCLR) Clear start, restart or retrigger
#define | TCC_CTRLBCLR_CMD_STOP_Val _U_(0x2)
| (TCC_CTRLBCLR) Force stop
#define | TCC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3)
| (TCC_CTRLBCLR) Force update or double buffered registers
#define | TCC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4)
| (TCC_CTRLBCLR) Force COUNT read synchronization
#define | TCC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5)
| (TCC_CTRLBCLR) One-shot DMA trigger
#define | TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos)
#define | TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos)
#define | TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos)
#define | TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos)
#define | TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos)
#define | TCC_CTRLBCLR_CMD_DMAOS (TCC_CTRLBCLR_CMD_DMAOS_Val << TCC_CTRLBCLR_CMD_Pos)
#define | TCC_CTRLBCLR_MASK _U_(0xFF)
| (TCC_CTRLBCLR) MASK Register
#define | TCC_CTRLBSET_OFFSET 0x05
| (TCC_CTRLBSET offset) Control B Set
#define | TCC_CTRLBSET_RESETVALUE _U_(0x00)
| (TCC_CTRLBSET reset_value) Control B Set
#define | TCC_CTRLBSET_DIR_Pos 0
| (TCC_CTRLBSET) Counter Direction
#define | TCC_CTRLBSET_DIR (_U_(0x1) << TCC_CTRLBSET_DIR_Pos)
#define | TCC_CTRLBSET_LUPD_Pos 1
| (TCC_CTRLBSET) Lock Update
#define | TCC_CTRLBSET_LUPD (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos)
#define | TCC_CTRLBSET_ONESHOT_Pos 2
| (TCC_CTRLBSET) One-Shot
#define | TCC_CTRLBSET_ONESHOT (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos)
#define | TCC_CTRLBSET_IDXCMD_Pos 3
| (TCC_CTRLBSET) Ramp Index Command
#define | TCC_CTRLBSET_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos)
#define | TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
#define | TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0)
| (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B
#define | TCC_CTRLBSET_IDXCMD_SET_Val _U_(0x1)
| (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle
#define | TCC_CTRLBSET_IDXCMD_CLEAR_Val _U_(0x2)
| (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle
#define | TCC_CTRLBSET_IDXCMD_HOLD_Val _U_(0x3)
| (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle
#define | TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos)
#define | TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos)
#define | TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos)
#define | TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
#define | TCC_CTRLBSET_CMD_Pos 5
| (TCC_CTRLBSET) TCC Command
#define | TCC_CTRLBSET_CMD_Msk (_U_(0x7) << TCC_CTRLBSET_CMD_Pos)
#define | TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
#define | TCC_CTRLBSET_CMD_NONE_Val _U_(0x0)
| (TCC_CTRLBSET) No action
#define | TCC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1)
| (TCC_CTRLBSET) Clear start, restart or retrigger
#define | TCC_CTRLBSET_CMD_STOP_Val _U_(0x2)
| (TCC_CTRLBSET) Force stop
#define | TCC_CTRLBSET_CMD_UPDATE_Val _U_(0x3)
| (TCC_CTRLBSET) Force update or double buffered registers
#define | TCC_CTRLBSET_CMD_READSYNC_Val _U_(0x4)
| (TCC_CTRLBSET) Force COUNT read synchronization
#define | TCC_CTRLBSET_CMD_DMAOS_Val _U_(0x5)
| (TCC_CTRLBSET) One-shot DMA trigger
#define | TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos)
#define | TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos)
#define | TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos)
#define | TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos)
#define | TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos)
#define | TCC_CTRLBSET_CMD_DMAOS (TCC_CTRLBSET_CMD_DMAOS_Val << TCC_CTRLBSET_CMD_Pos)
#define | TCC_CTRLBSET_MASK _U_(0xFF)
| (TCC_CTRLBSET) MASK Register
#define | TCC_SYNCBUSY_OFFSET 0x08
| (TCC_SYNCBUSY offset) Synchronization Busy
#define | TCC_SYNCBUSY_RESETVALUE _U_(0x00000000)
| (TCC_SYNCBUSY reset_value) Synchronization Busy
#define | TCC_SYNCBUSY_SWRST_Pos 0
| (TCC_SYNCBUSY) Swrst Busy
#define | TCC_SYNCBUSY_SWRST (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos)
#define | TCC_SYNCBUSY_ENABLE_Pos 1
| (TCC_SYNCBUSY) Enable Busy
#define | TCC_SYNCBUSY_ENABLE (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos)
#define | TCC_SYNCBUSY_CTRLB_Pos 2
| (TCC_SYNCBUSY) Ctrlb Busy
#define | TCC_SYNCBUSY_CTRLB (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos)
#define | TCC_SYNCBUSY_STATUS_Pos 3
| (TCC_SYNCBUSY) Status Busy
#define | TCC_SYNCBUSY_STATUS (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos)
#define | TCC_SYNCBUSY_COUNT_Pos 4
| (TCC_SYNCBUSY) Count Busy
#define | TCC_SYNCBUSY_COUNT (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos)
#define | TCC_SYNCBUSY_PATT_Pos 5
| (TCC_SYNCBUSY) Pattern Busy
#define | TCC_SYNCBUSY_PATT (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos)
#define | TCC_SYNCBUSY_WAVE_Pos 6
| (TCC_SYNCBUSY) Wave Busy
#define | TCC_SYNCBUSY_WAVE (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos)
#define | TCC_SYNCBUSY_PER_Pos 7
| (TCC_SYNCBUSY) Period Busy
#define | TCC_SYNCBUSY_PER (_U_(0x1) << TCC_SYNCBUSY_PER_Pos)
#define | TCC_SYNCBUSY_CC0_Pos 8
| (TCC_SYNCBUSY) Compare Channel 0 Busy
#define | TCC_SYNCBUSY_CC0 (_U_(1) << TCC_SYNCBUSY_CC0_Pos)
#define | TCC_SYNCBUSY_CC1_Pos 9
| (TCC_SYNCBUSY) Compare Channel 1 Busy
#define | TCC_SYNCBUSY_CC1 (_U_(1) << TCC_SYNCBUSY_CC1_Pos)
#define | TCC_SYNCBUSY_CC2_Pos 10
| (TCC_SYNCBUSY) Compare Channel 2 Busy
#define | TCC_SYNCBUSY_CC2 (_U_(1) << TCC_SYNCBUSY_CC2_Pos)
#define | TCC_SYNCBUSY_CC3_Pos 11
| (TCC_SYNCBUSY) Compare Channel 3 Busy
#define | TCC_SYNCBUSY_CC3 (_U_(1) << TCC_SYNCBUSY_CC3_Pos)
#define | TCC_SYNCBUSY_CC4_Pos 12
| (TCC_SYNCBUSY) Compare Channel 4 Busy
#define | TCC_SYNCBUSY_CC4 (_U_(1) << TCC_SYNCBUSY_CC4_Pos)
#define | TCC_SYNCBUSY_CC5_Pos 13
| (TCC_SYNCBUSY) Compare Channel 5 Busy
#define | TCC_SYNCBUSY_CC5 (_U_(1) << TCC_SYNCBUSY_CC5_Pos)
#define | TCC_SYNCBUSY_CC_Pos 8
| (TCC_SYNCBUSY) Compare Channel x Busy
#define | TCC_SYNCBUSY_CC_Msk (_U_(0x3F) << TCC_SYNCBUSY_CC_Pos)
#define | TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
#define | TCC_SYNCBUSY_MASK _U_(0x00003FFF)
| (TCC_SYNCBUSY) MASK Register
#define | TCC_FCTRLA_OFFSET 0x0C
| (TCC_FCTRLA offset) Recoverable Fault A Configuration
#define | TCC_FCTRLA_RESETVALUE _U_(0x00000000)
| (TCC_FCTRLA reset_value) Recoverable Fault A Configuration
#define | TCC_FCTRLA_SRC_Pos 0
| (TCC_FCTRLA) Fault A Source
#define | TCC_FCTRLA_SRC_Msk (_U_(0x3) << TCC_FCTRLA_SRC_Pos)
#define | TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
#define | TCC_FCTRLA_SRC_DISABLE_Val _U_(0x0)
| (TCC_FCTRLA) Fault input disabled
#define | TCC_FCTRLA_SRC_ENABLE_Val _U_(0x1)
| (TCC_FCTRLA) MCEx (x=0,1) event input
#define | TCC_FCTRLA_SRC_INVERT_Val _U_(0x2)
| (TCC_FCTRLA) Inverted MCEx (x=0,1) event input
#define | TCC_FCTRLA_SRC_ALTFAULT_Val _U_(0x3)
| (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period
#define | TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos)
#define | TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos)
#define | TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos)
#define | TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos)
#define | TCC_FCTRLA_KEEP_Pos 3
| (TCC_FCTRLA) Fault A Keeper
#define | TCC_FCTRLA_KEEP (_U_(0x1) << TCC_FCTRLA_KEEP_Pos)
#define | TCC_FCTRLA_QUAL_Pos 4
| (TCC_FCTRLA) Fault A Qualification
#define | TCC_FCTRLA_QUAL (_U_(0x1) << TCC_FCTRLA_QUAL_Pos)
#define | TCC_FCTRLA_BLANK_Pos 5
| (TCC_FCTRLA) Fault A Blanking Mode
#define | TCC_FCTRLA_BLANK_Msk (_U_(0x3) << TCC_FCTRLA_BLANK_Pos)
#define | TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
#define | TCC_FCTRLA_BLANK_START_Val _U_(0x0)
| (TCC_FCTRLA) Blanking applied from start of the ramp
#define | TCC_FCTRLA_BLANK_RISE_Val _U_(0x1)
| (TCC_FCTRLA) Blanking applied from rising edge of the output waveform
#define | TCC_FCTRLA_BLANK_FALL_Val _U_(0x2)
| (TCC_FCTRLA) Blanking applied from falling edge of the output waveform
#define | TCC_FCTRLA_BLANK_BOTH_Val _U_(0x3)
| (TCC_FCTRLA) Blanking applied from each toggle of the output waveform
#define | TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos)
#define | TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
#define | TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
#define | TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
#define | TCC_FCTRLA_RESTART_Pos 7
| (TCC_FCTRLA) Fault A Restart
#define | TCC_FCTRLA_RESTART (_U_(0x1) << TCC_FCTRLA_RESTART_Pos)
#define | TCC_FCTRLA_HALT_Pos 8
| (TCC_FCTRLA) Fault A Halt Mode
#define | TCC_FCTRLA_HALT_Msk (_U_(0x3) << TCC_FCTRLA_HALT_Pos)
#define | TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
#define | TCC_FCTRLA_HALT_DISABLE_Val _U_(0x0)
| (TCC_FCTRLA) Halt action disabled
#define | TCC_FCTRLA_HALT_HW_Val _U_(0x1)
| (TCC_FCTRLA) Hardware halt action
#define | TCC_FCTRLA_HALT_SW_Val _U_(0x2)
| (TCC_FCTRLA) Software halt action
#define | TCC_FCTRLA_HALT_NR_Val _U_(0x3)
| (TCC_FCTRLA) Non-recoverable fault
#define | TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos)
#define | TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos)
#define | TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos)
#define | TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
#define | TCC_FCTRLA_CHSEL_Pos 10
| (TCC_FCTRLA) Fault A Capture Channel
#define | TCC_FCTRLA_CHSEL_Msk (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos)
#define | TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
#define | TCC_FCTRLA_CHSEL_CC0_Val _U_(0x0)
| (TCC_FCTRLA) Capture value stored in channel 0
#define | TCC_FCTRLA_CHSEL_CC1_Val _U_(0x1)
| (TCC_FCTRLA) Capture value stored in channel 1
#define | TCC_FCTRLA_CHSEL_CC2_Val _U_(0x2)
| (TCC_FCTRLA) Capture value stored in channel 2
#define | TCC_FCTRLA_CHSEL_CC3_Val _U_(0x3)
| (TCC_FCTRLA) Capture value stored in channel 3
#define | TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos)
#define | TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos)
#define | TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos)
#define | TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
#define | TCC_FCTRLA_CAPTURE_Pos 12
| (TCC_FCTRLA) Fault A Capture Action
#define | TCC_FCTRLA_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
#define | TCC_FCTRLA_CAPTURE_DISABLE_Val _U_(0x0)
| (TCC_FCTRLA) No capture
#define | TCC_FCTRLA_CAPTURE_CAPT_Val _U_(0x1)
| (TCC_FCTRLA) Capture on fault
#define | TCC_FCTRLA_CAPTURE_CAPTMIN_Val _U_(0x2)
| (TCC_FCTRLA) Minimum capture
#define | TCC_FCTRLA_CAPTURE_CAPTMAX_Val _U_(0x3)
| (TCC_FCTRLA) Maximum capture
#define | TCC_FCTRLA_CAPTURE_LOCMIN_Val _U_(0x4)
| (TCC_FCTRLA) Minimum local detection
#define | TCC_FCTRLA_CAPTURE_LOCMAX_Val _U_(0x5)
| (TCC_FCTRLA) Maximum local detection
#define | TCC_FCTRLA_CAPTURE_DERIV0_Val _U_(0x6)
| (TCC_FCTRLA) Minimum and maximum local detection
#define | TCC_FCTRLA_CAPTURE_CAPTMARK_Val _U_(0x7)
| (TCC_FCTRLA) Capture with ramp index as MSB value
#define | TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
#define | TCC_FCTRLA_BLANKPRESC_Pos 15
| (TCC_FCTRLA) Fault A Blanking Prescaler
#define | TCC_FCTRLA_BLANKPRESC (_U_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos)
#define | TCC_FCTRLA_BLANKVAL_Pos 16
| (TCC_FCTRLA) Fault A Blanking Time
#define | TCC_FCTRLA_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos)
#define | TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
#define | TCC_FCTRLA_FILTERVAL_Pos 24
| (TCC_FCTRLA) Fault A Filter Value
#define | TCC_FCTRLA_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos)
#define | TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
#define | TCC_FCTRLA_MASK _U_(0x0FFFFFFB)
| (TCC_FCTRLA) MASK Register
#define | TCC_FCTRLB_OFFSET 0x10
| (TCC_FCTRLB offset) Recoverable Fault B Configuration
#define | TCC_FCTRLB_RESETVALUE _U_(0x00000000)
| (TCC_FCTRLB reset_value) Recoverable Fault B Configuration
#define | TCC_FCTRLB_SRC_Pos 0
| (TCC_FCTRLB) Fault B Source
#define | TCC_FCTRLB_SRC_Msk (_U_(0x3) << TCC_FCTRLB_SRC_Pos)
#define | TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
#define | TCC_FCTRLB_SRC_DISABLE_Val _U_(0x0)
| (TCC_FCTRLB) Fault input disabled
#define | TCC_FCTRLB_SRC_ENABLE_Val _U_(0x1)
| (TCC_FCTRLB) MCEx (x=0,1) event input
#define | TCC_FCTRLB_SRC_INVERT_Val _U_(0x2)
| (TCC_FCTRLB) Inverted MCEx (x=0,1) event input
#define | TCC_FCTRLB_SRC_ALTFAULT_Val _U_(0x3)
| (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period
#define | TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos)
#define | TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos)
#define | TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos)
#define | TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos)
#define | TCC_FCTRLB_KEEP_Pos 3
| (TCC_FCTRLB) Fault B Keeper
#define | TCC_FCTRLB_KEEP (_U_(0x1) << TCC_FCTRLB_KEEP_Pos)
#define | TCC_FCTRLB_QUAL_Pos 4
| (TCC_FCTRLB) Fault B Qualification
#define | TCC_FCTRLB_QUAL (_U_(0x1) << TCC_FCTRLB_QUAL_Pos)
#define | TCC_FCTRLB_BLANK_Pos 5
| (TCC_FCTRLB) Fault B Blanking Mode
#define | TCC_FCTRLB_BLANK_Msk (_U_(0x3) << TCC_FCTRLB_BLANK_Pos)
#define | TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
#define | TCC_FCTRLB_BLANK_START_Val _U_(0x0)
| (TCC_FCTRLB) Blanking applied from start of the ramp
#define | TCC_FCTRLB_BLANK_RISE_Val _U_(0x1)
| (TCC_FCTRLB) Blanking applied from rising edge of the output waveform
#define | TCC_FCTRLB_BLANK_FALL_Val _U_(0x2)
| (TCC_FCTRLB) Blanking applied from falling edge of the output waveform
#define | TCC_FCTRLB_BLANK_BOTH_Val _U_(0x3)
| (TCC_FCTRLB) Blanking applied from each toggle of the output waveform
#define | TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos)
#define | TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
#define | TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
#define | TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
#define | TCC_FCTRLB_RESTART_Pos 7
| (TCC_FCTRLB) Fault B Restart
#define | TCC_FCTRLB_RESTART (_U_(0x1) << TCC_FCTRLB_RESTART_Pos)
#define | TCC_FCTRLB_HALT_Pos 8
| (TCC_FCTRLB) Fault B Halt Mode
#define | TCC_FCTRLB_HALT_Msk (_U_(0x3) << TCC_FCTRLB_HALT_Pos)
#define | TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
#define | TCC_FCTRLB_HALT_DISABLE_Val _U_(0x0)
| (TCC_FCTRLB) Halt action disabled
#define | TCC_FCTRLB_HALT_HW_Val _U_(0x1)
| (TCC_FCTRLB) Hardware halt action
#define | TCC_FCTRLB_HALT_SW_Val _U_(0x2)
| (TCC_FCTRLB) Software halt action
#define | TCC_FCTRLB_HALT_NR_Val _U_(0x3)
| (TCC_FCTRLB) Non-recoverable fault
#define | TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos)
#define | TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos)
#define | TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos)
#define | TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
#define | TCC_FCTRLB_CHSEL_Pos 10
| (TCC_FCTRLB) Fault B Capture Channel
#define | TCC_FCTRLB_CHSEL_Msk (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos)
#define | TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
#define | TCC_FCTRLB_CHSEL_CC0_Val _U_(0x0)
| (TCC_FCTRLB) Capture value stored in channel 0
#define | TCC_FCTRLB_CHSEL_CC1_Val _U_(0x1)
| (TCC_FCTRLB) Capture value stored in channel 1
#define | TCC_FCTRLB_CHSEL_CC2_Val _U_(0x2)
| (TCC_FCTRLB) Capture value stored in channel 2
#define | TCC_FCTRLB_CHSEL_CC3_Val _U_(0x3)
| (TCC_FCTRLB) Capture value stored in channel 3
#define | TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos)
#define | TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos)
#define | TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos)
#define | TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
#define | TCC_FCTRLB_CAPTURE_Pos 12
| (TCC_FCTRLB) Fault B Capture Action
#define | TCC_FCTRLB_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
#define | TCC_FCTRLB_CAPTURE_DISABLE_Val _U_(0x0)
| (TCC_FCTRLB) No capture
#define | TCC_FCTRLB_CAPTURE_CAPT_Val _U_(0x1)
| (TCC_FCTRLB) Capture on fault
#define | TCC_FCTRLB_CAPTURE_CAPTMIN_Val _U_(0x2)
| (TCC_FCTRLB) Minimum capture
#define | TCC_FCTRLB_CAPTURE_CAPTMAX_Val _U_(0x3)
| (TCC_FCTRLB) Maximum capture
#define | TCC_FCTRLB_CAPTURE_LOCMIN_Val _U_(0x4)
| (TCC_FCTRLB) Minimum local detection
#define | TCC_FCTRLB_CAPTURE_LOCMAX_Val _U_(0x5)
| (TCC_FCTRLB) Maximum local detection
#define | TCC_FCTRLB_CAPTURE_DERIV0_Val _U_(0x6)
| (TCC_FCTRLB) Minimum and maximum local detection
#define | TCC_FCTRLB_CAPTURE_CAPTMARK_Val _U_(0x7)
| (TCC_FCTRLB) Capture with ramp index as MSB value
#define | TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
#define | TCC_FCTRLB_BLANKPRESC_Pos 15
| (TCC_FCTRLB) Fault B Blanking Prescaler
#define | TCC_FCTRLB_BLANKPRESC (_U_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos)
#define | TCC_FCTRLB_BLANKVAL_Pos 16
| (TCC_FCTRLB) Fault B Blanking Time
#define | TCC_FCTRLB_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos)
#define | TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
#define | TCC_FCTRLB_FILTERVAL_Pos 24
| (TCC_FCTRLB) Fault B Filter Value
#define | TCC_FCTRLB_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos)
#define | TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
#define | TCC_FCTRLB_MASK _U_(0x0FFFFFFB)
| (TCC_FCTRLB) MASK Register
#define | TCC_WEXCTRL_OFFSET 0x14
| (TCC_WEXCTRL offset) Waveform Extension Configuration
#define | TCC_WEXCTRL_RESETVALUE _U_(0x00000000)
| (TCC_WEXCTRL reset_value) Waveform Extension Configuration
#define | TCC_WEXCTRL_OTMX_Pos 0
| (TCC_WEXCTRL) Output Matrix
#define | TCC_WEXCTRL_OTMX_Msk (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos)
#define | TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
#define | TCC_WEXCTRL_DTIEN0_Pos 8
| (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable
#define | TCC_WEXCTRL_DTIEN0 (_U_(1) << TCC_WEXCTRL_DTIEN0_Pos)
#define | TCC_WEXCTRL_DTIEN1_Pos 9
| (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable
#define | TCC_WEXCTRL_DTIEN1 (_U_(1) << TCC_WEXCTRL_DTIEN1_Pos)
#define | TCC_WEXCTRL_DTIEN2_Pos 10
| (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable
#define | TCC_WEXCTRL_DTIEN2 (_U_(1) << TCC_WEXCTRL_DTIEN2_Pos)
#define | TCC_WEXCTRL_DTIEN3_Pos 11
| (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable
#define | TCC_WEXCTRL_DTIEN3 (_U_(1) << TCC_WEXCTRL_DTIEN3_Pos)
#define | TCC_WEXCTRL_DTIEN_Pos 8
| (TCC_WEXCTRL) Dead-time Insertion Generator x Enable
#define | TCC_WEXCTRL_DTIEN_Msk (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos)
#define | TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
#define | TCC_WEXCTRL_DTLS_Pos 16
| (TCC_WEXCTRL) Dead-time Low Side Outputs Value
#define | TCC_WEXCTRL_DTLS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos)
#define | TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
#define | TCC_WEXCTRL_DTHS_Pos 24
| (TCC_WEXCTRL) Dead-time High Side Outputs Value
#define | TCC_WEXCTRL_DTHS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos)
#define | TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
#define | TCC_WEXCTRL_MASK _U_(0xFFFF0F03)
| (TCC_WEXCTRL) MASK Register
#define | TCC_DRVCTRL_OFFSET 0x18
| (TCC_DRVCTRL offset) Driver Control
#define | TCC_DRVCTRL_RESETVALUE _U_(0x00000000)
| (TCC_DRVCTRL reset_value) Driver Control
#define | TCC_DRVCTRL_NRE0_Pos 0
| (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable
#define | TCC_DRVCTRL_NRE0 (_U_(1) << TCC_DRVCTRL_NRE0_Pos)
#define | TCC_DRVCTRL_NRE1_Pos 1
| (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable
#define | TCC_DRVCTRL_NRE1 (_U_(1) << TCC_DRVCTRL_NRE1_Pos)
#define | TCC_DRVCTRL_NRE2_Pos 2
| (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable
#define | TCC_DRVCTRL_NRE2 (_U_(1) << TCC_DRVCTRL_NRE2_Pos)
#define | TCC_DRVCTRL_NRE3_Pos 3
| (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable
#define | TCC_DRVCTRL_NRE3 (_U_(1) << TCC_DRVCTRL_NRE3_Pos)
#define | TCC_DRVCTRL_NRE4_Pos 4
| (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable
#define | TCC_DRVCTRL_NRE4 (_U_(1) << TCC_DRVCTRL_NRE4_Pos)
#define | TCC_DRVCTRL_NRE5_Pos 5
| (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable
#define | TCC_DRVCTRL_NRE5 (_U_(1) << TCC_DRVCTRL_NRE5_Pos)
#define | TCC_DRVCTRL_NRE6_Pos 6
| (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable
#define | TCC_DRVCTRL_NRE6 (_U_(1) << TCC_DRVCTRL_NRE6_Pos)
#define | TCC_DRVCTRL_NRE7_Pos 7
| (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable
#define | TCC_DRVCTRL_NRE7 (_U_(1) << TCC_DRVCTRL_NRE7_Pos)
#define | TCC_DRVCTRL_NRE_Pos 0
| (TCC_DRVCTRL) Non-Recoverable State x Output Enable
#define | TCC_DRVCTRL_NRE_Msk (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos)
#define | TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
#define | TCC_DRVCTRL_NRV0_Pos 8
| (TCC_DRVCTRL) Non-Recoverable State 0 Output Value
#define | TCC_DRVCTRL_NRV0 (_U_(1) << TCC_DRVCTRL_NRV0_Pos)
#define | TCC_DRVCTRL_NRV1_Pos 9
| (TCC_DRVCTRL) Non-Recoverable State 1 Output Value
#define | TCC_DRVCTRL_NRV1 (_U_(1) << TCC_DRVCTRL_NRV1_Pos)
#define | TCC_DRVCTRL_NRV2_Pos 10
| (TCC_DRVCTRL) Non-Recoverable State 2 Output Value
#define | TCC_DRVCTRL_NRV2 (_U_(1) << TCC_DRVCTRL_NRV2_Pos)
#define | TCC_DRVCTRL_NRV3_Pos 11
| (TCC_DRVCTRL) Non-Recoverable State 3 Output Value
#define | TCC_DRVCTRL_NRV3 (_U_(1) << TCC_DRVCTRL_NRV3_Pos)
#define | TCC_DRVCTRL_NRV4_Pos 12
| (TCC_DRVCTRL) Non-Recoverable State 4 Output Value
#define | TCC_DRVCTRL_NRV4 (_U_(1) << TCC_DRVCTRL_NRV4_Pos)
#define | TCC_DRVCTRL_NRV5_Pos 13
| (TCC_DRVCTRL) Non-Recoverable State 5 Output Value
#define | TCC_DRVCTRL_NRV5 (_U_(1) << TCC_DRVCTRL_NRV5_Pos)
#define | TCC_DRVCTRL_NRV6_Pos 14
| (TCC_DRVCTRL) Non-Recoverable State 6 Output Value
#define | TCC_DRVCTRL_NRV6 (_U_(1) << TCC_DRVCTRL_NRV6_Pos)
#define | TCC_DRVCTRL_NRV7_Pos 15
| (TCC_DRVCTRL) Non-Recoverable State 7 Output Value
#define | TCC_DRVCTRL_NRV7 (_U_(1) << TCC_DRVCTRL_NRV7_Pos)
#define | TCC_DRVCTRL_NRV_Pos 8
| (TCC_DRVCTRL) Non-Recoverable State x Output Value
#define | TCC_DRVCTRL_NRV_Msk (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos)
#define | TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
#define | TCC_DRVCTRL_INVEN0_Pos 16
| (TCC_DRVCTRL) Output Waveform 0 Inversion
#define | TCC_DRVCTRL_INVEN0 (_U_(1) << TCC_DRVCTRL_INVEN0_Pos)
#define | TCC_DRVCTRL_INVEN1_Pos 17
| (TCC_DRVCTRL) Output Waveform 1 Inversion
#define | TCC_DRVCTRL_INVEN1 (_U_(1) << TCC_DRVCTRL_INVEN1_Pos)
#define | TCC_DRVCTRL_INVEN2_Pos 18
| (TCC_DRVCTRL) Output Waveform 2 Inversion
#define | TCC_DRVCTRL_INVEN2 (_U_(1) << TCC_DRVCTRL_INVEN2_Pos)
#define | TCC_DRVCTRL_INVEN3_Pos 19
| (TCC_DRVCTRL) Output Waveform 3 Inversion
#define | TCC_DRVCTRL_INVEN3 (_U_(1) << TCC_DRVCTRL_INVEN3_Pos)
#define | TCC_DRVCTRL_INVEN4_Pos 20
| (TCC_DRVCTRL) Output Waveform 4 Inversion
#define | TCC_DRVCTRL_INVEN4 (_U_(1) << TCC_DRVCTRL_INVEN4_Pos)
#define | TCC_DRVCTRL_INVEN5_Pos 21
| (TCC_DRVCTRL) Output Waveform 5 Inversion
#define | TCC_DRVCTRL_INVEN5 (_U_(1) << TCC_DRVCTRL_INVEN5_Pos)
#define | TCC_DRVCTRL_INVEN6_Pos 22
| (TCC_DRVCTRL) Output Waveform 6 Inversion
#define | TCC_DRVCTRL_INVEN6 (_U_(1) << TCC_DRVCTRL_INVEN6_Pos)
#define | TCC_DRVCTRL_INVEN7_Pos 23
| (TCC_DRVCTRL) Output Waveform 7 Inversion
#define | TCC_DRVCTRL_INVEN7 (_U_(1) << TCC_DRVCTRL_INVEN7_Pos)
#define | TCC_DRVCTRL_INVEN_Pos 16
| (TCC_DRVCTRL) Output Waveform x Inversion
#define | TCC_DRVCTRL_INVEN_Msk (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos)
#define | TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
#define | TCC_DRVCTRL_FILTERVAL0_Pos 24
| (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value
#define | TCC_DRVCTRL_FILTERVAL0_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos)
#define | TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
#define | TCC_DRVCTRL_FILTERVAL1_Pos 28
| (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value
#define | TCC_DRVCTRL_FILTERVAL1_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos)
#define | TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
#define | TCC_DRVCTRL_MASK _U_(0xFFFFFFFF)
| (TCC_DRVCTRL) MASK Register
#define | TCC_DBGCTRL_OFFSET 0x1E
| (TCC_DBGCTRL offset) Debug Control
#define | TCC_DBGCTRL_RESETVALUE _U_(0x00)
| (TCC_DBGCTRL reset_value) Debug Control
#define | TCC_DBGCTRL_DBGRUN_Pos 0
| (TCC_DBGCTRL) Debug Running Mode
#define | TCC_DBGCTRL_DBGRUN (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos)
#define | TCC_DBGCTRL_FDDBD_Pos 2
| (TCC_DBGCTRL) Fault Detection on Debug Break Detection
#define | TCC_DBGCTRL_FDDBD (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos)
#define | TCC_DBGCTRL_MASK _U_(0x05)
| (TCC_DBGCTRL) MASK Register
#define | TCC_EVCTRL_OFFSET 0x20
| (TCC_EVCTRL offset) Event Control
#define | TCC_EVCTRL_RESETVALUE _U_(0x00000000)
| (TCC_EVCTRL reset_value) Event Control
#define | TCC_EVCTRL_EVACT0_Pos 0
| (TCC_EVCTRL) Timer/counter Input Event0 Action
#define | TCC_EVCTRL_EVACT0_Msk (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
#define | TCC_EVCTRL_EVACT0_OFF_Val _U_(0x0)
| (TCC_EVCTRL) Event action disabled
#define | TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1)
| (TCC_EVCTRL) Start, restart or re-trigger counter on event
#define | TCC_EVCTRL_EVACT0_COUNTEV_Val _U_(0x2)
| (TCC_EVCTRL) Count on event
#define | TCC_EVCTRL_EVACT0_START_Val _U_(0x3)
| (TCC_EVCTRL) Start counter on event
#define | TCC_EVCTRL_EVACT0_INC_Val _U_(0x4)
| (TCC_EVCTRL) Increment counter on event
#define | TCC_EVCTRL_EVACT0_COUNT_Val _U_(0x5)
| (TCC_EVCTRL) Count on active state of asynchronous event
#define | TCC_EVCTRL_EVACT0_STAMP_Val _U_(0x6)
| (TCC_EVCTRL) Stamp capture
#define | TCC_EVCTRL_EVACT0_FAULT_Val _U_(0x7)
| (TCC_EVCTRL) Non-recoverable fault
#define | TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
#define | TCC_EVCTRL_EVACT1_Pos 3
| (TCC_EVCTRL) Timer/counter Input Event1 Action
#define | TCC_EVCTRL_EVACT1_Msk (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
#define | TCC_EVCTRL_EVACT1_OFF_Val _U_(0x0)
| (TCC_EVCTRL) Event action disabled
#define | TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1)
| (TCC_EVCTRL) Re-trigger counter on event
#define | TCC_EVCTRL_EVACT1_DIR_Val _U_(0x2)
| (TCC_EVCTRL) Direction control
#define | TCC_EVCTRL_EVACT1_STOP_Val _U_(0x3)
| (TCC_EVCTRL) Stop counter on event
#define | TCC_EVCTRL_EVACT1_DEC_Val _U_(0x4)
| (TCC_EVCTRL) Decrement counter on event
#define | TCC_EVCTRL_EVACT1_PPW_Val _U_(0x5)
| (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register
#define | TCC_EVCTRL_EVACT1_PWP_Val _U_(0x6)
| (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register
#define | TCC_EVCTRL_EVACT1_FAULT_Val _U_(0x7)
| (TCC_EVCTRL) Non-recoverable fault
#define | TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
#define | TCC_EVCTRL_CNTSEL_Pos 6
| (TCC_EVCTRL) Timer/counter Output Event Mode
#define | TCC_EVCTRL_CNTSEL_Msk (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos)
#define | TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
#define | TCC_EVCTRL_CNTSEL_START_Val _U_(0x0)
| (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts
#define | TCC_EVCTRL_CNTSEL_END_Val _U_(0x1)
| (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends
#define | TCC_EVCTRL_CNTSEL_BETWEEN_Val _U_(0x2)
| (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
#define | TCC_EVCTRL_CNTSEL_BOUNDARY_Val _U_(0x3)
| (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
#define | TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos)
#define | TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos)
#define | TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos)
#define | TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos)
#define | TCC_EVCTRL_OVFEO_Pos 8
| (TCC_EVCTRL) Overflow/Underflow Output Event Enable
#define | TCC_EVCTRL_OVFEO (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos)
#define | TCC_EVCTRL_TRGEO_Pos 9
| (TCC_EVCTRL) Retrigger Output Event Enable
#define | TCC_EVCTRL_TRGEO (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos)
#define | TCC_EVCTRL_CNTEO_Pos 10
| (TCC_EVCTRL) Timer/counter Output Event Enable
#define | TCC_EVCTRL_CNTEO (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos)
#define | TCC_EVCTRL_TCINV0_Pos 12
| (TCC_EVCTRL) Inverted Event 0 Input Enable
#define | TCC_EVCTRL_TCINV0 (_U_(1) << TCC_EVCTRL_TCINV0_Pos)
#define | TCC_EVCTRL_TCINV1_Pos 13
| (TCC_EVCTRL) Inverted Event 1 Input Enable
#define | TCC_EVCTRL_TCINV1 (_U_(1) << TCC_EVCTRL_TCINV1_Pos)
#define | TCC_EVCTRL_TCINV_Pos 12
| (TCC_EVCTRL) Inverted Event x Input Enable
#define | TCC_EVCTRL_TCINV_Msk (_U_(0x3) << TCC_EVCTRL_TCINV_Pos)
#define | TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
#define | TCC_EVCTRL_TCEI0_Pos 14
| (TCC_EVCTRL) Timer/counter Event 0 Input Enable
#define | TCC_EVCTRL_TCEI0 (_U_(1) << TCC_EVCTRL_TCEI0_Pos)
#define | TCC_EVCTRL_TCEI1_Pos 15
| (TCC_EVCTRL) Timer/counter Event 1 Input Enable
#define | TCC_EVCTRL_TCEI1 (_U_(1) << TCC_EVCTRL_TCEI1_Pos)
#define | TCC_EVCTRL_TCEI_Pos 14
| (TCC_EVCTRL) Timer/counter Event x Input Enable
#define | TCC_EVCTRL_TCEI_Msk (_U_(0x3) << TCC_EVCTRL_TCEI_Pos)
#define | TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
#define | TCC_EVCTRL_MCEI0_Pos 16
| (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable
#define | TCC_EVCTRL_MCEI0 (_U_(1) << TCC_EVCTRL_MCEI0_Pos)
#define | TCC_EVCTRL_MCEI1_Pos 17
| (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable
#define | TCC_EVCTRL_MCEI1 (_U_(1) << TCC_EVCTRL_MCEI1_Pos)
#define | TCC_EVCTRL_MCEI2_Pos 18
| (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable
#define | TCC_EVCTRL_MCEI2 (_U_(1) << TCC_EVCTRL_MCEI2_Pos)
#define | TCC_EVCTRL_MCEI3_Pos 19
| (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable
#define | TCC_EVCTRL_MCEI3 (_U_(1) << TCC_EVCTRL_MCEI3_Pos)
#define | TCC_EVCTRL_MCEI4_Pos 20
| (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable
#define | TCC_EVCTRL_MCEI4 (_U_(1) << TCC_EVCTRL_MCEI4_Pos)
#define | TCC_EVCTRL_MCEI5_Pos 21
| (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable
#define | TCC_EVCTRL_MCEI5 (_U_(1) << TCC_EVCTRL_MCEI5_Pos)
#define | TCC_EVCTRL_MCEI_Pos 16
| (TCC_EVCTRL) Match or Capture Channel x Event Input Enable
#define | TCC_EVCTRL_MCEI_Msk (_U_(0x3F) << TCC_EVCTRL_MCEI_Pos)
#define | TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
#define | TCC_EVCTRL_MCEO0_Pos 24
| (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable
#define | TCC_EVCTRL_MCEO0 (_U_(1) << TCC_EVCTRL_MCEO0_Pos)
#define | TCC_EVCTRL_MCEO1_Pos 25
| (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable
#define | TCC_EVCTRL_MCEO1 (_U_(1) << TCC_EVCTRL_MCEO1_Pos)
#define | TCC_EVCTRL_MCEO2_Pos 26
| (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable
#define | TCC_EVCTRL_MCEO2 (_U_(1) << TCC_EVCTRL_MCEO2_Pos)
#define | TCC_EVCTRL_MCEO3_Pos 27
| (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable
#define | TCC_EVCTRL_MCEO3 (_U_(1) << TCC_EVCTRL_MCEO3_Pos)
#define | TCC_EVCTRL_MCEO4_Pos 28
| (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable
#define | TCC_EVCTRL_MCEO4 (_U_(1) << TCC_EVCTRL_MCEO4_Pos)
#define | TCC_EVCTRL_MCEO5_Pos 29
| (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable
#define | TCC_EVCTRL_MCEO5 (_U_(1) << TCC_EVCTRL_MCEO5_Pos)
#define | TCC_EVCTRL_MCEO_Pos 24
| (TCC_EVCTRL) Match or Capture Channel x Event Output Enable
#define | TCC_EVCTRL_MCEO_Msk (_U_(0x3F) << TCC_EVCTRL_MCEO_Pos)
#define | TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
#define | TCC_EVCTRL_MASK _U_(0x3F3FF7FF)
| (TCC_EVCTRL) MASK Register
#define | TCC_INTENCLR_OFFSET 0x24
| (TCC_INTENCLR offset) Interrupt Enable Clear
#define | TCC_INTENCLR_RESETVALUE _U_(0x00000000)
| (TCC_INTENCLR reset_value) Interrupt Enable Clear
#define | TCC_INTENCLR_OVF_Pos 0
| (TCC_INTENCLR) Overflow Interrupt Enable
#define | TCC_INTENCLR_OVF (_U_(0x1) << TCC_INTENCLR_OVF_Pos)
#define | TCC_INTENCLR_TRG_Pos 1
| (TCC_INTENCLR) Retrigger Interrupt Enable
#define | TCC_INTENCLR_TRG (_U_(0x1) << TCC_INTENCLR_TRG_Pos)
#define | TCC_INTENCLR_CNT_Pos 2
| (TCC_INTENCLR) Counter Interrupt Enable
#define | TCC_INTENCLR_CNT (_U_(0x1) << TCC_INTENCLR_CNT_Pos)
#define | TCC_INTENCLR_ERR_Pos 3
| (TCC_INTENCLR) Error Interrupt Enable
#define | TCC_INTENCLR_ERR (_U_(0x1) << TCC_INTENCLR_ERR_Pos)
#define | TCC_INTENCLR_UFS_Pos 10
| (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable
#define | TCC_INTENCLR_UFS (_U_(0x1) << TCC_INTENCLR_UFS_Pos)
#define | TCC_INTENCLR_DFS_Pos 11
| (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable
#define | TCC_INTENCLR_DFS (_U_(0x1) << TCC_INTENCLR_DFS_Pos)
#define | TCC_INTENCLR_FAULTA_Pos 12
| (TCC_INTENCLR) Recoverable Fault A Interrupt Enable
#define | TCC_INTENCLR_FAULTA (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos)
#define | TCC_INTENCLR_FAULTB_Pos 13
| (TCC_INTENCLR) Recoverable Fault B Interrupt Enable
#define | TCC_INTENCLR_FAULTB (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos)
#define | TCC_INTENCLR_FAULT0_Pos 14
| (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable
#define | TCC_INTENCLR_FAULT0 (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos)
#define | TCC_INTENCLR_FAULT1_Pos 15
| (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable
#define | TCC_INTENCLR_FAULT1 (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos)
#define | TCC_INTENCLR_MC0_Pos 16
| (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable
#define | TCC_INTENCLR_MC0 (_U_(1) << TCC_INTENCLR_MC0_Pos)
#define | TCC_INTENCLR_MC1_Pos 17
| (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable
#define | TCC_INTENCLR_MC1 (_U_(1) << TCC_INTENCLR_MC1_Pos)
#define | TCC_INTENCLR_MC2_Pos 18
| (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable
#define | TCC_INTENCLR_MC2 (_U_(1) << TCC_INTENCLR_MC2_Pos)
#define | TCC_INTENCLR_MC3_Pos 19
| (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable
#define | TCC_INTENCLR_MC3 (_U_(1) << TCC_INTENCLR_MC3_Pos)
#define | TCC_INTENCLR_MC4_Pos 20
| (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable
#define | TCC_INTENCLR_MC4 (_U_(1) << TCC_INTENCLR_MC4_Pos)
#define | TCC_INTENCLR_MC5_Pos 21
| (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable
#define | TCC_INTENCLR_MC5 (_U_(1) << TCC_INTENCLR_MC5_Pos)
#define | TCC_INTENCLR_MC_Pos 16
| (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable
#define | TCC_INTENCLR_MC_Msk (_U_(0x3F) << TCC_INTENCLR_MC_Pos)
#define | TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
#define | TCC_INTENCLR_MASK _U_(0x003FFC0F)
| (TCC_INTENCLR) MASK Register
#define | TCC_INTENSET_OFFSET 0x28
| (TCC_INTENSET offset) Interrupt Enable Set
#define | TCC_INTENSET_RESETVALUE _U_(0x00000000)
| (TCC_INTENSET reset_value) Interrupt Enable Set
#define | TCC_INTENSET_OVF_Pos 0
| (TCC_INTENSET) Overflow Interrupt Enable
#define | TCC_INTENSET_OVF (_U_(0x1) << TCC_INTENSET_OVF_Pos)
#define | TCC_INTENSET_TRG_Pos 1
| (TCC_INTENSET) Retrigger Interrupt Enable
#define | TCC_INTENSET_TRG (_U_(0x1) << TCC_INTENSET_TRG_Pos)
#define | TCC_INTENSET_CNT_Pos 2
| (TCC_INTENSET) Counter Interrupt Enable
#define | TCC_INTENSET_CNT (_U_(0x1) << TCC_INTENSET_CNT_Pos)
#define | TCC_INTENSET_ERR_Pos 3
| (TCC_INTENSET) Error Interrupt Enable
#define | TCC_INTENSET_ERR (_U_(0x1) << TCC_INTENSET_ERR_Pos)
#define | TCC_INTENSET_UFS_Pos 10
| (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable
#define | TCC_INTENSET_UFS (_U_(0x1) << TCC_INTENSET_UFS_Pos)
#define | TCC_INTENSET_DFS_Pos 11
| (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable
#define | TCC_INTENSET_DFS (_U_(0x1) << TCC_INTENSET_DFS_Pos)
#define | TCC_INTENSET_FAULTA_Pos 12
| (TCC_INTENSET) Recoverable Fault A Interrupt Enable
#define | TCC_INTENSET_FAULTA (_U_(0x1) << TCC_INTENSET_FAULTA_Pos)
#define | TCC_INTENSET_FAULTB_Pos 13
| (TCC_INTENSET) Recoverable Fault B Interrupt Enable
#define | TCC_INTENSET_FAULTB (_U_(0x1) << TCC_INTENSET_FAULTB_Pos)
#define | TCC_INTENSET_FAULT0_Pos 14
| (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable
#define | TCC_INTENSET_FAULT0 (_U_(0x1) << TCC_INTENSET_FAULT0_Pos)
#define | TCC_INTENSET_FAULT1_Pos 15
| (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable
#define | TCC_INTENSET_FAULT1 (_U_(0x1) << TCC_INTENSET_FAULT1_Pos)
#define | TCC_INTENSET_MC0_Pos 16
| (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable
#define | TCC_INTENSET_MC0 (_U_(1) << TCC_INTENSET_MC0_Pos)
#define | TCC_INTENSET_MC1_Pos 17
| (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable
#define | TCC_INTENSET_MC1 (_U_(1) << TCC_INTENSET_MC1_Pos)
#define | TCC_INTENSET_MC2_Pos 18
| (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable
#define | TCC_INTENSET_MC2 (_U_(1) << TCC_INTENSET_MC2_Pos)
#define | TCC_INTENSET_MC3_Pos 19
| (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable
#define | TCC_INTENSET_MC3 (_U_(1) << TCC_INTENSET_MC3_Pos)
#define | TCC_INTENSET_MC4_Pos 20
| (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable
#define | TCC_INTENSET_MC4 (_U_(1) << TCC_INTENSET_MC4_Pos)
#define | TCC_INTENSET_MC5_Pos 21
| (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable
#define | TCC_INTENSET_MC5 (_U_(1) << TCC_INTENSET_MC5_Pos)
#define | TCC_INTENSET_MC_Pos 16
| (TCC_INTENSET) Match or Capture Channel x Interrupt Enable
#define | TCC_INTENSET_MC_Msk (_U_(0x3F) << TCC_INTENSET_MC_Pos)
#define | TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
#define | TCC_INTENSET_MASK _U_(0x003FFC0F)
| (TCC_INTENSET) MASK Register
#define | TCC_INTFLAG_OFFSET 0x2C
| (TCC_INTFLAG offset) Interrupt Flag Status and Clear
#define | TCC_INTFLAG_RESETVALUE _U_(0x00000000)
| (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear
#define | TCC_INTFLAG_OVF_Pos 0
| (TCC_INTFLAG) Overflow
#define | TCC_INTFLAG_OVF (_U_(0x1) << TCC_INTFLAG_OVF_Pos)
#define | TCC_INTFLAG_TRG_Pos 1
| (TCC_INTFLAG) Retrigger
#define | TCC_INTFLAG_TRG (_U_(0x1) << TCC_INTFLAG_TRG_Pos)
#define | TCC_INTFLAG_CNT_Pos 2
| (TCC_INTFLAG) Counter
#define | TCC_INTFLAG_CNT (_U_(0x1) << TCC_INTFLAG_CNT_Pos)
#define | TCC_INTFLAG_ERR_Pos 3
| (TCC_INTFLAG) Error
#define | TCC_INTFLAG_ERR (_U_(0x1) << TCC_INTFLAG_ERR_Pos)
#define | TCC_INTFLAG_UFS_Pos 10
| (TCC_INTFLAG) Non-Recoverable Update Fault
#define | TCC_INTFLAG_UFS (_U_(0x1) << TCC_INTFLAG_UFS_Pos)
#define | TCC_INTFLAG_DFS_Pos 11
| (TCC_INTFLAG) Non-Recoverable Debug Fault
#define | TCC_INTFLAG_DFS (_U_(0x1) << TCC_INTFLAG_DFS_Pos)
#define | TCC_INTFLAG_FAULTA_Pos 12
| (TCC_INTFLAG) Recoverable Fault A
#define | TCC_INTFLAG_FAULTA (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos)
#define | TCC_INTFLAG_FAULTB_Pos 13
| (TCC_INTFLAG) Recoverable Fault B
#define | TCC_INTFLAG_FAULTB (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos)
#define | TCC_INTFLAG_FAULT0_Pos 14
| (TCC_INTFLAG) Non-Recoverable Fault 0
#define | TCC_INTFLAG_FAULT0 (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos)
#define | TCC_INTFLAG_FAULT1_Pos 15
| (TCC_INTFLAG) Non-Recoverable Fault 1
#define | TCC_INTFLAG_FAULT1 (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos)
#define | TCC_INTFLAG_MC0_Pos 16
| (TCC_INTFLAG) Match or Capture 0
#define | TCC_INTFLAG_MC0 (_U_(1) << TCC_INTFLAG_MC0_Pos)
#define | TCC_INTFLAG_MC1_Pos 17
| (TCC_INTFLAG) Match or Capture 1
#define | TCC_INTFLAG_MC1 (_U_(1) << TCC_INTFLAG_MC1_Pos)
#define | TCC_INTFLAG_MC2_Pos 18
| (TCC_INTFLAG) Match or Capture 2
#define | TCC_INTFLAG_MC2 (_U_(1) << TCC_INTFLAG_MC2_Pos)
#define | TCC_INTFLAG_MC3_Pos 19
| (TCC_INTFLAG) Match or Capture 3
#define | TCC_INTFLAG_MC3 (_U_(1) << TCC_INTFLAG_MC3_Pos)
#define | TCC_INTFLAG_MC4_Pos 20
| (TCC_INTFLAG) Match or Capture 4
#define | TCC_INTFLAG_MC4 (_U_(1) << TCC_INTFLAG_MC4_Pos)
#define | TCC_INTFLAG_MC5_Pos 21
| (TCC_INTFLAG) Match or Capture 5
#define | TCC_INTFLAG_MC5 (_U_(1) << TCC_INTFLAG_MC5_Pos)
#define | TCC_INTFLAG_MC_Pos 16
| (TCC_INTFLAG) Match or Capture x
#define | TCC_INTFLAG_MC_Msk (_U_(0x3F) << TCC_INTFLAG_MC_Pos)
#define | TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
#define | TCC_INTFLAG_MASK _U_(0x003FFC0F)
| (TCC_INTFLAG) MASK Register
#define | TCC_STATUS_OFFSET 0x30
| (TCC_STATUS offset) Status
#define | TCC_STATUS_RESETVALUE _U_(0x00000001)
| (TCC_STATUS reset_value) Status
#define | TCC_STATUS_STOP_Pos 0
| (TCC_STATUS) Stop
#define | TCC_STATUS_STOP (_U_(0x1) << TCC_STATUS_STOP_Pos)
#define | TCC_STATUS_IDX_Pos 1
| (TCC_STATUS) Ramp
#define | TCC_STATUS_IDX (_U_(0x1) << TCC_STATUS_IDX_Pos)
#define | TCC_STATUS_UFS_Pos 2
| (TCC_STATUS) Non-recoverable Update Fault State
#define | TCC_STATUS_UFS (_U_(0x1) << TCC_STATUS_UFS_Pos)
#define | TCC_STATUS_DFS_Pos 3
| (TCC_STATUS) Non-Recoverable Debug Fault State
#define | TCC_STATUS_DFS (_U_(0x1) << TCC_STATUS_DFS_Pos)
#define | TCC_STATUS_SLAVE_Pos 4
| (TCC_STATUS) Slave
#define | TCC_STATUS_SLAVE (_U_(0x1) << TCC_STATUS_SLAVE_Pos)
#define | TCC_STATUS_PATTBUFV_Pos 5
| (TCC_STATUS) Pattern Buffer Valid
#define | TCC_STATUS_PATTBUFV (_U_(0x1) << TCC_STATUS_PATTBUFV_Pos)
#define | TCC_STATUS_PERBUFV_Pos 7
| (TCC_STATUS) Period Buffer Valid
#define | TCC_STATUS_PERBUFV (_U_(0x1) << TCC_STATUS_PERBUFV_Pos)
#define | TCC_STATUS_FAULTAIN_Pos 8
| (TCC_STATUS) Recoverable Fault A Input
#define | TCC_STATUS_FAULTAIN (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos)
#define | TCC_STATUS_FAULTBIN_Pos 9
| (TCC_STATUS) Recoverable Fault B Input
#define | TCC_STATUS_FAULTBIN (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos)
#define | TCC_STATUS_FAULT0IN_Pos 10
| (TCC_STATUS) Non-Recoverable Fault0 Input
#define | TCC_STATUS_FAULT0IN (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos)
#define | TCC_STATUS_FAULT1IN_Pos 11
| (TCC_STATUS) Non-Recoverable Fault1 Input
#define | TCC_STATUS_FAULT1IN (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos)
#define | TCC_STATUS_FAULTA_Pos 12
| (TCC_STATUS) Recoverable Fault A State
#define | TCC_STATUS_FAULTA (_U_(0x1) << TCC_STATUS_FAULTA_Pos)
#define | TCC_STATUS_FAULTB_Pos 13
| (TCC_STATUS) Recoverable Fault B State
#define | TCC_STATUS_FAULTB (_U_(0x1) << TCC_STATUS_FAULTB_Pos)
#define | TCC_STATUS_FAULT0_Pos 14
| (TCC_STATUS) Non-Recoverable Fault 0 State
#define | TCC_STATUS_FAULT0 (_U_(0x1) << TCC_STATUS_FAULT0_Pos)
#define | TCC_STATUS_FAULT1_Pos 15
| (TCC_STATUS) Non-Recoverable Fault 1 State
#define | TCC_STATUS_FAULT1 (_U_(0x1) << TCC_STATUS_FAULT1_Pos)
#define | TCC_STATUS_CCBUFV0_Pos 16
| (TCC_STATUS) Compare Channel 0 Buffer Valid
#define | TCC_STATUS_CCBUFV0 (_U_(1) << TCC_STATUS_CCBUFV0_Pos)
#define | TCC_STATUS_CCBUFV1_Pos 17
| (TCC_STATUS) Compare Channel 1 Buffer Valid
#define | TCC_STATUS_CCBUFV1 (_U_(1) << TCC_STATUS_CCBUFV1_Pos)
#define | TCC_STATUS_CCBUFV2_Pos 18
| (TCC_STATUS) Compare Channel 2 Buffer Valid
#define | TCC_STATUS_CCBUFV2 (_U_(1) << TCC_STATUS_CCBUFV2_Pos)
#define | TCC_STATUS_CCBUFV3_Pos 19
| (TCC_STATUS) Compare Channel 3 Buffer Valid
#define | TCC_STATUS_CCBUFV3 (_U_(1) << TCC_STATUS_CCBUFV3_Pos)
#define | TCC_STATUS_CCBUFV4_Pos 20
| (TCC_STATUS) Compare Channel 4 Buffer Valid
#define | TCC_STATUS_CCBUFV4 (_U_(1) << TCC_STATUS_CCBUFV4_Pos)
#define | TCC_STATUS_CCBUFV5_Pos 21
| (TCC_STATUS) Compare Channel 5 Buffer Valid
#define | TCC_STATUS_CCBUFV5 (_U_(1) << TCC_STATUS_CCBUFV5_Pos)
#define | TCC_STATUS_CCBUFV_Pos 16
| (TCC_STATUS) Compare Channel x Buffer Valid
#define | TCC_STATUS_CCBUFV_Msk (_U_(0x3F) << TCC_STATUS_CCBUFV_Pos)
#define | TCC_STATUS_CCBUFV(value) (TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos))
#define | TCC_STATUS_CMP0_Pos 24
| (TCC_STATUS) Compare Channel 0 Value
#define | TCC_STATUS_CMP0 (_U_(1) << TCC_STATUS_CMP0_Pos)
#define | TCC_STATUS_CMP1_Pos 25
| (TCC_STATUS) Compare Channel 1 Value
#define | TCC_STATUS_CMP1 (_U_(1) << TCC_STATUS_CMP1_Pos)
#define | TCC_STATUS_CMP2_Pos 26
| (TCC_STATUS) Compare Channel 2 Value
#define | TCC_STATUS_CMP2 (_U_(1) << TCC_STATUS_CMP2_Pos)
#define | TCC_STATUS_CMP3_Pos 27
| (TCC_STATUS) Compare Channel 3 Value
#define | TCC_STATUS_CMP3 (_U_(1) << TCC_STATUS_CMP3_Pos)
#define | TCC_STATUS_CMP4_Pos 28
| (TCC_STATUS) Compare Channel 4 Value
#define | TCC_STATUS_CMP4 (_U_(1) << TCC_STATUS_CMP4_Pos)
#define | TCC_STATUS_CMP5_Pos 29
| (TCC_STATUS) Compare Channel 5 Value
#define | TCC_STATUS_CMP5 (_U_(1) << TCC_STATUS_CMP5_Pos)
#define | TCC_STATUS_CMP_Pos 24
| (TCC_STATUS) Compare Channel x Value
#define | TCC_STATUS_CMP_Msk (_U_(0x3F) << TCC_STATUS_CMP_Pos)
#define | TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
#define | TCC_STATUS_MASK _U_(0x3F3FFFBF)
| (TCC_STATUS) MASK Register
#define | TCC_COUNT_OFFSET 0x34
| (TCC_COUNT offset) Count
#define | TCC_COUNT_RESETVALUE _U_(0x00000000)
| (TCC_COUNT reset_value) Count
#define | TCC_COUNT_DITH4_COUNT_Pos 4
| (TCC_COUNT_DITH4) Counter Value
#define | TCC_COUNT_DITH4_COUNT_Msk (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos)
#define | TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
#define | TCC_COUNT_DITH4_MASK _U_(0x00FFFFF0)
| (TCC_COUNT_DITH4) MASK Register
#define | TCC_COUNT_DITH5_COUNT_Pos 5
| (TCC_COUNT_DITH5) Counter Value
#define | TCC_COUNT_DITH5_COUNT_Msk (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos)
#define | TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
#define | TCC_COUNT_DITH5_MASK _U_(0x00FFFFE0)
| (TCC_COUNT_DITH5) MASK Register
#define | TCC_COUNT_DITH6_COUNT_Pos 6
| (TCC_COUNT_DITH6) Counter Value
#define | TCC_COUNT_DITH6_COUNT_Msk (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos)
#define | TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
#define | TCC_COUNT_DITH6_MASK _U_(0x00FFFFC0)
| (TCC_COUNT_DITH6) MASK Register
#define | TCC_COUNT_COUNT_Pos 0
| (TCC_COUNT) Counter Value
#define | TCC_COUNT_COUNT_Msk (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos)
#define | TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
#define | TCC_COUNT_MASK _U_(0x00FFFFFF)
| (TCC_COUNT) MASK Register
#define | TCC_PATT_OFFSET 0x38
| (TCC_PATT offset) Pattern
#define | TCC_PATT_RESETVALUE _U_(0x0000)
| (TCC_PATT reset_value) Pattern
#define | TCC_PATT_PGE0_Pos 0
| (TCC_PATT) Pattern Generator 0 Output Enable
#define | TCC_PATT_PGE0 (_U_(1) << TCC_PATT_PGE0_Pos)
#define | TCC_PATT_PGE1_Pos 1
| (TCC_PATT) Pattern Generator 1 Output Enable
#define | TCC_PATT_PGE1 (_U_(1) << TCC_PATT_PGE1_Pos)
#define | TCC_PATT_PGE2_Pos 2
| (TCC_PATT) Pattern Generator 2 Output Enable
#define | TCC_PATT_PGE2 (_U_(1) << TCC_PATT_PGE2_Pos)
#define | TCC_PATT_PGE3_Pos 3
| (TCC_PATT) Pattern Generator 3 Output Enable
#define | TCC_PATT_PGE3 (_U_(1) << TCC_PATT_PGE3_Pos)
#define | TCC_PATT_PGE4_Pos 4
| (TCC_PATT) Pattern Generator 4 Output Enable
#define | TCC_PATT_PGE4 (_U_(1) << TCC_PATT_PGE4_Pos)
#define | TCC_PATT_PGE5_Pos 5
| (TCC_PATT) Pattern Generator 5 Output Enable
#define | TCC_PATT_PGE5 (_U_(1) << TCC_PATT_PGE5_Pos)
#define | TCC_PATT_PGE6_Pos 6
| (TCC_PATT) Pattern Generator 6 Output Enable
#define | TCC_PATT_PGE6 (_U_(1) << TCC_PATT_PGE6_Pos)
#define | TCC_PATT_PGE7_Pos 7
| (TCC_PATT) Pattern Generator 7 Output Enable
#define | TCC_PATT_PGE7 (_U_(1) << TCC_PATT_PGE7_Pos)
#define | TCC_PATT_PGE_Pos 0
| (TCC_PATT) Pattern Generator x Output Enable
#define | TCC_PATT_PGE_Msk (_U_(0xFF) << TCC_PATT_PGE_Pos)
#define | TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
#define | TCC_PATT_PGV0_Pos 8
| (TCC_PATT) Pattern Generator 0 Output Value
#define | TCC_PATT_PGV0 (_U_(1) << TCC_PATT_PGV0_Pos)
#define | TCC_PATT_PGV1_Pos 9
| (TCC_PATT) Pattern Generator 1 Output Value
#define | TCC_PATT_PGV1 (_U_(1) << TCC_PATT_PGV1_Pos)
#define | TCC_PATT_PGV2_Pos 10
| (TCC_PATT) Pattern Generator 2 Output Value
#define | TCC_PATT_PGV2 (_U_(1) << TCC_PATT_PGV2_Pos)
#define | TCC_PATT_PGV3_Pos 11
| (TCC_PATT) Pattern Generator 3 Output Value
#define | TCC_PATT_PGV3 (_U_(1) << TCC_PATT_PGV3_Pos)
#define | TCC_PATT_PGV4_Pos 12
| (TCC_PATT) Pattern Generator 4 Output Value
#define | TCC_PATT_PGV4 (_U_(1) << TCC_PATT_PGV4_Pos)
#define | TCC_PATT_PGV5_Pos 13
| (TCC_PATT) Pattern Generator 5 Output Value
#define | TCC_PATT_PGV5 (_U_(1) << TCC_PATT_PGV5_Pos)
#define | TCC_PATT_PGV6_Pos 14
| (TCC_PATT) Pattern Generator 6 Output Value
#define | TCC_PATT_PGV6 (_U_(1) << TCC_PATT_PGV6_Pos)
#define | TCC_PATT_PGV7_Pos 15
| (TCC_PATT) Pattern Generator 7 Output Value
#define | TCC_PATT_PGV7 (_U_(1) << TCC_PATT_PGV7_Pos)
#define | TCC_PATT_PGV_Pos 8
| (TCC_PATT) Pattern Generator x Output Value
#define | TCC_PATT_PGV_Msk (_U_(0xFF) << TCC_PATT_PGV_Pos)
#define | TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
#define | TCC_PATT_MASK _U_(0xFFFF)
| (TCC_PATT) MASK Register
#define | TCC_WAVE_OFFSET 0x3C
| (TCC_WAVE offset) Waveform Control
#define | TCC_WAVE_RESETVALUE _U_(0x00000000)
| (TCC_WAVE reset_value) Waveform Control
#define | TCC_WAVE_WAVEGEN_Pos 0
| (TCC_WAVE) Waveform Generation
#define | TCC_WAVE_WAVEGEN_Msk (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
#define | TCC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0)
| (TCC_WAVE) Normal frequency
#define | TCC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1)
| (TCC_WAVE) Match frequency
#define | TCC_WAVE_WAVEGEN_NPWM_Val _U_(0x2)
| (TCC_WAVE) Normal PWM
#define | TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4)
| (TCC_WAVE) Dual-slope critical
#define | TCC_WAVE_WAVEGEN_DSBOTTOM_Val _U_(0x5)
| (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO
#define | TCC_WAVE_WAVEGEN_DSBOTH_Val _U_(0x6)
| (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
#define | TCC_WAVE_WAVEGEN_DSTOP_Val _U_(0x7)
| (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP
#define | TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
#define | TCC_WAVE_RAMP_Pos 4
| (TCC_WAVE) Ramp Mode
#define | TCC_WAVE_RAMP_Msk (_U_(0x3) << TCC_WAVE_RAMP_Pos)
#define | TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
#define | TCC_WAVE_RAMP_RAMP1_Val _U_(0x0)
| (TCC_WAVE) RAMP1 operation
#define | TCC_WAVE_RAMP_RAMP2A_Val _U_(0x1)
| (TCC_WAVE) Alternative RAMP2 operation
#define | TCC_WAVE_RAMP_RAMP2_Val _U_(0x2)
| (TCC_WAVE) RAMP2 operation
#define | TCC_WAVE_RAMP_RAMP2C_Val _U_(0x3)
| (TCC_WAVE) Critical RAMP2 operation
#define | TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
#define | TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
#define | TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
#define | TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos)
#define | TCC_WAVE_CIPEREN_Pos 7
| (TCC_WAVE) Circular period Enable
#define | TCC_WAVE_CIPEREN (_U_(0x1) << TCC_WAVE_CIPEREN_Pos)
#define | TCC_WAVE_CICCEN0_Pos 8
| (TCC_WAVE) Circular Channel 0 Enable
#define | TCC_WAVE_CICCEN0 (_U_(1) << TCC_WAVE_CICCEN0_Pos)
#define | TCC_WAVE_CICCEN1_Pos 9
| (TCC_WAVE) Circular Channel 1 Enable
#define | TCC_WAVE_CICCEN1 (_U_(1) << TCC_WAVE_CICCEN1_Pos)
#define | TCC_WAVE_CICCEN2_Pos 10
| (TCC_WAVE) Circular Channel 2 Enable
#define | TCC_WAVE_CICCEN2 (_U_(1) << TCC_WAVE_CICCEN2_Pos)
#define | TCC_WAVE_CICCEN3_Pos 11
| (TCC_WAVE) Circular Channel 3 Enable
#define | TCC_WAVE_CICCEN3 (_U_(1) << TCC_WAVE_CICCEN3_Pos)
#define | TCC_WAVE_CICCEN_Pos 8
| (TCC_WAVE) Circular Channel x Enable
#define | TCC_WAVE_CICCEN_Msk (_U_(0xF) << TCC_WAVE_CICCEN_Pos)
#define | TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
#define | TCC_WAVE_POL0_Pos 16
| (TCC_WAVE) Channel 0 Polarity
#define | TCC_WAVE_POL0 (_U_(1) << TCC_WAVE_POL0_Pos)
#define | TCC_WAVE_POL1_Pos 17
| (TCC_WAVE) Channel 1 Polarity
#define | TCC_WAVE_POL1 (_U_(1) << TCC_WAVE_POL1_Pos)
#define | TCC_WAVE_POL2_Pos 18
| (TCC_WAVE) Channel 2 Polarity
#define | TCC_WAVE_POL2 (_U_(1) << TCC_WAVE_POL2_Pos)
#define | TCC_WAVE_POL3_Pos 19
| (TCC_WAVE) Channel 3 Polarity
#define | TCC_WAVE_POL3 (_U_(1) << TCC_WAVE_POL3_Pos)
#define | TCC_WAVE_POL4_Pos 20
| (TCC_WAVE) Channel 4 Polarity
#define | TCC_WAVE_POL4 (_U_(1) << TCC_WAVE_POL4_Pos)
#define | TCC_WAVE_POL5_Pos 21
| (TCC_WAVE) Channel 5 Polarity
#define | TCC_WAVE_POL5 (_U_(1) << TCC_WAVE_POL5_Pos)
#define | TCC_WAVE_POL_Pos 16
| (TCC_WAVE) Channel x Polarity
#define | TCC_WAVE_POL_Msk (_U_(0x3F) << TCC_WAVE_POL_Pos)
#define | TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
#define | TCC_WAVE_SWAP0_Pos 24
| (TCC_WAVE) Swap DTI Output Pair 0
#define | TCC_WAVE_SWAP0 (_U_(1) << TCC_WAVE_SWAP0_Pos)
#define | TCC_WAVE_SWAP1_Pos 25
| (TCC_WAVE) Swap DTI Output Pair 1
#define | TCC_WAVE_SWAP1 (_U_(1) << TCC_WAVE_SWAP1_Pos)
#define | TCC_WAVE_SWAP2_Pos 26
| (TCC_WAVE) Swap DTI Output Pair 2
#define | TCC_WAVE_SWAP2 (_U_(1) << TCC_WAVE_SWAP2_Pos)
#define | TCC_WAVE_SWAP3_Pos 27
| (TCC_WAVE) Swap DTI Output Pair 3
#define | TCC_WAVE_SWAP3 (_U_(1) << TCC_WAVE_SWAP3_Pos)
#define | TCC_WAVE_SWAP_Pos 24
| (TCC_WAVE) Swap DTI Output Pair x
#define | TCC_WAVE_SWAP_Msk (_U_(0xF) << TCC_WAVE_SWAP_Pos)
#define | TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
#define | TCC_WAVE_MASK _U_(0x0F3F0FB7)
| (TCC_WAVE) MASK Register
#define | TCC_PER_OFFSET 0x40
| (TCC_PER offset) Period
#define | TCC_PER_RESETVALUE _U_(0xFFFFFFFF)
| (TCC_PER reset_value) Period
#define | TCC_PER_DITH4_DITHER_Pos 0
| (TCC_PER_DITH4) Dithering Cycle Number
#define | TCC_PER_DITH4_DITHER_Msk (_U_(0xF) << TCC_PER_DITH4_DITHER_Pos)
#define | TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos))
#define | TCC_PER_DITH4_PER_Pos 4
| (TCC_PER_DITH4) Period Value
#define | TCC_PER_DITH4_PER_Msk (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos)
#define | TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
#define | TCC_PER_DITH4_MASK _U_(0x00FFFFFF)
| (TCC_PER_DITH4) MASK Register
#define | TCC_PER_DITH5_DITHER_Pos 0
| (TCC_PER_DITH5) Dithering Cycle Number
#define | TCC_PER_DITH5_DITHER_Msk (_U_(0x1F) << TCC_PER_DITH5_DITHER_Pos)
#define | TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos))
#define | TCC_PER_DITH5_PER_Pos 5
| (TCC_PER_DITH5) Period Value
#define | TCC_PER_DITH5_PER_Msk (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos)
#define | TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
#define | TCC_PER_DITH5_MASK _U_(0x00FFFFFF)
| (TCC_PER_DITH5) MASK Register
#define | TCC_PER_DITH6_DITHER_Pos 0
| (TCC_PER_DITH6) Dithering Cycle Number
#define | TCC_PER_DITH6_DITHER_Msk (_U_(0x3F) << TCC_PER_DITH6_DITHER_Pos)
#define | TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos))
#define | TCC_PER_DITH6_PER_Pos 6
| (TCC_PER_DITH6) Period Value
#define | TCC_PER_DITH6_PER_Msk (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos)
#define | TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
#define | TCC_PER_DITH6_MASK _U_(0x00FFFFFF)
| (TCC_PER_DITH6) MASK Register
#define | TCC_PER_PER_Pos 0
| (TCC_PER) Period Value
#define | TCC_PER_PER_Msk (_U_(0xFFFFFF) << TCC_PER_PER_Pos)
#define | TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
#define | TCC_PER_MASK _U_(0x00FFFFFF)
| (TCC_PER) MASK Register
#define | TCC_CC_OFFSET 0x44
| (TCC_CC offset) Compare and Capture
#define | TCC_CC_RESETVALUE _U_(0x00000000)
| (TCC_CC reset_value) Compare and Capture
#define | TCC_CC_DITH4_DITHER_Pos 0
| (TCC_CC_DITH4) Dithering Cycle Number
#define | TCC_CC_DITH4_DITHER_Msk (_U_(0xF) << TCC_CC_DITH4_DITHER_Pos)
#define | TCC_CC_DITH4_DITHER(value) (TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos))
#define | TCC_CC_DITH4_CC_Pos 4
| (TCC_CC_DITH4) Channel Compare/Capture Value
#define | TCC_CC_DITH4_CC_Msk (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos)
#define | TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
#define | TCC_CC_DITH4_MASK _U_(0x00FFFFFF)
| (TCC_CC_DITH4) MASK Register
#define | TCC_CC_DITH5_DITHER_Pos 0
| (TCC_CC_DITH5) Dithering Cycle Number
#define | TCC_CC_DITH5_DITHER_Msk (_U_(0x1F) << TCC_CC_DITH5_DITHER_Pos)
#define | TCC_CC_DITH5_DITHER(value) (TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos))
#define | TCC_CC_DITH5_CC_Pos 5
| (TCC_CC_DITH5) Channel Compare/Capture Value
#define | TCC_CC_DITH5_CC_Msk (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos)
#define | TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
#define | TCC_CC_DITH5_MASK _U_(0x00FFFFFF)
| (TCC_CC_DITH5) MASK Register
#define | TCC_CC_DITH6_DITHER_Pos 0
| (TCC_CC_DITH6) Dithering Cycle Number
#define | TCC_CC_DITH6_DITHER_Msk (_U_(0x3F) << TCC_CC_DITH6_DITHER_Pos)
#define | TCC_CC_DITH6_DITHER(value) (TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos))
#define | TCC_CC_DITH6_CC_Pos 6
| (TCC_CC_DITH6) Channel Compare/Capture Value
#define | TCC_CC_DITH6_CC_Msk (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos)
#define | TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
#define | TCC_CC_DITH6_MASK _U_(0x00FFFFFF)
| (TCC_CC_DITH6) MASK Register
#define | TCC_CC_CC_Pos 0
| (TCC_CC) Channel Compare/Capture Value
#define | TCC_CC_CC_Msk (_U_(0xFFFFFF) << TCC_CC_CC_Pos)
#define | TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
#define | TCC_CC_MASK _U_(0x00FFFFFF)
| (TCC_CC) MASK Register
#define | TCC_PATTBUF_OFFSET 0x64
| (TCC_PATTBUF offset) Pattern Buffer
#define | TCC_PATTBUF_RESETVALUE _U_(0x0000)
| (TCC_PATTBUF reset_value) Pattern Buffer
#define | TCC_PATTBUF_PGEB0_Pos 0
| (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer
#define | TCC_PATTBUF_PGEB0 (_U_(1) << TCC_PATTBUF_PGEB0_Pos)
#define | TCC_PATTBUF_PGEB1_Pos 1
| (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer
#define | TCC_PATTBUF_PGEB1 (_U_(1) << TCC_PATTBUF_PGEB1_Pos)
#define | TCC_PATTBUF_PGEB2_Pos 2
| (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer
#define | TCC_PATTBUF_PGEB2 (_U_(1) << TCC_PATTBUF_PGEB2_Pos)
#define | TCC_PATTBUF_PGEB3_Pos 3
| (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer
#define | TCC_PATTBUF_PGEB3 (_U_(1) << TCC_PATTBUF_PGEB3_Pos)
#define | TCC_PATTBUF_PGEB4_Pos 4
| (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer
#define | TCC_PATTBUF_PGEB4 (_U_(1) << TCC_PATTBUF_PGEB4_Pos)
#define | TCC_PATTBUF_PGEB5_Pos 5
| (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer
#define | TCC_PATTBUF_PGEB5 (_U_(1) << TCC_PATTBUF_PGEB5_Pos)
#define | TCC_PATTBUF_PGEB6_Pos 6
| (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer
#define | TCC_PATTBUF_PGEB6 (_U_(1) << TCC_PATTBUF_PGEB6_Pos)
#define | TCC_PATTBUF_PGEB7_Pos 7
| (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer
#define | TCC_PATTBUF_PGEB7 (_U_(1) << TCC_PATTBUF_PGEB7_Pos)
#define | TCC_PATTBUF_PGEB_Pos 0
| (TCC_PATTBUF) Pattern Generator x Output Enable Buffer
#define | TCC_PATTBUF_PGEB_Msk (_U_(0xFF) << TCC_PATTBUF_PGEB_Pos)
#define | TCC_PATTBUF_PGEB(value) (TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos))
#define | TCC_PATTBUF_PGVB0_Pos 8
| (TCC_PATTBUF) Pattern Generator 0 Output Enable
#define | TCC_PATTBUF_PGVB0 (_U_(1) << TCC_PATTBUF_PGVB0_Pos)
#define | TCC_PATTBUF_PGVB1_Pos 9
| (TCC_PATTBUF) Pattern Generator 1 Output Enable
#define | TCC_PATTBUF_PGVB1 (_U_(1) << TCC_PATTBUF_PGVB1_Pos)
#define | TCC_PATTBUF_PGVB2_Pos 10
| (TCC_PATTBUF) Pattern Generator 2 Output Enable
#define | TCC_PATTBUF_PGVB2 (_U_(1) << TCC_PATTBUF_PGVB2_Pos)
#define | TCC_PATTBUF_PGVB3_Pos 11
| (TCC_PATTBUF) Pattern Generator 3 Output Enable
#define | TCC_PATTBUF_PGVB3 (_U_(1) << TCC_PATTBUF_PGVB3_Pos)
#define | TCC_PATTBUF_PGVB4_Pos 12
| (TCC_PATTBUF) Pattern Generator 4 Output Enable
#define | TCC_PATTBUF_PGVB4 (_U_(1) << TCC_PATTBUF_PGVB4_Pos)
#define | TCC_PATTBUF_PGVB5_Pos 13
| (TCC_PATTBUF) Pattern Generator 5 Output Enable
#define | TCC_PATTBUF_PGVB5 (_U_(1) << TCC_PATTBUF_PGVB5_Pos)
#define | TCC_PATTBUF_PGVB6_Pos 14
| (TCC_PATTBUF) Pattern Generator 6 Output Enable
#define | TCC_PATTBUF_PGVB6 (_U_(1) << TCC_PATTBUF_PGVB6_Pos)
#define | TCC_PATTBUF_PGVB7_Pos 15
| (TCC_PATTBUF) Pattern Generator 7 Output Enable
#define | TCC_PATTBUF_PGVB7 (_U_(1) << TCC_PATTBUF_PGVB7_Pos)
#define | TCC_PATTBUF_PGVB_Pos 8
| (TCC_PATTBUF) Pattern Generator x Output Enable
#define | TCC_PATTBUF_PGVB_Msk (_U_(0xFF) << TCC_PATTBUF_PGVB_Pos)
#define | TCC_PATTBUF_PGVB(value) (TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos))
#define | TCC_PATTBUF_MASK _U_(0xFFFF)
| (TCC_PATTBUF) MASK Register
#define | TCC_PERBUF_OFFSET 0x6C
| (TCC_PERBUF offset) Period Buffer
#define | TCC_PERBUF_RESETVALUE _U_(0xFFFFFFFF)
| (TCC_PERBUF reset_value) Period Buffer
#define | TCC_PERBUF_DITH4_DITHERBUF_Pos 0
| (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number
#define | TCC_PERBUF_DITH4_DITHERBUF_Msk (_U_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos)
#define | TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos))
#define | TCC_PERBUF_DITH4_PERBUF_Pos 4
| (TCC_PERBUF_DITH4) Period Buffer Value
#define | TCC_PERBUF_DITH4_PERBUF_Msk (_U_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos)
#define | TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos))
#define | TCC_PERBUF_DITH4_MASK _U_(0x00FFFFFF)
| (TCC_PERBUF_DITH4) MASK Register
#define | TCC_PERBUF_DITH5_DITHERBUF_Pos 0
| (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number
#define | TCC_PERBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos)
#define | TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos))
#define | TCC_PERBUF_DITH5_PERBUF_Pos 5
| (TCC_PERBUF_DITH5) Period Buffer Value
#define | TCC_PERBUF_DITH5_PERBUF_Msk (_U_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos)
#define | TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos))
#define | TCC_PERBUF_DITH5_MASK _U_(0x00FFFFFF)
| (TCC_PERBUF_DITH5) MASK Register
#define | TCC_PERBUF_DITH6_DITHERBUF_Pos 0
| (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number
#define | TCC_PERBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos)
#define | TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos))
#define | TCC_PERBUF_DITH6_PERBUF_Pos 6
| (TCC_PERBUF_DITH6) Period Buffer Value
#define | TCC_PERBUF_DITH6_PERBUF_Msk (_U_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos)
#define | TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos))
#define | TCC_PERBUF_DITH6_MASK _U_(0x00FFFFFF)
| (TCC_PERBUF_DITH6) MASK Register
#define | TCC_PERBUF_PERBUF_Pos 0
| (TCC_PERBUF) Period Buffer Value
#define | TCC_PERBUF_PERBUF_Msk (_U_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos)
#define | TCC_PERBUF_PERBUF(value) (TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos))
#define | TCC_PERBUF_MASK _U_(0x00FFFFFF)
| (TCC_PERBUF) MASK Register
#define | TCC_CCBUF_OFFSET 0x70
| (TCC_CCBUF offset) Compare and Capture Buffer
#define | TCC_CCBUF_RESETVALUE _U_(0x00000000)
| (TCC_CCBUF reset_value) Compare and Capture Buffer
#define | TCC_CCBUF_DITH4_CCBUF_Pos 0
| (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value
#define | TCC_CCBUF_DITH4_CCBUF_Msk (_U_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos)
#define | TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos))
#define | TCC_CCBUF_DITH4_DITHERBUF_Pos 4
| (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number
#define | TCC_CCBUF_DITH4_DITHERBUF_Msk (_U_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos)
#define | TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos))
#define | TCC_CCBUF_DITH4_MASK _U_(0x00FFFFFF)
| (TCC_CCBUF_DITH4) MASK Register
#define | TCC_CCBUF_DITH5_DITHERBUF_Pos 0
| (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number
#define | TCC_CCBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos)
#define | TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos))
#define | TCC_CCBUF_DITH5_CCBUF_Pos 5
| (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value
#define | TCC_CCBUF_DITH5_CCBUF_Msk (_U_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos)
#define | TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos))
#define | TCC_CCBUF_DITH5_MASK _U_(0x00FFFFFF)
| (TCC_CCBUF_DITH5) MASK Register
#define | TCC_CCBUF_DITH6_DITHERBUF_Pos 0
| (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number
#define | TCC_CCBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos)
#define | TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos))
#define | TCC_CCBUF_DITH6_CCBUF_Pos 6
| (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value
#define | TCC_CCBUF_DITH6_CCBUF_Msk (_U_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos)
#define | TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos))
#define | TCC_CCBUF_DITH6_MASK _U_(0x00FFFFFF)
| (TCC_CCBUF_DITH6) MASK Register
#define | TCC_CCBUF_CCBUF_Pos 0
| (TCC_CCBUF) Channel Compare/Capture Buffer Value
#define | TCC_CCBUF_CCBUF_Msk (_U_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos)
#define | TCC_CCBUF_CCBUF(value) (TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos))
#define | TCC_CCBUF_MASK _U_(0x00FFFFFF)
| (TCC_CCBUF) MASK Register

## Detailed Description

Component description for TCC.

Copyright (c) 2019 Microchip Technology Inc.

\asf_license_start

Definition in file tcc.h.