evsys.h
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#ifndef _SAME54_EVSYS_COMPONENT_
#define _SAME54_EVSYS_COMPONENT_
/* ========================================================================== */
/* ========================================================================== */
#define EVSYS_U2504
#define REV_EVSYS 0x100
/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x000) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1;
uint8_t :7;
} bit;
uint8_t reg;
} EVSYS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CTRLA_OFFSET 0x000
#define EVSYS_CTRLA_RESETVALUE _U_(0x00)
#define EVSYS_CTRLA_SWRST_Pos 0
#define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
#define EVSYS_CTRLA_MASK _U_(0x01)
/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x004) ( /W 32) Software Event -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL0:1;
uint32_t CHANNEL1:1;
uint32_t CHANNEL2:1;
uint32_t CHANNEL3:1;
uint32_t CHANNEL4:1;
uint32_t CHANNEL5:1;
uint32_t CHANNEL6:1;
uint32_t CHANNEL7:1;
uint32_t CHANNEL8:1;
uint32_t CHANNEL9:1;
uint32_t CHANNEL10:1;
uint32_t CHANNEL11:1;
uint32_t CHANNEL12:1;
uint32_t CHANNEL13:1;
uint32_t CHANNEL14:1;
uint32_t CHANNEL15:1;
uint32_t CHANNEL16:1;
uint32_t CHANNEL17:1;
uint32_t CHANNEL18:1;
uint32_t CHANNEL19:1;
uint32_t CHANNEL20:1;
uint32_t CHANNEL21:1;
uint32_t CHANNEL22:1;
uint32_t CHANNEL23:1;
uint32_t CHANNEL24:1;
uint32_t CHANNEL25:1;
uint32_t CHANNEL26:1;
uint32_t CHANNEL27:1;
uint32_t CHANNEL28:1;
uint32_t CHANNEL29:1;
uint32_t CHANNEL30:1;
uint32_t CHANNEL31:1;
} bit;
struct {
uint32_t CHANNEL:32;
} vec;
uint32_t reg;
} EVSYS_SWEVT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_SWEVT_OFFSET 0x004
#define EVSYS_SWEVT_RESETVALUE _U_(0x00000000)
#define EVSYS_SWEVT_CHANNEL0_Pos 0
#define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
#define EVSYS_SWEVT_CHANNEL1_Pos 1
#define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
#define EVSYS_SWEVT_CHANNEL2_Pos 2
#define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
#define EVSYS_SWEVT_CHANNEL3_Pos 3
#define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
#define EVSYS_SWEVT_CHANNEL4_Pos 4
#define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
#define EVSYS_SWEVT_CHANNEL5_Pos 5
#define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
#define EVSYS_SWEVT_CHANNEL6_Pos 6
#define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
#define EVSYS_SWEVT_CHANNEL7_Pos 7
#define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
#define EVSYS_SWEVT_CHANNEL8_Pos 8
#define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
#define EVSYS_SWEVT_CHANNEL9_Pos 9
#define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
#define EVSYS_SWEVT_CHANNEL10_Pos 10
#define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
#define EVSYS_SWEVT_CHANNEL11_Pos 11
#define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
#define EVSYS_SWEVT_CHANNEL12_Pos 12
#define EVSYS_SWEVT_CHANNEL12 (_U_(1) << EVSYS_SWEVT_CHANNEL12_Pos)
#define EVSYS_SWEVT_CHANNEL13_Pos 13
#define EVSYS_SWEVT_CHANNEL13 (_U_(1) << EVSYS_SWEVT_CHANNEL13_Pos)
#define EVSYS_SWEVT_CHANNEL14_Pos 14
#define EVSYS_SWEVT_CHANNEL14 (_U_(1) << EVSYS_SWEVT_CHANNEL14_Pos)
#define EVSYS_SWEVT_CHANNEL15_Pos 15
#define EVSYS_SWEVT_CHANNEL15 (_U_(1) << EVSYS_SWEVT_CHANNEL15_Pos)
#define EVSYS_SWEVT_CHANNEL16_Pos 16
#define EVSYS_SWEVT_CHANNEL16 (_U_(1) << EVSYS_SWEVT_CHANNEL16_Pos)
#define EVSYS_SWEVT_CHANNEL17_Pos 17
#define EVSYS_SWEVT_CHANNEL17 (_U_(1) << EVSYS_SWEVT_CHANNEL17_Pos)
#define EVSYS_SWEVT_CHANNEL18_Pos 18
#define EVSYS_SWEVT_CHANNEL18 (_U_(1) << EVSYS_SWEVT_CHANNEL18_Pos)
#define EVSYS_SWEVT_CHANNEL19_Pos 19
#define EVSYS_SWEVT_CHANNEL19 (_U_(1) << EVSYS_SWEVT_CHANNEL19_Pos)
#define EVSYS_SWEVT_CHANNEL20_Pos 20
#define EVSYS_SWEVT_CHANNEL20 (_U_(1) << EVSYS_SWEVT_CHANNEL20_Pos)
#define EVSYS_SWEVT_CHANNEL21_Pos 21
#define EVSYS_SWEVT_CHANNEL21 (_U_(1) << EVSYS_SWEVT_CHANNEL21_Pos)
#define EVSYS_SWEVT_CHANNEL22_Pos 22
#define EVSYS_SWEVT_CHANNEL22 (_U_(1) << EVSYS_SWEVT_CHANNEL22_Pos)
#define EVSYS_SWEVT_CHANNEL23_Pos 23
#define EVSYS_SWEVT_CHANNEL23 (_U_(1) << EVSYS_SWEVT_CHANNEL23_Pos)
#define EVSYS_SWEVT_CHANNEL24_Pos 24
#define EVSYS_SWEVT_CHANNEL24 (_U_(1) << EVSYS_SWEVT_CHANNEL24_Pos)
#define EVSYS_SWEVT_CHANNEL25_Pos 25
#define EVSYS_SWEVT_CHANNEL25 (_U_(1) << EVSYS_SWEVT_CHANNEL25_Pos)
#define EVSYS_SWEVT_CHANNEL26_Pos 26
#define EVSYS_SWEVT_CHANNEL26 (_U_(1) << EVSYS_SWEVT_CHANNEL26_Pos)
#define EVSYS_SWEVT_CHANNEL27_Pos 27
#define EVSYS_SWEVT_CHANNEL27 (_U_(1) << EVSYS_SWEVT_CHANNEL27_Pos)
#define EVSYS_SWEVT_CHANNEL28_Pos 28
#define EVSYS_SWEVT_CHANNEL28 (_U_(1) << EVSYS_SWEVT_CHANNEL28_Pos)
#define EVSYS_SWEVT_CHANNEL29_Pos 29
#define EVSYS_SWEVT_CHANNEL29 (_U_(1) << EVSYS_SWEVT_CHANNEL29_Pos)
#define EVSYS_SWEVT_CHANNEL30_Pos 30
#define EVSYS_SWEVT_CHANNEL30 (_U_(1) << EVSYS_SWEVT_CHANNEL30_Pos)
#define EVSYS_SWEVT_CHANNEL31_Pos 31
#define EVSYS_SWEVT_CHANNEL31 (_U_(1) << EVSYS_SWEVT_CHANNEL31_Pos)
#define EVSYS_SWEVT_CHANNEL_Pos 0
#define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFFFFFFF) << EVSYS_SWEVT_CHANNEL_Pos)
#define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
#define EVSYS_SWEVT_MASK _U_(0xFFFFFFFF)
/* -------- EVSYS_PRICTRL : (EVSYS Offset: 0x008) (R/W 8) Priority Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PRI:4;
uint8_t :3;
uint8_t RREN:1;
} bit;
uint8_t reg;
} EVSYS_PRICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_PRICTRL_OFFSET 0x008
#define EVSYS_PRICTRL_RESETVALUE _U_(0x00)
#define EVSYS_PRICTRL_PRI_Pos 0
#define EVSYS_PRICTRL_PRI_Msk (_U_(0xF) << EVSYS_PRICTRL_PRI_Pos)
#define EVSYS_PRICTRL_PRI(value) (EVSYS_PRICTRL_PRI_Msk & ((value) << EVSYS_PRICTRL_PRI_Pos))
#define EVSYS_PRICTRL_RREN_Pos 7
#define EVSYS_PRICTRL_RREN (_U_(0x1) << EVSYS_PRICTRL_RREN_Pos)
#define EVSYS_PRICTRL_MASK _U_(0x8F)
/* -------- EVSYS_INTPEND : (EVSYS Offset: 0x010) (R/W 16) Channel Pending Interrupt -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:4;
uint16_t :4;
uint16_t OVR:1;
uint16_t EVD:1;
uint16_t :4;
uint16_t READY:1;
uint16_t BUSY:1;
} bit;
uint16_t reg;
} EVSYS_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTPEND_OFFSET 0x010
#define EVSYS_INTPEND_RESETVALUE _U_(0x4000)
#define EVSYS_INTPEND_ID_Pos 0
#define EVSYS_INTPEND_ID_Msk (_U_(0xF) << EVSYS_INTPEND_ID_Pos)
#define EVSYS_INTPEND_ID(value) (EVSYS_INTPEND_ID_Msk & ((value) << EVSYS_INTPEND_ID_Pos))
#define EVSYS_INTPEND_OVR_Pos 8
#define EVSYS_INTPEND_OVR (_U_(0x1) << EVSYS_INTPEND_OVR_Pos)
#define EVSYS_INTPEND_EVD_Pos 9
#define EVSYS_INTPEND_EVD (_U_(0x1) << EVSYS_INTPEND_EVD_Pos)
#define EVSYS_INTPEND_READY_Pos 14
#define EVSYS_INTPEND_READY (_U_(0x1) << EVSYS_INTPEND_READY_Pos)
#define EVSYS_INTPEND_BUSY_Pos 15
#define EVSYS_INTPEND_BUSY (_U_(0x1) << EVSYS_INTPEND_BUSY_Pos)
#define EVSYS_INTPEND_MASK _U_(0xC30F)
/* -------- EVSYS_INTSTATUS : (EVSYS Offset: 0x014) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHINT0:1;
uint32_t CHINT1:1;
uint32_t CHINT2:1;
uint32_t CHINT3:1;
uint32_t CHINT4:1;
uint32_t CHINT5:1;
uint32_t CHINT6:1;
uint32_t CHINT7:1;
uint32_t CHINT8:1;
uint32_t CHINT9:1;
uint32_t CHINT10:1;
uint32_t CHINT11:1;
uint32_t :20;
} bit;
struct {
uint32_t CHINT:12;
uint32_t :20;
} vec;
uint32_t reg;
} EVSYS_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTSTATUS_OFFSET 0x014
#define EVSYS_INTSTATUS_RESETVALUE _U_(0x00000000)
#define EVSYS_INTSTATUS_CHINT0_Pos 0
#define EVSYS_INTSTATUS_CHINT0 (_U_(1) << EVSYS_INTSTATUS_CHINT0_Pos)
#define EVSYS_INTSTATUS_CHINT1_Pos 1
#define EVSYS_INTSTATUS_CHINT1 (_U_(1) << EVSYS_INTSTATUS_CHINT1_Pos)
#define EVSYS_INTSTATUS_CHINT2_Pos 2
#define EVSYS_INTSTATUS_CHINT2 (_U_(1) << EVSYS_INTSTATUS_CHINT2_Pos)
#define EVSYS_INTSTATUS_CHINT3_Pos 3
#define EVSYS_INTSTATUS_CHINT3 (_U_(1) << EVSYS_INTSTATUS_CHINT3_Pos)
#define EVSYS_INTSTATUS_CHINT4_Pos 4
#define EVSYS_INTSTATUS_CHINT4 (_U_(1) << EVSYS_INTSTATUS_CHINT4_Pos)
#define EVSYS_INTSTATUS_CHINT5_Pos 5
#define EVSYS_INTSTATUS_CHINT5 (_U_(1) << EVSYS_INTSTATUS_CHINT5_Pos)
#define EVSYS_INTSTATUS_CHINT6_Pos 6
#define EVSYS_INTSTATUS_CHINT6 (_U_(1) << EVSYS_INTSTATUS_CHINT6_Pos)
#define EVSYS_INTSTATUS_CHINT7_Pos 7
#define EVSYS_INTSTATUS_CHINT7 (_U_(1) << EVSYS_INTSTATUS_CHINT7_Pos)
#define EVSYS_INTSTATUS_CHINT8_Pos 8
#define EVSYS_INTSTATUS_CHINT8 (_U_(1) << EVSYS_INTSTATUS_CHINT8_Pos)
#define EVSYS_INTSTATUS_CHINT9_Pos 9
#define EVSYS_INTSTATUS_CHINT9 (_U_(1) << EVSYS_INTSTATUS_CHINT9_Pos)
#define EVSYS_INTSTATUS_CHINT10_Pos 10
#define EVSYS_INTSTATUS_CHINT10 (_U_(1) << EVSYS_INTSTATUS_CHINT10_Pos)
#define EVSYS_INTSTATUS_CHINT11_Pos 11
#define EVSYS_INTSTATUS_CHINT11 (_U_(1) << EVSYS_INTSTATUS_CHINT11_Pos)
#define EVSYS_INTSTATUS_CHINT_Pos 0
#define EVSYS_INTSTATUS_CHINT_Msk (_U_(0xFFF) << EVSYS_INTSTATUS_CHINT_Pos)
#define EVSYS_INTSTATUS_CHINT(value) (EVSYS_INTSTATUS_CHINT_Msk & ((value) << EVSYS_INTSTATUS_CHINT_Pos))
#define EVSYS_INTSTATUS_MASK _U_(0x00000FFF)
/* -------- EVSYS_BUSYCH : (EVSYS Offset: 0x018) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BUSYCH0:1;
uint32_t BUSYCH1:1;
uint32_t BUSYCH2:1;
uint32_t BUSYCH3:1;
uint32_t BUSYCH4:1;
uint32_t BUSYCH5:1;
uint32_t BUSYCH6:1;
uint32_t BUSYCH7:1;
uint32_t BUSYCH8:1;
uint32_t BUSYCH9:1;
uint32_t BUSYCH10:1;
uint32_t BUSYCH11:1;
uint32_t :20;
} bit;
struct {
uint32_t BUSYCH:12;
uint32_t :20;
} vec;
uint32_t reg;
} EVSYS_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_BUSYCH_OFFSET 0x018
#define EVSYS_BUSYCH_RESETVALUE _U_(0x00000000)
#define EVSYS_BUSYCH_BUSYCH0_Pos 0
#define EVSYS_BUSYCH_BUSYCH0 (_U_(1) << EVSYS_BUSYCH_BUSYCH0_Pos)
#define EVSYS_BUSYCH_BUSYCH1_Pos 1
#define EVSYS_BUSYCH_BUSYCH1 (_U_(1) << EVSYS_BUSYCH_BUSYCH1_Pos)
#define EVSYS_BUSYCH_BUSYCH2_Pos 2
#define EVSYS_BUSYCH_BUSYCH2 (_U_(1) << EVSYS_BUSYCH_BUSYCH2_Pos)
#define EVSYS_BUSYCH_BUSYCH3_Pos 3
#define EVSYS_BUSYCH_BUSYCH3 (_U_(1) << EVSYS_BUSYCH_BUSYCH3_Pos)
#define EVSYS_BUSYCH_BUSYCH4_Pos 4
#define EVSYS_BUSYCH_BUSYCH4 (_U_(1) << EVSYS_BUSYCH_BUSYCH4_Pos)
#define EVSYS_BUSYCH_BUSYCH5_Pos 5
#define EVSYS_BUSYCH_BUSYCH5 (_U_(1) << EVSYS_BUSYCH_BUSYCH5_Pos)
#define EVSYS_BUSYCH_BUSYCH6_Pos 6
#define EVSYS_BUSYCH_BUSYCH6 (_U_(1) << EVSYS_BUSYCH_BUSYCH6_Pos)
#define EVSYS_BUSYCH_BUSYCH7_Pos 7
#define EVSYS_BUSYCH_BUSYCH7 (_U_(1) << EVSYS_BUSYCH_BUSYCH7_Pos)
#define EVSYS_BUSYCH_BUSYCH8_Pos 8
#define EVSYS_BUSYCH_BUSYCH8 (_U_(1) << EVSYS_BUSYCH_BUSYCH8_Pos)
#define EVSYS_BUSYCH_BUSYCH9_Pos 9
#define EVSYS_BUSYCH_BUSYCH9 (_U_(1) << EVSYS_BUSYCH_BUSYCH9_Pos)
#define EVSYS_BUSYCH_BUSYCH10_Pos 10
#define EVSYS_BUSYCH_BUSYCH10 (_U_(1) << EVSYS_BUSYCH_BUSYCH10_Pos)
#define EVSYS_BUSYCH_BUSYCH11_Pos 11
#define EVSYS_BUSYCH_BUSYCH11 (_U_(1) << EVSYS_BUSYCH_BUSYCH11_Pos)
#define EVSYS_BUSYCH_BUSYCH_Pos 0
#define EVSYS_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << EVSYS_BUSYCH_BUSYCH_Pos)
#define EVSYS_BUSYCH_BUSYCH(value) (EVSYS_BUSYCH_BUSYCH_Msk & ((value) << EVSYS_BUSYCH_BUSYCH_Pos))
#define EVSYS_BUSYCH_MASK _U_(0x00000FFF)
/* -------- EVSYS_READYUSR : (EVSYS Offset: 0x01C) (R/ 32) Ready Users -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t READYUSR0:1;
uint32_t READYUSR1:1;
uint32_t READYUSR2:1;
uint32_t READYUSR3:1;
uint32_t READYUSR4:1;
uint32_t READYUSR5:1;
uint32_t READYUSR6:1;
uint32_t READYUSR7:1;
uint32_t READYUSR8:1;
uint32_t READYUSR9:1;
uint32_t READYUSR10:1;
uint32_t READYUSR11:1;
uint32_t :20;
} bit;
struct {
uint32_t READYUSR:12;
uint32_t :20;
} vec;
uint32_t reg;
} EVSYS_READYUSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_READYUSR_OFFSET 0x01C
#define EVSYS_READYUSR_RESETVALUE _U_(0xFFFFFFFF)
#define EVSYS_READYUSR_READYUSR0_Pos 0
#define EVSYS_READYUSR_READYUSR0 (_U_(1) << EVSYS_READYUSR_READYUSR0_Pos)
#define EVSYS_READYUSR_READYUSR1_Pos 1
#define EVSYS_READYUSR_READYUSR1 (_U_(1) << EVSYS_READYUSR_READYUSR1_Pos)
#define EVSYS_READYUSR_READYUSR2_Pos 2
#define EVSYS_READYUSR_READYUSR2 (_U_(1) << EVSYS_READYUSR_READYUSR2_Pos)
#define EVSYS_READYUSR_READYUSR3_Pos 3
#define EVSYS_READYUSR_READYUSR3 (_U_(1) << EVSYS_READYUSR_READYUSR3_Pos)
#define EVSYS_READYUSR_READYUSR4_Pos 4
#define EVSYS_READYUSR_READYUSR4 (_U_(1) << EVSYS_READYUSR_READYUSR4_Pos)
#define EVSYS_READYUSR_READYUSR5_Pos 5
#define EVSYS_READYUSR_READYUSR5 (_U_(1) << EVSYS_READYUSR_READYUSR5_Pos)
#define EVSYS_READYUSR_READYUSR6_Pos 6
#define EVSYS_READYUSR_READYUSR6 (_U_(1) << EVSYS_READYUSR_READYUSR6_Pos)
#define EVSYS_READYUSR_READYUSR7_Pos 7
#define EVSYS_READYUSR_READYUSR7 (_U_(1) << EVSYS_READYUSR_READYUSR7_Pos)
#define EVSYS_READYUSR_READYUSR8_Pos 8
#define EVSYS_READYUSR_READYUSR8 (_U_(1) << EVSYS_READYUSR_READYUSR8_Pos)
#define EVSYS_READYUSR_READYUSR9_Pos 9
#define EVSYS_READYUSR_READYUSR9 (_U_(1) << EVSYS_READYUSR_READYUSR9_Pos)
#define EVSYS_READYUSR_READYUSR10_Pos 10
#define EVSYS_READYUSR_READYUSR10 (_U_(1) << EVSYS_READYUSR_READYUSR10_Pos)
#define EVSYS_READYUSR_READYUSR11_Pos 11
#define EVSYS_READYUSR_READYUSR11 (_U_(1) << EVSYS_READYUSR_READYUSR11_Pos)
#define EVSYS_READYUSR_READYUSR_Pos 0
#define EVSYS_READYUSR_READYUSR_Msk (_U_(0xFFF) << EVSYS_READYUSR_READYUSR_Pos)
#define EVSYS_READYUSR_READYUSR(value) (EVSYS_READYUSR_READYUSR_Msk & ((value) << EVSYS_READYUSR_READYUSR_Pos))
#define EVSYS_READYUSR_MASK _U_(0x00000FFF)
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x020) (R/W 32) CHANNEL Channel n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVGEN:7;
uint32_t :1;
uint32_t PATH:2;
uint32_t EDGSEL:2;
uint32_t :2;
uint32_t RUNSTDBY:1;
uint32_t ONDEMAND:1;
uint32_t :16;
} bit;
uint32_t reg;
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHANNEL_OFFSET 0x020
#define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000)
#define EVSYS_CHANNEL_EVGEN_Pos 0
#define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
#define EVSYS_CHANNEL_PATH_Pos 8
#define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0)
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1)
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2)
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_EDGSEL_Pos 10
#define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0)
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1)
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2)
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3)
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_RUNSTDBY_Pos 14
#define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
#define EVSYS_CHANNEL_ONDEMAND_Pos 15
#define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
#define EVSYS_CHANNEL_MASK _U_(0x0000CF7F)
/* -------- EVSYS_CHINTENCLR : (EVSYS Offset: 0x024) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVR:1;
uint8_t EVD:1;
uint8_t :6;
} bit;
uint8_t reg;
} EVSYS_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHINTENCLR_OFFSET 0x024
#define EVSYS_CHINTENCLR_RESETVALUE _U_(0x00)
#define EVSYS_CHINTENCLR_OVR_Pos 0
#define EVSYS_CHINTENCLR_OVR (_U_(0x1) << EVSYS_CHINTENCLR_OVR_Pos)
#define EVSYS_CHINTENCLR_EVD_Pos 1
#define EVSYS_CHINTENCLR_EVD (_U_(0x1) << EVSYS_CHINTENCLR_EVD_Pos)
#define EVSYS_CHINTENCLR_MASK _U_(0x03)
/* -------- EVSYS_CHINTENSET : (EVSYS Offset: 0x025) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVR:1;
uint8_t EVD:1;
uint8_t :6;
} bit;
uint8_t reg;
} EVSYS_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHINTENSET_OFFSET 0x025
#define EVSYS_CHINTENSET_RESETVALUE _U_(0x00)
#define EVSYS_CHINTENSET_OVR_Pos 0
#define EVSYS_CHINTENSET_OVR (_U_(0x1) << EVSYS_CHINTENSET_OVR_Pos)
#define EVSYS_CHINTENSET_EVD_Pos 1
#define EVSYS_CHINTENSET_EVD (_U_(0x1) << EVSYS_CHINTENSET_EVD_Pos)
#define EVSYS_CHINTENSET_MASK _U_(0x03)
/* -------- EVSYS_CHINTFLAG : (EVSYS Offset: 0x026) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t OVR:1;
__I uint8_t EVD:1;
__I uint8_t :6;
} bit;
uint8_t reg;
} EVSYS_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHINTFLAG_OFFSET 0x026
#define EVSYS_CHINTFLAG_RESETVALUE _U_(0x00)
#define EVSYS_CHINTFLAG_OVR_Pos 0
#define EVSYS_CHINTFLAG_OVR (_U_(0x1) << EVSYS_CHINTFLAG_OVR_Pos)
#define EVSYS_CHINTFLAG_EVD_Pos 1
#define EVSYS_CHINTFLAG_EVD (_U_(0x1) << EVSYS_CHINTFLAG_EVD_Pos)
#define EVSYS_CHINTFLAG_MASK _U_(0x03)
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x027) (R/ 8) CHANNEL Channel n Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RDYUSR:1;
uint8_t BUSYCH:1;
uint8_t :6;
} bit;
uint8_t reg;
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHSTATUS_OFFSET 0x027
#define EVSYS_CHSTATUS_RESETVALUE _U_(0x01)
#define EVSYS_CHSTATUS_RDYUSR_Pos 0
#define EVSYS_CHSTATUS_RDYUSR (_U_(0x1) << EVSYS_CHSTATUS_RDYUSR_Pos)
#define EVSYS_CHSTATUS_BUSYCH_Pos 1
#define EVSYS_CHSTATUS_BUSYCH (_U_(0x1) << EVSYS_CHSTATUS_BUSYCH_Pos)
#define EVSYS_CHSTATUS_MASK _U_(0x03)
/* -------- EVSYS_USER : (EVSYS Offset: 0x120) (R/W 32) User Multiplexer n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL:6;
uint32_t :26;
} bit;
uint32_t reg;
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_USER_OFFSET 0x120
#define EVSYS_USER_RESETVALUE _U_(0x00000000)
#define EVSYS_USER_CHANNEL_Pos 0
#define EVSYS_USER_CHANNEL_Msk (_U_(0x3F) << EVSYS_USER_CHANNEL_Pos)
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
#define EVSYS_USER_MASK _U_(0x0000003F)
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EVSYS_CHANNEL_Type CHANNEL;
__IO EVSYS_CHINTENCLR_Type CHINTENCLR;
__IO EVSYS_CHINTENSET_Type CHINTENSET;
__IO EVSYS_CHINTFLAG_Type CHINTFLAG;
__I EVSYS_CHSTATUS_Type CHSTATUS;
} EvsysChannel;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EVSYS_CTRLA_Type CTRLA;
RoReg8 Reserved1[0x3];
__O EVSYS_SWEVT_Type SWEVT;
__IO EVSYS_PRICTRL_Type PRICTRL;
RoReg8 Reserved2[0x7];
__IO EVSYS_INTPEND_Type INTPEND;
RoReg8 Reserved3[0x2];
__I EVSYS_INTSTATUS_Type INTSTATUS;
__I EVSYS_BUSYCH_Type BUSYCH;
__I EVSYS_READYUSR_Type READYUSR;
EvsysChannel Channel[32];
__IO EVSYS_USER_Type USER[67];
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME54_EVSYS_COMPONENT_ */
EVSYS_READYUSR_Type::READYUSR5
uint32_t READYUSR5
Definition: evsys.h:355
EvsysChannel::CHINTENCLR
__IO EVSYS_CHINTENCLR_Type CHINTENCLR
Offset: 0x004 (R/W 8) Channel n Interrupt Enable Clear.
Definition: evsys.h:560
EVSYS_READYUSR_Type::READYUSR6
uint32_t READYUSR6
Definition: evsys.h:356
EVSYS_CHSTATUS_Type::reg
uint8_t reg
Definition: evsys.h:524
EVSYS_INTSTATUS_Type::CHINT8
uint32_t CHINT8
Definition: evsys.h:242
EVSYS_CHINTENCLR_Type
Definition: evsys.h:455
EVSYS_BUSYCH_Type::reg
uint32_t reg
Definition: evsys.h:310
EVSYS_READYUSR_Type::READYUSR4
uint32_t READYUSR4
Definition: evsys.h:354
EVSYS_READYUSR_Type::READYUSR10
uint32_t READYUSR10
Definition: evsys.h:360
EVSYS_SWEVT_Type::CHANNEL4
uint32_t CHANNEL4
Definition: evsys.h:68
EVSYS_CHSTATUS_Type::RDYUSR
uint8_t RDYUSR
Definition: evsys.h:520
EVSYS_CHINTENSET_Type::OVR
uint8_t OVR
Definition: evsys.h:478
EVSYS_CHINTFLAG_Type::reg
uint8_t reg
Definition: evsys.h:503
EVSYS_BUSYCH_Type::BUSYCH5
uint32_t BUSYCH5
Definition: evsys.h:297
EVSYS_READYUSR_Type::READYUSR8
uint32_t READYUSR8
Definition: evsys.h:358
EVSYS_INTSTATUS_Type::CHINT
uint32_t CHINT
Definition: evsys.h:249
EVSYS_SWEVT_Type::CHANNEL21
uint32_t CHANNEL21
Definition: evsys.h:85
EVSYS_CHINTENCLR_Type::OVR
uint8_t OVR
Definition: evsys.h:457
EVSYS_SWEVT_Type::CHANNEL23
uint32_t CHANNEL23
Definition: evsys.h:87
EVSYS_CHANNEL_Type
Definition: evsys.h:406
EVSYS_INTPEND_Type::reg
uint16_t reg
Definition: evsys.h:210
EvsysChannel::CHSTATUS
__I EVSYS_CHSTATUS_Type CHSTATUS
Offset: 0x007 (R/ 8) Channel n Status.
Definition: evsys.h:563
EVSYS_CHSTATUS_Type
Definition: evsys.h:518
EVSYS_SWEVT_Type::CHANNEL9
uint32_t CHANNEL9
Definition: evsys.h:73
EVSYS_BUSYCH_Type::BUSYCH4
uint32_t BUSYCH4
Definition: evsys.h:296
EVSYS_SWEVT_Type::CHANNEL27
uint32_t CHANNEL27
Definition: evsys.h:91
EVSYS_CTRLA_Type::reg
uint8_t reg
Definition: evsys.h:49
Evsys::BUSYCH
__I EVSYS_BUSYCH_Type BUSYCH
Offset: 0x018 (R/ 32) Busy Channels.
Definition: evsys.h:578
EVSYS_INTPEND_Type::BUSY
uint16_t BUSY
Definition: evsys.h:208
EVSYS_SWEVT_Type::CHANNEL
uint32_t CHANNEL
Definition: evsys.h:98
EVSYS_CHANNEL_Type::EVGEN
uint32_t EVGEN
Definition: evsys.h:408
EVSYS_SWEVT_Type::CHANNEL31
uint32_t CHANNEL31
Definition: evsys.h:95
EVSYS_READYUSR_Type::READYUSR2
uint32_t READYUSR2
Definition: evsys.h:352
EVSYS_INTSTATUS_Type::CHINT9
uint32_t CHINT9
Definition: evsys.h:243
EVSYS_READYUSR_Type::READYUSR11
uint32_t READYUSR11
Definition: evsys.h:361
EVSYS_SWEVT_Type::CHANNEL26
uint32_t CHANNEL26
Definition: evsys.h:90
EVSYS_CHANNEL_Type::EDGSEL
uint32_t EDGSEL
Definition: evsys.h:411
Evsys::CTRLA
__IO EVSYS_CTRLA_Type CTRLA
Offset: 0x000 (R/W 8) Control.
Definition: evsys.h:570
EVSYS_READYUSR_Type::READYUSR7
uint32_t READYUSR7
Definition: evsys.h:357
EVSYS_SWEVT_Type::CHANNEL29
uint32_t CHANNEL29
Definition: evsys.h:93
EVSYS_SWEVT_Type::CHANNEL8
uint32_t CHANNEL8
Definition: evsys.h:72
EVSYS_CHINTENSET_Type::EVD
uint8_t EVD
Definition: evsys.h:479
EVSYS_READYUSR_Type::reg
uint32_t reg
Definition: evsys.h:368
EVSYS_SWEVT_Type
Definition: evsys.h:62
EVSYS_BUSYCH_Type
Definition: evsys.h:290
EVSYS_SWEVT_Type::reg
uint32_t reg
Definition: evsys.h:100
EVSYS_INTSTATUS_Type::CHINT5
uint32_t CHINT5
Definition: evsys.h:239
EVSYS_BUSYCH_Type::BUSYCH8
uint32_t BUSYCH8
Definition: evsys.h:300
EVSYS_INTSTATUS_Type::CHINT11
uint32_t CHINT11
Definition: evsys.h:245
EVSYS_CHINTENSET_Type::reg
uint8_t reg
Definition: evsys.h:482
EVSYS_INTSTATUS_Type::CHINT2
uint32_t CHINT2
Definition: evsys.h:236
EVSYS_INTSTATUS_Type::reg
uint32_t reg
Definition: evsys.h:252
EVSYS_BUSYCH_Type::BUSYCH2
uint32_t BUSYCH2
Definition: evsys.h:294
EVSYS_PRICTRL_Type::reg
uint8_t reg
Definition: evsys.h:184
EvsysChannel
EvsysChannel hardware registers.
Definition: evsys.h:558
Evsys::READYUSR
__I EVSYS_READYUSR_Type READYUSR
Offset: 0x01C (R/ 32) Ready Users.
Definition: evsys.h:579
EVSYS_SWEVT_Type::CHANNEL11
uint32_t CHANNEL11
Definition: evsys.h:75
EVSYS_INTPEND_Type::OVR
uint16_t OVR
Definition: evsys.h:204
EVSYS_BUSYCH_Type::BUSYCH3
uint32_t BUSYCH3
Definition: evsys.h:295
EVSYS_READYUSR_Type::READYUSR
uint32_t READYUSR
Definition: evsys.h:365
EVSYS_CHINTFLAG_Type::OVR
__I uint8_t OVR
Definition: evsys.h:499
EVSYS_BUSYCH_Type::BUSYCH
uint32_t BUSYCH
Definition: evsys.h:307
EVSYS_SWEVT_Type::CHANNEL13
uint32_t CHANNEL13
Definition: evsys.h:77
EVSYS_CTRLA_Type
Definition: evsys.h:44
EVSYS_SWEVT_Type::CHANNEL17
uint32_t CHANNEL17
Definition: evsys.h:81
EVSYS_SWEVT_Type::CHANNEL30
uint32_t CHANNEL30
Definition: evsys.h:94
EVSYS_INTSTATUS_Type::CHINT3
uint32_t CHINT3
Definition: evsys.h:237
EVSYS_CHANNEL_Type::reg
uint32_t reg
Definition: evsys.h:417
EVSYS_READYUSR_Type
Definition: evsys.h:348
EVSYS_INTPEND_Type
Definition: evsys.h:200
EVSYS_PRICTRL_Type::RREN
uint8_t RREN
Definition: evsys.h:182
EVSYS_INTPEND_Type::READY
uint16_t READY
Definition: evsys.h:207
EVSYS_SWEVT_Type::CHANNEL7
uint32_t CHANNEL7
Definition: evsys.h:71
EVSYS_CHINTENSET_Type
Definition: evsys.h:476
EVSYS_BUSYCH_Type::BUSYCH11
uint32_t BUSYCH11
Definition: evsys.h:303
EVSYS_READYUSR_Type::READYUSR9
uint32_t READYUSR9
Definition: evsys.h:359
EVSYS_BUSYCH_Type::BUSYCH0
uint32_t BUSYCH0
Definition: evsys.h:292
EVSYS_USER_Type
Definition: evsys.h:539
Evsys::INTPEND
__IO EVSYS_INTPEND_Type INTPEND
Offset: 0x010 (R/W 16) Channel Pending Interrupt.
Definition: evsys.h:575
EVSYS_SWEVT_Type::CHANNEL2
uint32_t CHANNEL2
Definition: evsys.h:66
EVSYS_USER_Type::reg
uint32_t reg
Definition: evsys.h:544
EVSYS_PRICTRL_Type
Definition: evsys.h:178
EVSYS_INTSTATUS_Type::CHINT4
uint32_t CHINT4
Definition: evsys.h:238
EVSYS_SWEVT_Type::CHANNEL28
uint32_t CHANNEL28
Definition: evsys.h:92
EVSYS_SWEVT_Type::CHANNEL19
uint32_t CHANNEL19
Definition: evsys.h:83
EVSYS_CHANNEL_Type::RUNSTDBY
uint32_t RUNSTDBY
Definition: evsys.h:413
EVSYS_SWEVT_Type::CHANNEL18
uint32_t CHANNEL18
Definition: evsys.h:82
EVSYS_INTSTATUS_Type::CHINT10
uint32_t CHINT10
Definition: evsys.h:244
EvsysChannel::CHINTENSET
__IO EVSYS_CHINTENSET_Type CHINTENSET
Offset: 0x005 (R/W 8) Channel n Interrupt Enable Set.
Definition: evsys.h:561
EVSYS_BUSYCH_Type::BUSYCH7
uint32_t BUSYCH7
Definition: evsys.h:299
EVSYS_INTSTATUS_Type::CHINT1
uint32_t CHINT1
Definition: evsys.h:235
EVSYS_BUSYCH_Type::BUSYCH1
uint32_t BUSYCH1
Definition: evsys.h:293
EVSYS_SWEVT_Type::CHANNEL22
uint32_t CHANNEL22
Definition: evsys.h:86
EVSYS_INTPEND_Type::EVD
uint16_t EVD
Definition: evsys.h:205
EvsysChannel::CHINTFLAG
__IO EVSYS_CHINTFLAG_Type CHINTFLAG
Offset: 0x006 (R/W 8) Channel n Interrupt Flag Status and Clear.
Definition: evsys.h:562
EVSYS_CHINTENCLR_Type::EVD
uint8_t EVD
Definition: evsys.h:458
EVSYS_BUSYCH_Type::BUSYCH9
uint32_t BUSYCH9
Definition: evsys.h:301
Evsys::INTSTATUS
__I EVSYS_INTSTATUS_Type INTSTATUS
Offset: 0x014 (R/ 32) Interrupt Status.
Definition: evsys.h:577
EVSYS_CHINTFLAG_Type
Definition: evsys.h:497
Evsys
EVSYS hardware registers.
Definition: evsys.h:569
EVSYS_SWEVT_Type::CHANNEL12
uint32_t CHANNEL12
Definition: evsys.h:76
EVSYS_BUSYCH_Type::BUSYCH6
uint32_t BUSYCH6
Definition: evsys.h:298
EVSYS_SWEVT_Type::CHANNEL15
uint32_t CHANNEL15
Definition: evsys.h:79
EVSYS_SWEVT_Type::CHANNEL10
uint32_t CHANNEL10
Definition: evsys.h:74
EVSYS_SWEVT_Type::CHANNEL5
uint32_t CHANNEL5
Definition: evsys.h:69
EVSYS_BUSYCH_Type::BUSYCH10
uint32_t BUSYCH10
Definition: evsys.h:302
EVSYS_SWEVT_Type::CHANNEL3
uint32_t CHANNEL3
Definition: evsys.h:67
EVSYS_SWEVT_Type::CHANNEL16
uint32_t CHANNEL16
Definition: evsys.h:80
EVSYS_PRICTRL_Type::PRI
uint8_t PRI
Definition: evsys.h:180
EVSYS_READYUSR_Type::READYUSR1
uint32_t READYUSR1
Definition: evsys.h:351
EVSYS_READYUSR_Type::READYUSR0
uint32_t READYUSR0
Definition: evsys.h:350
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
Evsys::SWEVT
__O EVSYS_SWEVT_Type SWEVT
Offset: 0x004 ( /W 32) Software Event.
Definition: evsys.h:572
EVSYS_INTSTATUS_Type
Definition: evsys.h:232
EVSYS_INTSTATUS_Type::CHINT7
uint32_t CHINT7
Definition: evsys.h:241
EVSYS_SWEVT_Type::CHANNEL14
uint32_t CHANNEL14
Definition: evsys.h:78
EVSYS_SWEVT_Type::CHANNEL20
uint32_t CHANNEL20
Definition: evsys.h:84
EVSYS_INTPEND_Type::ID
uint16_t ID
Definition: evsys.h:202
EVSYS_CHINTFLAG_Type::uint8_t
__I uint8_t
Definition: evsys.h:501
EVSYS_CHINTFLAG_Type::EVD
__I uint8_t EVD
Definition: evsys.h:500
EVSYS_INTSTATUS_Type::CHINT0
uint32_t CHINT0
Definition: evsys.h:234
EVSYS_SWEVT_Type::CHANNEL6
uint32_t CHANNEL6
Definition: evsys.h:70
EVSYS_CHANNEL_Type::PATH
uint32_t PATH
Definition: evsys.h:410
EVSYS_CHANNEL_Type::ONDEMAND
uint32_t ONDEMAND
Definition: evsys.h:414
EVSYS_SWEVT_Type::CHANNEL0
uint32_t CHANNEL0
Definition: evsys.h:64
EvsysChannel::CHANNEL
__IO EVSYS_CHANNEL_Type CHANNEL
Offset: 0x000 (R/W 32) Channel n Control.
Definition: evsys.h:559
EVSYS_SWEVT_Type::CHANNEL1
uint32_t CHANNEL1
Definition: evsys.h:65
EVSYS_CTRLA_Type::SWRST
uint8_t SWRST
Definition: evsys.h:46
EVSYS_SWEVT_Type::CHANNEL25
uint32_t CHANNEL25
Definition: evsys.h:89
EVSYS_READYUSR_Type::READYUSR3
uint32_t READYUSR3
Definition: evsys.h:353
EVSYS_CHINTENCLR_Type::reg
uint8_t reg
Definition: evsys.h:461
EVSYS_SWEVT_Type::CHANNEL24
uint32_t CHANNEL24
Definition: evsys.h:88
EVSYS_USER_Type::CHANNEL
uint32_t CHANNEL
Definition: evsys.h:541
EVSYS_INTSTATUS_Type::CHINT6
uint32_t CHINT6
Definition: evsys.h:240
EVSYS_CHSTATUS_Type::BUSYCH
uint8_t BUSYCH
Definition: evsys.h:521
Evsys::PRICTRL
__IO EVSYS_PRICTRL_Type PRICTRL
Offset: 0x008 (R/W 8) Priority Control.
Definition: evsys.h:573