SAME54P20A Test Project
port.h
Go to the documentation of this file.
1 
30 #ifndef _SAME54_PORT_INSTANCE_
31 #define _SAME54_PORT_INSTANCE_
32 
33 /* ========== Register definition for PORT peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_PORT_DIR0 (0x41008000)
36 #define REG_PORT_DIRCLR0 (0x41008004)
37 #define REG_PORT_DIRSET0 (0x41008008)
38 #define REG_PORT_DIRTGL0 (0x4100800C)
39 #define REG_PORT_OUT0 (0x41008010)
40 #define REG_PORT_OUTCLR0 (0x41008014)
41 #define REG_PORT_OUTSET0 (0x41008018)
42 #define REG_PORT_OUTTGL0 (0x4100801C)
43 #define REG_PORT_IN0 (0x41008020)
44 #define REG_PORT_CTRL0 (0x41008024)
45 #define REG_PORT_WRCONFIG0 (0x41008028)
46 #define REG_PORT_EVCTRL0 (0x4100802C)
47 #define REG_PORT_PMUX0 (0x41008030)
48 #define REG_PORT_PINCFG0 (0x41008040)
49 #define REG_PORT_DIR1 (0x41008080)
50 #define REG_PORT_DIRCLR1 (0x41008084)
51 #define REG_PORT_DIRSET1 (0x41008088)
52 #define REG_PORT_DIRTGL1 (0x4100808C)
53 #define REG_PORT_OUT1 (0x41008090)
54 #define REG_PORT_OUTCLR1 (0x41008094)
55 #define REG_PORT_OUTSET1 (0x41008098)
56 #define REG_PORT_OUTTGL1 (0x4100809C)
57 #define REG_PORT_IN1 (0x410080A0)
58 #define REG_PORT_CTRL1 (0x410080A4)
59 #define REG_PORT_WRCONFIG1 (0x410080A8)
60 #define REG_PORT_EVCTRL1 (0x410080AC)
61 #define REG_PORT_PMUX1 (0x410080B0)
62 #define REG_PORT_PINCFG1 (0x410080C0)
63 #define REG_PORT_DIR2 (0x41008100)
64 #define REG_PORT_DIRCLR2 (0x41008104)
65 #define REG_PORT_DIRSET2 (0x41008108)
66 #define REG_PORT_DIRTGL2 (0x4100810C)
67 #define REG_PORT_OUT2 (0x41008110)
68 #define REG_PORT_OUTCLR2 (0x41008114)
69 #define REG_PORT_OUTSET2 (0x41008118)
70 #define REG_PORT_OUTTGL2 (0x4100811C)
71 #define REG_PORT_IN2 (0x41008120)
72 #define REG_PORT_CTRL2 (0x41008124)
73 #define REG_PORT_WRCONFIG2 (0x41008128)
74 #define REG_PORT_EVCTRL2 (0x4100812C)
75 #define REG_PORT_PMUX2 (0x41008130)
76 #define REG_PORT_PINCFG2 (0x41008140)
77 #define REG_PORT_DIR3 (0x41008180)
78 #define REG_PORT_DIRCLR3 (0x41008184)
79 #define REG_PORT_DIRSET3 (0x41008188)
80 #define REG_PORT_DIRTGL3 (0x4100818C)
81 #define REG_PORT_OUT3 (0x41008190)
82 #define REG_PORT_OUTCLR3 (0x41008194)
83 #define REG_PORT_OUTSET3 (0x41008198)
84 #define REG_PORT_OUTTGL3 (0x4100819C)
85 #define REG_PORT_IN3 (0x410081A0)
86 #define REG_PORT_CTRL3 (0x410081A4)
87 #define REG_PORT_WRCONFIG3 (0x410081A8)
88 #define REG_PORT_EVCTRL3 (0x410081AC)
89 #define REG_PORT_PMUX3 (0x410081B0)
90 #define REG_PORT_PINCFG3 (0x410081C0)
91 #else
92 #define REG_PORT_DIR0 (*(RwReg *)0x41008000UL)
93 #define REG_PORT_DIRCLR0 (*(RwReg *)0x41008004UL)
94 #define REG_PORT_DIRSET0 (*(RwReg *)0x41008008UL)
95 #define REG_PORT_DIRTGL0 (*(RwReg *)0x4100800CUL)
96 #define REG_PORT_OUT0 (*(RwReg *)0x41008010UL)
97 #define REG_PORT_OUTCLR0 (*(RwReg *)0x41008014UL)
98 #define REG_PORT_OUTSET0 (*(RwReg *)0x41008018UL)
99 #define REG_PORT_OUTTGL0 (*(RwReg *)0x4100801CUL)
100 #define REG_PORT_IN0 (*(RoReg *)0x41008020UL)
101 #define REG_PORT_CTRL0 (*(RwReg *)0x41008024UL)
102 #define REG_PORT_WRCONFIG0 (*(WoReg *)0x41008028UL)
103 #define REG_PORT_EVCTRL0 (*(RwReg *)0x4100802CUL)
104 #define REG_PORT_PMUX0 (*(RwReg8 *)0x41008030UL)
105 #define REG_PORT_PINCFG0 (*(RwReg8 *)0x41008040UL)
106 #define REG_PORT_DIR1 (*(RwReg *)0x41008080UL)
107 #define REG_PORT_DIRCLR1 (*(RwReg *)0x41008084UL)
108 #define REG_PORT_DIRSET1 (*(RwReg *)0x41008088UL)
109 #define REG_PORT_DIRTGL1 (*(RwReg *)0x4100808CUL)
110 #define REG_PORT_OUT1 (*(RwReg *)0x41008090UL)
111 #define REG_PORT_OUTCLR1 (*(RwReg *)0x41008094UL)
112 #define REG_PORT_OUTSET1 (*(RwReg *)0x41008098UL)
113 #define REG_PORT_OUTTGL1 (*(RwReg *)0x4100809CUL)
114 #define REG_PORT_IN1 (*(RoReg *)0x410080A0UL)
115 #define REG_PORT_CTRL1 (*(RwReg *)0x410080A4UL)
116 #define REG_PORT_WRCONFIG1 (*(WoReg *)0x410080A8UL)
117 #define REG_PORT_EVCTRL1 (*(RwReg *)0x410080ACUL)
118 #define REG_PORT_PMUX1 (*(RwReg8 *)0x410080B0UL)
119 #define REG_PORT_PINCFG1 (*(RwReg8 *)0x410080C0UL)
120 #define REG_PORT_DIR2 (*(RwReg *)0x41008100UL)
121 #define REG_PORT_DIRCLR2 (*(RwReg *)0x41008104UL)
122 #define REG_PORT_DIRSET2 (*(RwReg *)0x41008108UL)
123 #define REG_PORT_DIRTGL2 (*(RwReg *)0x4100810CUL)
124 #define REG_PORT_OUT2 (*(RwReg *)0x41008110UL)
125 #define REG_PORT_OUTCLR2 (*(RwReg *)0x41008114UL)
126 #define REG_PORT_OUTSET2 (*(RwReg *)0x41008118UL)
127 #define REG_PORT_OUTTGL2 (*(RwReg *)0x4100811CUL)
128 #define REG_PORT_IN2 (*(RoReg *)0x41008120UL)
129 #define REG_PORT_CTRL2 (*(RwReg *)0x41008124UL)
130 #define REG_PORT_WRCONFIG2 (*(WoReg *)0x41008128UL)
131 #define REG_PORT_EVCTRL2 (*(RwReg *)0x4100812CUL)
132 #define REG_PORT_PMUX2 (*(RwReg8 *)0x41008130UL)
133 #define REG_PORT_PINCFG2 (*(RwReg8 *)0x41008140UL)
134 #define REG_PORT_DIR3 (*(RwReg *)0x41008180UL)
135 #define REG_PORT_DIRCLR3 (*(RwReg *)0x41008184UL)
136 #define REG_PORT_DIRSET3 (*(RwReg *)0x41008188UL)
137 #define REG_PORT_DIRTGL3 (*(RwReg *)0x4100818CUL)
138 #define REG_PORT_OUT3 (*(RwReg *)0x41008190UL)
139 #define REG_PORT_OUTCLR3 (*(RwReg *)0x41008194UL)
140 #define REG_PORT_OUTSET3 (*(RwReg *)0x41008198UL)
141 #define REG_PORT_OUTTGL3 (*(RwReg *)0x4100819CUL)
142 #define REG_PORT_IN3 (*(RoReg *)0x410081A0UL)
143 #define REG_PORT_CTRL3 (*(RwReg *)0x410081A4UL)
144 #define REG_PORT_WRCONFIG3 (*(WoReg *)0x410081A8UL)
145 #define REG_PORT_EVCTRL3 (*(RwReg *)0x410081ACUL)
146 #define REG_PORT_PMUX3 (*(RwReg8 *)0x410081B0UL)
147 #define REG_PORT_PINCFG3 (*(RwReg8 *)0x410081C0UL)
148 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
149 
150 /* ========== Instance parameters for PORT peripheral ========== */
151 #define PORT_BITS 118
152 #define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
153 #define PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
154 #define PORT_DRVSTR 1 // DRVSTR supported
155 #define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
156 #define PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
157 #define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
158 #define PORT_EV_NUM 4
159 #define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
160 #define PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
161 #define PORT_ODRAIN 0 // ODRAIN supported
162 #define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
163 #define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
164 #define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
165 #define PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
166 #define PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
167 #define PORT_PMUXBIT0_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
168 #define PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }
169 #define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
170 #define PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }
171 #define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
172 #define PORT_PMUXBIT2_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }
173 #define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
174 #define PORT_PMUXBIT3_IMPLEMENTED { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }
175 #define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }
176 #define PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
177 #define PORT_PPP_IMPLEMENTED { 0x00000001 } // IOBUS2 implemented?
178 #define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
179 #define PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }
180 #define PORT_SLEWLIM 0 // SLEWLIM supported
181 #define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
182 #define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
183 
184 #endif /* _SAME54_PORT_INSTANCE_ */