SAME54P20A Test Project
dmac.h
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1 
30 #ifndef _SAME54_DMAC_INSTANCE_
31 #define _SAME54_DMAC_INSTANCE_
32 
33 /* ========== Register definition for DMAC peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_DMAC_CTRL (0x4100A000)
36 #define REG_DMAC_CRCCTRL (0x4100A002)
37 #define REG_DMAC_CRCDATAIN (0x4100A004)
38 #define REG_DMAC_CRCCHKSUM (0x4100A008)
39 #define REG_DMAC_CRCSTATUS (0x4100A00C)
40 #define REG_DMAC_DBGCTRL (0x4100A00D)
41 #define REG_DMAC_SWTRIGCTRL (0x4100A010)
42 #define REG_DMAC_PRICTRL0 (0x4100A014)
43 #define REG_DMAC_INTPEND (0x4100A020)
44 #define REG_DMAC_INTSTATUS (0x4100A024)
45 #define REG_DMAC_BUSYCH (0x4100A028)
46 #define REG_DMAC_PENDCH (0x4100A02C)
47 #define REG_DMAC_ACTIVE (0x4100A030)
48 #define REG_DMAC_BASEADDR (0x4100A034)
49 #define REG_DMAC_WRBADDR (0x4100A038)
50 #define REG_DMAC_CHCTRLA0 (0x4100A040)
51 #define REG_DMAC_CHCTRLB0 (0x4100A044)
52 #define REG_DMAC_CHPRILVL0 (0x4100A045)
53 #define REG_DMAC_CHEVCTRL0 (0x4100A046)
54 #define REG_DMAC_CHINTENCLR0 (0x4100A04C)
55 #define REG_DMAC_CHINTENSET0 (0x4100A04D)
56 #define REG_DMAC_CHINTFLAG0 (0x4100A04E)
57 #define REG_DMAC_CHSTATUS0 (0x4100A04F)
58 #define REG_DMAC_CHCTRLA1 (0x4100A050)
59 #define REG_DMAC_CHCTRLB1 (0x4100A054)
60 #define REG_DMAC_CHPRILVL1 (0x4100A055)
61 #define REG_DMAC_CHEVCTRL1 (0x4100A056)
62 #define REG_DMAC_CHINTENCLR1 (0x4100A05C)
63 #define REG_DMAC_CHINTENSET1 (0x4100A05D)
64 #define REG_DMAC_CHINTFLAG1 (0x4100A05E)
65 #define REG_DMAC_CHSTATUS1 (0x4100A05F)
66 #define REG_DMAC_CHCTRLA2 (0x4100A060)
67 #define REG_DMAC_CHCTRLB2 (0x4100A064)
68 #define REG_DMAC_CHPRILVL2 (0x4100A065)
69 #define REG_DMAC_CHEVCTRL2 (0x4100A066)
70 #define REG_DMAC_CHINTENCLR2 (0x4100A06C)
71 #define REG_DMAC_CHINTENSET2 (0x4100A06D)
72 #define REG_DMAC_CHINTFLAG2 (0x4100A06E)
73 #define REG_DMAC_CHSTATUS2 (0x4100A06F)
74 #define REG_DMAC_CHCTRLA3 (0x4100A070)
75 #define REG_DMAC_CHCTRLB3 (0x4100A074)
76 #define REG_DMAC_CHPRILVL3 (0x4100A075)
77 #define REG_DMAC_CHEVCTRL3 (0x4100A076)
78 #define REG_DMAC_CHINTENCLR3 (0x4100A07C)
79 #define REG_DMAC_CHINTENSET3 (0x4100A07D)
80 #define REG_DMAC_CHINTFLAG3 (0x4100A07E)
81 #define REG_DMAC_CHSTATUS3 (0x4100A07F)
82 #define REG_DMAC_CHCTRLA4 (0x4100A080)
83 #define REG_DMAC_CHCTRLB4 (0x4100A084)
84 #define REG_DMAC_CHPRILVL4 (0x4100A085)
85 #define REG_DMAC_CHEVCTRL4 (0x4100A086)
86 #define REG_DMAC_CHINTENCLR4 (0x4100A08C)
87 #define REG_DMAC_CHINTENSET4 (0x4100A08D)
88 #define REG_DMAC_CHINTFLAG4 (0x4100A08E)
89 #define REG_DMAC_CHSTATUS4 (0x4100A08F)
90 #define REG_DMAC_CHCTRLA5 (0x4100A090)
91 #define REG_DMAC_CHCTRLB5 (0x4100A094)
92 #define REG_DMAC_CHPRILVL5 (0x4100A095)
93 #define REG_DMAC_CHEVCTRL5 (0x4100A096)
94 #define REG_DMAC_CHINTENCLR5 (0x4100A09C)
95 #define REG_DMAC_CHINTENSET5 (0x4100A09D)
96 #define REG_DMAC_CHINTFLAG5 (0x4100A09E)
97 #define REG_DMAC_CHSTATUS5 (0x4100A09F)
98 #define REG_DMAC_CHCTRLA6 (0x4100A0A0)
99 #define REG_DMAC_CHCTRLB6 (0x4100A0A4)
100 #define REG_DMAC_CHPRILVL6 (0x4100A0A5)
101 #define REG_DMAC_CHEVCTRL6 (0x4100A0A6)
102 #define REG_DMAC_CHINTENCLR6 (0x4100A0AC)
103 #define REG_DMAC_CHINTENSET6 (0x4100A0AD)
104 #define REG_DMAC_CHINTFLAG6 (0x4100A0AE)
105 #define REG_DMAC_CHSTATUS6 (0x4100A0AF)
106 #define REG_DMAC_CHCTRLA7 (0x4100A0B0)
107 #define REG_DMAC_CHCTRLB7 (0x4100A0B4)
108 #define REG_DMAC_CHPRILVL7 (0x4100A0B5)
109 #define REG_DMAC_CHEVCTRL7 (0x4100A0B6)
110 #define REG_DMAC_CHINTENCLR7 (0x4100A0BC)
111 #define REG_DMAC_CHINTENSET7 (0x4100A0BD)
112 #define REG_DMAC_CHINTFLAG7 (0x4100A0BE)
113 #define REG_DMAC_CHSTATUS7 (0x4100A0BF)
114 #define REG_DMAC_CHCTRLA8 (0x4100A0C0)
115 #define REG_DMAC_CHCTRLB8 (0x4100A0C4)
116 #define REG_DMAC_CHPRILVL8 (0x4100A0C5)
117 #define REG_DMAC_CHEVCTRL8 (0x4100A0C6)
118 #define REG_DMAC_CHINTENCLR8 (0x4100A0CC)
119 #define REG_DMAC_CHINTENSET8 (0x4100A0CD)
120 #define REG_DMAC_CHINTFLAG8 (0x4100A0CE)
121 #define REG_DMAC_CHSTATUS8 (0x4100A0CF)
122 #define REG_DMAC_CHCTRLA9 (0x4100A0D0)
123 #define REG_DMAC_CHCTRLB9 (0x4100A0D4)
124 #define REG_DMAC_CHPRILVL9 (0x4100A0D5)
125 #define REG_DMAC_CHEVCTRL9 (0x4100A0D6)
126 #define REG_DMAC_CHINTENCLR9 (0x4100A0DC)
127 #define REG_DMAC_CHINTENSET9 (0x4100A0DD)
128 #define REG_DMAC_CHINTFLAG9 (0x4100A0DE)
129 #define REG_DMAC_CHSTATUS9 (0x4100A0DF)
130 #define REG_DMAC_CHCTRLA10 (0x4100A0E0)
131 #define REG_DMAC_CHCTRLB10 (0x4100A0E4)
132 #define REG_DMAC_CHPRILVL10 (0x4100A0E5)
133 #define REG_DMAC_CHEVCTRL10 (0x4100A0E6)
134 #define REG_DMAC_CHINTENCLR10 (0x4100A0EC)
135 #define REG_DMAC_CHINTENSET10 (0x4100A0ED)
136 #define REG_DMAC_CHINTFLAG10 (0x4100A0EE)
137 #define REG_DMAC_CHSTATUS10 (0x4100A0EF)
138 #define REG_DMAC_CHCTRLA11 (0x4100A0F0)
139 #define REG_DMAC_CHCTRLB11 (0x4100A0F4)
140 #define REG_DMAC_CHPRILVL11 (0x4100A0F5)
141 #define REG_DMAC_CHEVCTRL11 (0x4100A0F6)
142 #define REG_DMAC_CHINTENCLR11 (0x4100A0FC)
143 #define REG_DMAC_CHINTENSET11 (0x4100A0FD)
144 #define REG_DMAC_CHINTFLAG11 (0x4100A0FE)
145 #define REG_DMAC_CHSTATUS11 (0x4100A0FF)
146 #define REG_DMAC_CHCTRLA12 (0x4100A100)
147 #define REG_DMAC_CHCTRLB12 (0x4100A104)
148 #define REG_DMAC_CHPRILVL12 (0x4100A105)
149 #define REG_DMAC_CHEVCTRL12 (0x4100A106)
150 #define REG_DMAC_CHINTENCLR12 (0x4100A10C)
151 #define REG_DMAC_CHINTENSET12 (0x4100A10D)
152 #define REG_DMAC_CHINTFLAG12 (0x4100A10E)
153 #define REG_DMAC_CHSTATUS12 (0x4100A10F)
154 #define REG_DMAC_CHCTRLA13 (0x4100A110)
155 #define REG_DMAC_CHCTRLB13 (0x4100A114)
156 #define REG_DMAC_CHPRILVL13 (0x4100A115)
157 #define REG_DMAC_CHEVCTRL13 (0x4100A116)
158 #define REG_DMAC_CHINTENCLR13 (0x4100A11C)
159 #define REG_DMAC_CHINTENSET13 (0x4100A11D)
160 #define REG_DMAC_CHINTFLAG13 (0x4100A11E)
161 #define REG_DMAC_CHSTATUS13 (0x4100A11F)
162 #define REG_DMAC_CHCTRLA14 (0x4100A120)
163 #define REG_DMAC_CHCTRLB14 (0x4100A124)
164 #define REG_DMAC_CHPRILVL14 (0x4100A125)
165 #define REG_DMAC_CHEVCTRL14 (0x4100A126)
166 #define REG_DMAC_CHINTENCLR14 (0x4100A12C)
167 #define REG_DMAC_CHINTENSET14 (0x4100A12D)
168 #define REG_DMAC_CHINTFLAG14 (0x4100A12E)
169 #define REG_DMAC_CHSTATUS14 (0x4100A12F)
170 #define REG_DMAC_CHCTRLA15 (0x4100A130)
171 #define REG_DMAC_CHCTRLB15 (0x4100A134)
172 #define REG_DMAC_CHPRILVL15 (0x4100A135)
173 #define REG_DMAC_CHEVCTRL15 (0x4100A136)
174 #define REG_DMAC_CHINTENCLR15 (0x4100A13C)
175 #define REG_DMAC_CHINTENSET15 (0x4100A13D)
176 #define REG_DMAC_CHINTFLAG15 (0x4100A13E)
177 #define REG_DMAC_CHSTATUS15 (0x4100A13F)
178 #define REG_DMAC_CHCTRLA16 (0x4100A140)
179 #define REG_DMAC_CHCTRLB16 (0x4100A144)
180 #define REG_DMAC_CHPRILVL16 (0x4100A145)
181 #define REG_DMAC_CHEVCTRL16 (0x4100A146)
182 #define REG_DMAC_CHINTENCLR16 (0x4100A14C)
183 #define REG_DMAC_CHINTENSET16 (0x4100A14D)
184 #define REG_DMAC_CHINTFLAG16 (0x4100A14E)
185 #define REG_DMAC_CHSTATUS16 (0x4100A14F)
186 #define REG_DMAC_CHCTRLA17 (0x4100A150)
187 #define REG_DMAC_CHCTRLB17 (0x4100A154)
188 #define REG_DMAC_CHPRILVL17 (0x4100A155)
189 #define REG_DMAC_CHEVCTRL17 (0x4100A156)
190 #define REG_DMAC_CHINTENCLR17 (0x4100A15C)
191 #define REG_DMAC_CHINTENSET17 (0x4100A15D)
192 #define REG_DMAC_CHINTFLAG17 (0x4100A15E)
193 #define REG_DMAC_CHSTATUS17 (0x4100A15F)
194 #define REG_DMAC_CHCTRLA18 (0x4100A160)
195 #define REG_DMAC_CHCTRLB18 (0x4100A164)
196 #define REG_DMAC_CHPRILVL18 (0x4100A165)
197 #define REG_DMAC_CHEVCTRL18 (0x4100A166)
198 #define REG_DMAC_CHINTENCLR18 (0x4100A16C)
199 #define REG_DMAC_CHINTENSET18 (0x4100A16D)
200 #define REG_DMAC_CHINTFLAG18 (0x4100A16E)
201 #define REG_DMAC_CHSTATUS18 (0x4100A16F)
202 #define REG_DMAC_CHCTRLA19 (0x4100A170)
203 #define REG_DMAC_CHCTRLB19 (0x4100A174)
204 #define REG_DMAC_CHPRILVL19 (0x4100A175)
205 #define REG_DMAC_CHEVCTRL19 (0x4100A176)
206 #define REG_DMAC_CHINTENCLR19 (0x4100A17C)
207 #define REG_DMAC_CHINTENSET19 (0x4100A17D)
208 #define REG_DMAC_CHINTFLAG19 (0x4100A17E)
209 #define REG_DMAC_CHSTATUS19 (0x4100A17F)
210 #define REG_DMAC_CHCTRLA20 (0x4100A180)
211 #define REG_DMAC_CHCTRLB20 (0x4100A184)
212 #define REG_DMAC_CHPRILVL20 (0x4100A185)
213 #define REG_DMAC_CHEVCTRL20 (0x4100A186)
214 #define REG_DMAC_CHINTENCLR20 (0x4100A18C)
215 #define REG_DMAC_CHINTENSET20 (0x4100A18D)
216 #define REG_DMAC_CHINTFLAG20 (0x4100A18E)
217 #define REG_DMAC_CHSTATUS20 (0x4100A18F)
218 #define REG_DMAC_CHCTRLA21 (0x4100A190)
219 #define REG_DMAC_CHCTRLB21 (0x4100A194)
220 #define REG_DMAC_CHPRILVL21 (0x4100A195)
221 #define REG_DMAC_CHEVCTRL21 (0x4100A196)
222 #define REG_DMAC_CHINTENCLR21 (0x4100A19C)
223 #define REG_DMAC_CHINTENSET21 (0x4100A19D)
224 #define REG_DMAC_CHINTFLAG21 (0x4100A19E)
225 #define REG_DMAC_CHSTATUS21 (0x4100A19F)
226 #define REG_DMAC_CHCTRLA22 (0x4100A1A0)
227 #define REG_DMAC_CHCTRLB22 (0x4100A1A4)
228 #define REG_DMAC_CHPRILVL22 (0x4100A1A5)
229 #define REG_DMAC_CHEVCTRL22 (0x4100A1A6)
230 #define REG_DMAC_CHINTENCLR22 (0x4100A1AC)
231 #define REG_DMAC_CHINTENSET22 (0x4100A1AD)
232 #define REG_DMAC_CHINTFLAG22 (0x4100A1AE)
233 #define REG_DMAC_CHSTATUS22 (0x4100A1AF)
234 #define REG_DMAC_CHCTRLA23 (0x4100A1B0)
235 #define REG_DMAC_CHCTRLB23 (0x4100A1B4)
236 #define REG_DMAC_CHPRILVL23 (0x4100A1B5)
237 #define REG_DMAC_CHEVCTRL23 (0x4100A1B6)
238 #define REG_DMAC_CHINTENCLR23 (0x4100A1BC)
239 #define REG_DMAC_CHINTENSET23 (0x4100A1BD)
240 #define REG_DMAC_CHINTFLAG23 (0x4100A1BE)
241 #define REG_DMAC_CHSTATUS23 (0x4100A1BF)
242 #define REG_DMAC_CHCTRLA24 (0x4100A1C0)
243 #define REG_DMAC_CHCTRLB24 (0x4100A1C4)
244 #define REG_DMAC_CHPRILVL24 (0x4100A1C5)
245 #define REG_DMAC_CHEVCTRL24 (0x4100A1C6)
246 #define REG_DMAC_CHINTENCLR24 (0x4100A1CC)
247 #define REG_DMAC_CHINTENSET24 (0x4100A1CD)
248 #define REG_DMAC_CHINTFLAG24 (0x4100A1CE)
249 #define REG_DMAC_CHSTATUS24 (0x4100A1CF)
250 #define REG_DMAC_CHCTRLA25 (0x4100A1D0)
251 #define REG_DMAC_CHCTRLB25 (0x4100A1D4)
252 #define REG_DMAC_CHPRILVL25 (0x4100A1D5)
253 #define REG_DMAC_CHEVCTRL25 (0x4100A1D6)
254 #define REG_DMAC_CHINTENCLR25 (0x4100A1DC)
255 #define REG_DMAC_CHINTENSET25 (0x4100A1DD)
256 #define REG_DMAC_CHINTFLAG25 (0x4100A1DE)
257 #define REG_DMAC_CHSTATUS25 (0x4100A1DF)
258 #define REG_DMAC_CHCTRLA26 (0x4100A1E0)
259 #define REG_DMAC_CHCTRLB26 (0x4100A1E4)
260 #define REG_DMAC_CHPRILVL26 (0x4100A1E5)
261 #define REG_DMAC_CHEVCTRL26 (0x4100A1E6)
262 #define REG_DMAC_CHINTENCLR26 (0x4100A1EC)
263 #define REG_DMAC_CHINTENSET26 (0x4100A1ED)
264 #define REG_DMAC_CHINTFLAG26 (0x4100A1EE)
265 #define REG_DMAC_CHSTATUS26 (0x4100A1EF)
266 #define REG_DMAC_CHCTRLA27 (0x4100A1F0)
267 #define REG_DMAC_CHCTRLB27 (0x4100A1F4)
268 #define REG_DMAC_CHPRILVL27 (0x4100A1F5)
269 #define REG_DMAC_CHEVCTRL27 (0x4100A1F6)
270 #define REG_DMAC_CHINTENCLR27 (0x4100A1FC)
271 #define REG_DMAC_CHINTENSET27 (0x4100A1FD)
272 #define REG_DMAC_CHINTFLAG27 (0x4100A1FE)
273 #define REG_DMAC_CHSTATUS27 (0x4100A1FF)
274 #define REG_DMAC_CHCTRLA28 (0x4100A200)
275 #define REG_DMAC_CHCTRLB28 (0x4100A204)
276 #define REG_DMAC_CHPRILVL28 (0x4100A205)
277 #define REG_DMAC_CHEVCTRL28 (0x4100A206)
278 #define REG_DMAC_CHINTENCLR28 (0x4100A20C)
279 #define REG_DMAC_CHINTENSET28 (0x4100A20D)
280 #define REG_DMAC_CHINTFLAG28 (0x4100A20E)
281 #define REG_DMAC_CHSTATUS28 (0x4100A20F)
282 #define REG_DMAC_CHCTRLA29 (0x4100A210)
283 #define REG_DMAC_CHCTRLB29 (0x4100A214)
284 #define REG_DMAC_CHPRILVL29 (0x4100A215)
285 #define REG_DMAC_CHEVCTRL29 (0x4100A216)
286 #define REG_DMAC_CHINTENCLR29 (0x4100A21C)
287 #define REG_DMAC_CHINTENSET29 (0x4100A21D)
288 #define REG_DMAC_CHINTFLAG29 (0x4100A21E)
289 #define REG_DMAC_CHSTATUS29 (0x4100A21F)
290 #define REG_DMAC_CHCTRLA30 (0x4100A220)
291 #define REG_DMAC_CHCTRLB30 (0x4100A224)
292 #define REG_DMAC_CHPRILVL30 (0x4100A225)
293 #define REG_DMAC_CHEVCTRL30 (0x4100A226)
294 #define REG_DMAC_CHINTENCLR30 (0x4100A22C)
295 #define REG_DMAC_CHINTENSET30 (0x4100A22D)
296 #define REG_DMAC_CHINTFLAG30 (0x4100A22E)
297 #define REG_DMAC_CHSTATUS30 (0x4100A22F)
298 #define REG_DMAC_CHCTRLA31 (0x4100A230)
299 #define REG_DMAC_CHCTRLB31 (0x4100A234)
300 #define REG_DMAC_CHPRILVL31 (0x4100A235)
301 #define REG_DMAC_CHEVCTRL31 (0x4100A236)
302 #define REG_DMAC_CHINTENCLR31 (0x4100A23C)
303 #define REG_DMAC_CHINTENSET31 (0x4100A23D)
304 #define REG_DMAC_CHINTFLAG31 (0x4100A23E)
305 #define REG_DMAC_CHSTATUS31 (0x4100A23F)
306 #else
307 #define REG_DMAC_CTRL (*(RwReg16*)0x4100A000UL)
308 #define REG_DMAC_CRCCTRL (*(RwReg16*)0x4100A002UL)
309 #define REG_DMAC_CRCDATAIN (*(RwReg *)0x4100A004UL)
310 #define REG_DMAC_CRCCHKSUM (*(RwReg *)0x4100A008UL)
311 #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100A00CUL)
312 #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100A00DUL)
313 #define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x4100A010UL)
314 #define REG_DMAC_PRICTRL0 (*(RwReg *)0x4100A014UL)
315 #define REG_DMAC_INTPEND (*(RwReg16*)0x4100A020UL)
316 #define REG_DMAC_INTSTATUS (*(RoReg *)0x4100A024UL)
317 #define REG_DMAC_BUSYCH (*(RoReg *)0x4100A028UL)
318 #define REG_DMAC_PENDCH (*(RoReg *)0x4100A02CUL)
319 #define REG_DMAC_ACTIVE (*(RoReg *)0x4100A030UL)
320 #define REG_DMAC_BASEADDR (*(RwReg *)0x4100A034UL)
321 #define REG_DMAC_WRBADDR (*(RwReg *)0x4100A038UL)
322 #define REG_DMAC_CHCTRLA0 (*(RwReg *)0x4100A040UL)
323 #define REG_DMAC_CHCTRLB0 (*(RwReg8 *)0x4100A044UL)
324 #define REG_DMAC_CHPRILVL0 (*(RwReg8 *)0x4100A045UL)
325 #define REG_DMAC_CHEVCTRL0 (*(RwReg8 *)0x4100A046UL)
326 #define REG_DMAC_CHINTENCLR0 (*(RwReg8 *)0x4100A04CUL)
327 #define REG_DMAC_CHINTENSET0 (*(RwReg8 *)0x4100A04DUL)
328 #define REG_DMAC_CHINTFLAG0 (*(RwReg8 *)0x4100A04EUL)
329 #define REG_DMAC_CHSTATUS0 (*(RwReg8 *)0x4100A04FUL)
330 #define REG_DMAC_CHCTRLA1 (*(RwReg *)0x4100A050UL)
331 #define REG_DMAC_CHCTRLB1 (*(RwReg8 *)0x4100A054UL)
332 #define REG_DMAC_CHPRILVL1 (*(RwReg8 *)0x4100A055UL)
333 #define REG_DMAC_CHEVCTRL1 (*(RwReg8 *)0x4100A056UL)
334 #define REG_DMAC_CHINTENCLR1 (*(RwReg8 *)0x4100A05CUL)
335 #define REG_DMAC_CHINTENSET1 (*(RwReg8 *)0x4100A05DUL)
336 #define REG_DMAC_CHINTFLAG1 (*(RwReg8 *)0x4100A05EUL)
337 #define REG_DMAC_CHSTATUS1 (*(RwReg8 *)0x4100A05FUL)
338 #define REG_DMAC_CHCTRLA2 (*(RwReg *)0x4100A060UL)
339 #define REG_DMAC_CHCTRLB2 (*(RwReg8 *)0x4100A064UL)
340 #define REG_DMAC_CHPRILVL2 (*(RwReg8 *)0x4100A065UL)
341 #define REG_DMAC_CHEVCTRL2 (*(RwReg8 *)0x4100A066UL)
342 #define REG_DMAC_CHINTENCLR2 (*(RwReg8 *)0x4100A06CUL)
343 #define REG_DMAC_CHINTENSET2 (*(RwReg8 *)0x4100A06DUL)
344 #define REG_DMAC_CHINTFLAG2 (*(RwReg8 *)0x4100A06EUL)
345 #define REG_DMAC_CHSTATUS2 (*(RwReg8 *)0x4100A06FUL)
346 #define REG_DMAC_CHCTRLA3 (*(RwReg *)0x4100A070UL)
347 #define REG_DMAC_CHCTRLB3 (*(RwReg8 *)0x4100A074UL)
348 #define REG_DMAC_CHPRILVL3 (*(RwReg8 *)0x4100A075UL)
349 #define REG_DMAC_CHEVCTRL3 (*(RwReg8 *)0x4100A076UL)
350 #define REG_DMAC_CHINTENCLR3 (*(RwReg8 *)0x4100A07CUL)
351 #define REG_DMAC_CHINTENSET3 (*(RwReg8 *)0x4100A07DUL)
352 #define REG_DMAC_CHINTFLAG3 (*(RwReg8 *)0x4100A07EUL)
353 #define REG_DMAC_CHSTATUS3 (*(RwReg8 *)0x4100A07FUL)
354 #define REG_DMAC_CHCTRLA4 (*(RwReg *)0x4100A080UL)
355 #define REG_DMAC_CHCTRLB4 (*(RwReg8 *)0x4100A084UL)
356 #define REG_DMAC_CHPRILVL4 (*(RwReg8 *)0x4100A085UL)
357 #define REG_DMAC_CHEVCTRL4 (*(RwReg8 *)0x4100A086UL)
358 #define REG_DMAC_CHINTENCLR4 (*(RwReg8 *)0x4100A08CUL)
359 #define REG_DMAC_CHINTENSET4 (*(RwReg8 *)0x4100A08DUL)
360 #define REG_DMAC_CHINTFLAG4 (*(RwReg8 *)0x4100A08EUL)
361 #define REG_DMAC_CHSTATUS4 (*(RwReg8 *)0x4100A08FUL)
362 #define REG_DMAC_CHCTRLA5 (*(RwReg *)0x4100A090UL)
363 #define REG_DMAC_CHCTRLB5 (*(RwReg8 *)0x4100A094UL)
364 #define REG_DMAC_CHPRILVL5 (*(RwReg8 *)0x4100A095UL)
365 #define REG_DMAC_CHEVCTRL5 (*(RwReg8 *)0x4100A096UL)
366 #define REG_DMAC_CHINTENCLR5 (*(RwReg8 *)0x4100A09CUL)
367 #define REG_DMAC_CHINTENSET5 (*(RwReg8 *)0x4100A09DUL)
368 #define REG_DMAC_CHINTFLAG5 (*(RwReg8 *)0x4100A09EUL)
369 #define REG_DMAC_CHSTATUS5 (*(RwReg8 *)0x4100A09FUL)
370 #define REG_DMAC_CHCTRLA6 (*(RwReg *)0x4100A0A0UL)
371 #define REG_DMAC_CHCTRLB6 (*(RwReg8 *)0x4100A0A4UL)
372 #define REG_DMAC_CHPRILVL6 (*(RwReg8 *)0x4100A0A5UL)
373 #define REG_DMAC_CHEVCTRL6 (*(RwReg8 *)0x4100A0A6UL)
374 #define REG_DMAC_CHINTENCLR6 (*(RwReg8 *)0x4100A0ACUL)
375 #define REG_DMAC_CHINTENSET6 (*(RwReg8 *)0x4100A0ADUL)
376 #define REG_DMAC_CHINTFLAG6 (*(RwReg8 *)0x4100A0AEUL)
377 #define REG_DMAC_CHSTATUS6 (*(RwReg8 *)0x4100A0AFUL)
378 #define REG_DMAC_CHCTRLA7 (*(RwReg *)0x4100A0B0UL)
379 #define REG_DMAC_CHCTRLB7 (*(RwReg8 *)0x4100A0B4UL)
380 #define REG_DMAC_CHPRILVL7 (*(RwReg8 *)0x4100A0B5UL)
381 #define REG_DMAC_CHEVCTRL7 (*(RwReg8 *)0x4100A0B6UL)
382 #define REG_DMAC_CHINTENCLR7 (*(RwReg8 *)0x4100A0BCUL)
383 #define REG_DMAC_CHINTENSET7 (*(RwReg8 *)0x4100A0BDUL)
384 #define REG_DMAC_CHINTFLAG7 (*(RwReg8 *)0x4100A0BEUL)
385 #define REG_DMAC_CHSTATUS7 (*(RwReg8 *)0x4100A0BFUL)
386 #define REG_DMAC_CHCTRLA8 (*(RwReg *)0x4100A0C0UL)
387 #define REG_DMAC_CHCTRLB8 (*(RwReg8 *)0x4100A0C4UL)
388 #define REG_DMAC_CHPRILVL8 (*(RwReg8 *)0x4100A0C5UL)
389 #define REG_DMAC_CHEVCTRL8 (*(RwReg8 *)0x4100A0C6UL)
390 #define REG_DMAC_CHINTENCLR8 (*(RwReg8 *)0x4100A0CCUL)
391 #define REG_DMAC_CHINTENSET8 (*(RwReg8 *)0x4100A0CDUL)
392 #define REG_DMAC_CHINTFLAG8 (*(RwReg8 *)0x4100A0CEUL)
393 #define REG_DMAC_CHSTATUS8 (*(RwReg8 *)0x4100A0CFUL)
394 #define REG_DMAC_CHCTRLA9 (*(RwReg *)0x4100A0D0UL)
395 #define REG_DMAC_CHCTRLB9 (*(RwReg8 *)0x4100A0D4UL)
396 #define REG_DMAC_CHPRILVL9 (*(RwReg8 *)0x4100A0D5UL)
397 #define REG_DMAC_CHEVCTRL9 (*(RwReg8 *)0x4100A0D6UL)
398 #define REG_DMAC_CHINTENCLR9 (*(RwReg8 *)0x4100A0DCUL)
399 #define REG_DMAC_CHINTENSET9 (*(RwReg8 *)0x4100A0DDUL)
400 #define REG_DMAC_CHINTFLAG9 (*(RwReg8 *)0x4100A0DEUL)
401 #define REG_DMAC_CHSTATUS9 (*(RwReg8 *)0x4100A0DFUL)
402 #define REG_DMAC_CHCTRLA10 (*(RwReg *)0x4100A0E0UL)
403 #define REG_DMAC_CHCTRLB10 (*(RwReg8 *)0x4100A0E4UL)
404 #define REG_DMAC_CHPRILVL10 (*(RwReg8 *)0x4100A0E5UL)
405 #define REG_DMAC_CHEVCTRL10 (*(RwReg8 *)0x4100A0E6UL)
406 #define REG_DMAC_CHINTENCLR10 (*(RwReg8 *)0x4100A0ECUL)
407 #define REG_DMAC_CHINTENSET10 (*(RwReg8 *)0x4100A0EDUL)
408 #define REG_DMAC_CHINTFLAG10 (*(RwReg8 *)0x4100A0EEUL)
409 #define REG_DMAC_CHSTATUS10 (*(RwReg8 *)0x4100A0EFUL)
410 #define REG_DMAC_CHCTRLA11 (*(RwReg *)0x4100A0F0UL)
411 #define REG_DMAC_CHCTRLB11 (*(RwReg8 *)0x4100A0F4UL)
412 #define REG_DMAC_CHPRILVL11 (*(RwReg8 *)0x4100A0F5UL)
413 #define REG_DMAC_CHEVCTRL11 (*(RwReg8 *)0x4100A0F6UL)
414 #define REG_DMAC_CHINTENCLR11 (*(RwReg8 *)0x4100A0FCUL)
415 #define REG_DMAC_CHINTENSET11 (*(RwReg8 *)0x4100A0FDUL)
416 #define REG_DMAC_CHINTFLAG11 (*(RwReg8 *)0x4100A0FEUL)
417 #define REG_DMAC_CHSTATUS11 (*(RwReg8 *)0x4100A0FFUL)
418 #define REG_DMAC_CHCTRLA12 (*(RwReg *)0x4100A100UL)
419 #define REG_DMAC_CHCTRLB12 (*(RwReg8 *)0x4100A104UL)
420 #define REG_DMAC_CHPRILVL12 (*(RwReg8 *)0x4100A105UL)
421 #define REG_DMAC_CHEVCTRL12 (*(RwReg8 *)0x4100A106UL)
422 #define REG_DMAC_CHINTENCLR12 (*(RwReg8 *)0x4100A10CUL)
423 #define REG_DMAC_CHINTENSET12 (*(RwReg8 *)0x4100A10DUL)
424 #define REG_DMAC_CHINTFLAG12 (*(RwReg8 *)0x4100A10EUL)
425 #define REG_DMAC_CHSTATUS12 (*(RwReg8 *)0x4100A10FUL)
426 #define REG_DMAC_CHCTRLA13 (*(RwReg *)0x4100A110UL)
427 #define REG_DMAC_CHCTRLB13 (*(RwReg8 *)0x4100A114UL)
428 #define REG_DMAC_CHPRILVL13 (*(RwReg8 *)0x4100A115UL)
429 #define REG_DMAC_CHEVCTRL13 (*(RwReg8 *)0x4100A116UL)
430 #define REG_DMAC_CHINTENCLR13 (*(RwReg8 *)0x4100A11CUL)
431 #define REG_DMAC_CHINTENSET13 (*(RwReg8 *)0x4100A11DUL)
432 #define REG_DMAC_CHINTFLAG13 (*(RwReg8 *)0x4100A11EUL)
433 #define REG_DMAC_CHSTATUS13 (*(RwReg8 *)0x4100A11FUL)
434 #define REG_DMAC_CHCTRLA14 (*(RwReg *)0x4100A120UL)
435 #define REG_DMAC_CHCTRLB14 (*(RwReg8 *)0x4100A124UL)
436 #define REG_DMAC_CHPRILVL14 (*(RwReg8 *)0x4100A125UL)
437 #define REG_DMAC_CHEVCTRL14 (*(RwReg8 *)0x4100A126UL)
438 #define REG_DMAC_CHINTENCLR14 (*(RwReg8 *)0x4100A12CUL)
439 #define REG_DMAC_CHINTENSET14 (*(RwReg8 *)0x4100A12DUL)
440 #define REG_DMAC_CHINTFLAG14 (*(RwReg8 *)0x4100A12EUL)
441 #define REG_DMAC_CHSTATUS14 (*(RwReg8 *)0x4100A12FUL)
442 #define REG_DMAC_CHCTRLA15 (*(RwReg *)0x4100A130UL)
443 #define REG_DMAC_CHCTRLB15 (*(RwReg8 *)0x4100A134UL)
444 #define REG_DMAC_CHPRILVL15 (*(RwReg8 *)0x4100A135UL)
445 #define REG_DMAC_CHEVCTRL15 (*(RwReg8 *)0x4100A136UL)
446 #define REG_DMAC_CHINTENCLR15 (*(RwReg8 *)0x4100A13CUL)
447 #define REG_DMAC_CHINTENSET15 (*(RwReg8 *)0x4100A13DUL)
448 #define REG_DMAC_CHINTFLAG15 (*(RwReg8 *)0x4100A13EUL)
449 #define REG_DMAC_CHSTATUS15 (*(RwReg8 *)0x4100A13FUL)
450 #define REG_DMAC_CHCTRLA16 (*(RwReg *)0x4100A140UL)
451 #define REG_DMAC_CHCTRLB16 (*(RwReg8 *)0x4100A144UL)
452 #define REG_DMAC_CHPRILVL16 (*(RwReg8 *)0x4100A145UL)
453 #define REG_DMAC_CHEVCTRL16 (*(RwReg8 *)0x4100A146UL)
454 #define REG_DMAC_CHINTENCLR16 (*(RwReg8 *)0x4100A14CUL)
455 #define REG_DMAC_CHINTENSET16 (*(RwReg8 *)0x4100A14DUL)
456 #define REG_DMAC_CHINTFLAG16 (*(RwReg8 *)0x4100A14EUL)
457 #define REG_DMAC_CHSTATUS16 (*(RwReg8 *)0x4100A14FUL)
458 #define REG_DMAC_CHCTRLA17 (*(RwReg *)0x4100A150UL)
459 #define REG_DMAC_CHCTRLB17 (*(RwReg8 *)0x4100A154UL)
460 #define REG_DMAC_CHPRILVL17 (*(RwReg8 *)0x4100A155UL)
461 #define REG_DMAC_CHEVCTRL17 (*(RwReg8 *)0x4100A156UL)
462 #define REG_DMAC_CHINTENCLR17 (*(RwReg8 *)0x4100A15CUL)
463 #define REG_DMAC_CHINTENSET17 (*(RwReg8 *)0x4100A15DUL)
464 #define REG_DMAC_CHINTFLAG17 (*(RwReg8 *)0x4100A15EUL)
465 #define REG_DMAC_CHSTATUS17 (*(RwReg8 *)0x4100A15FUL)
466 #define REG_DMAC_CHCTRLA18 (*(RwReg *)0x4100A160UL)
467 #define REG_DMAC_CHCTRLB18 (*(RwReg8 *)0x4100A164UL)
468 #define REG_DMAC_CHPRILVL18 (*(RwReg8 *)0x4100A165UL)
469 #define REG_DMAC_CHEVCTRL18 (*(RwReg8 *)0x4100A166UL)
470 #define REG_DMAC_CHINTENCLR18 (*(RwReg8 *)0x4100A16CUL)
471 #define REG_DMAC_CHINTENSET18 (*(RwReg8 *)0x4100A16DUL)
472 #define REG_DMAC_CHINTFLAG18 (*(RwReg8 *)0x4100A16EUL)
473 #define REG_DMAC_CHSTATUS18 (*(RwReg8 *)0x4100A16FUL)
474 #define REG_DMAC_CHCTRLA19 (*(RwReg *)0x4100A170UL)
475 #define REG_DMAC_CHCTRLB19 (*(RwReg8 *)0x4100A174UL)
476 #define REG_DMAC_CHPRILVL19 (*(RwReg8 *)0x4100A175UL)
477 #define REG_DMAC_CHEVCTRL19 (*(RwReg8 *)0x4100A176UL)
478 #define REG_DMAC_CHINTENCLR19 (*(RwReg8 *)0x4100A17CUL)
479 #define REG_DMAC_CHINTENSET19 (*(RwReg8 *)0x4100A17DUL)
480 #define REG_DMAC_CHINTFLAG19 (*(RwReg8 *)0x4100A17EUL)
481 #define REG_DMAC_CHSTATUS19 (*(RwReg8 *)0x4100A17FUL)
482 #define REG_DMAC_CHCTRLA20 (*(RwReg *)0x4100A180UL)
483 #define REG_DMAC_CHCTRLB20 (*(RwReg8 *)0x4100A184UL)
484 #define REG_DMAC_CHPRILVL20 (*(RwReg8 *)0x4100A185UL)
485 #define REG_DMAC_CHEVCTRL20 (*(RwReg8 *)0x4100A186UL)
486 #define REG_DMAC_CHINTENCLR20 (*(RwReg8 *)0x4100A18CUL)
487 #define REG_DMAC_CHINTENSET20 (*(RwReg8 *)0x4100A18DUL)
488 #define REG_DMAC_CHINTFLAG20 (*(RwReg8 *)0x4100A18EUL)
489 #define REG_DMAC_CHSTATUS20 (*(RwReg8 *)0x4100A18FUL)
490 #define REG_DMAC_CHCTRLA21 (*(RwReg *)0x4100A190UL)
491 #define REG_DMAC_CHCTRLB21 (*(RwReg8 *)0x4100A194UL)
492 #define REG_DMAC_CHPRILVL21 (*(RwReg8 *)0x4100A195UL)
493 #define REG_DMAC_CHEVCTRL21 (*(RwReg8 *)0x4100A196UL)
494 #define REG_DMAC_CHINTENCLR21 (*(RwReg8 *)0x4100A19CUL)
495 #define REG_DMAC_CHINTENSET21 (*(RwReg8 *)0x4100A19DUL)
496 #define REG_DMAC_CHINTFLAG21 (*(RwReg8 *)0x4100A19EUL)
497 #define REG_DMAC_CHSTATUS21 (*(RwReg8 *)0x4100A19FUL)
498 #define REG_DMAC_CHCTRLA22 (*(RwReg *)0x4100A1A0UL)
499 #define REG_DMAC_CHCTRLB22 (*(RwReg8 *)0x4100A1A4UL)
500 #define REG_DMAC_CHPRILVL22 (*(RwReg8 *)0x4100A1A5UL)
501 #define REG_DMAC_CHEVCTRL22 (*(RwReg8 *)0x4100A1A6UL)
502 #define REG_DMAC_CHINTENCLR22 (*(RwReg8 *)0x4100A1ACUL)
503 #define REG_DMAC_CHINTENSET22 (*(RwReg8 *)0x4100A1ADUL)
504 #define REG_DMAC_CHINTFLAG22 (*(RwReg8 *)0x4100A1AEUL)
505 #define REG_DMAC_CHSTATUS22 (*(RwReg8 *)0x4100A1AFUL)
506 #define REG_DMAC_CHCTRLA23 (*(RwReg *)0x4100A1B0UL)
507 #define REG_DMAC_CHCTRLB23 (*(RwReg8 *)0x4100A1B4UL)
508 #define REG_DMAC_CHPRILVL23 (*(RwReg8 *)0x4100A1B5UL)
509 #define REG_DMAC_CHEVCTRL23 (*(RwReg8 *)0x4100A1B6UL)
510 #define REG_DMAC_CHINTENCLR23 (*(RwReg8 *)0x4100A1BCUL)
511 #define REG_DMAC_CHINTENSET23 (*(RwReg8 *)0x4100A1BDUL)
512 #define REG_DMAC_CHINTFLAG23 (*(RwReg8 *)0x4100A1BEUL)
513 #define REG_DMAC_CHSTATUS23 (*(RwReg8 *)0x4100A1BFUL)
514 #define REG_DMAC_CHCTRLA24 (*(RwReg *)0x4100A1C0UL)
515 #define REG_DMAC_CHCTRLB24 (*(RwReg8 *)0x4100A1C4UL)
516 #define REG_DMAC_CHPRILVL24 (*(RwReg8 *)0x4100A1C5UL)
517 #define REG_DMAC_CHEVCTRL24 (*(RwReg8 *)0x4100A1C6UL)
518 #define REG_DMAC_CHINTENCLR24 (*(RwReg8 *)0x4100A1CCUL)
519 #define REG_DMAC_CHINTENSET24 (*(RwReg8 *)0x4100A1CDUL)
520 #define REG_DMAC_CHINTFLAG24 (*(RwReg8 *)0x4100A1CEUL)
521 #define REG_DMAC_CHSTATUS24 (*(RwReg8 *)0x4100A1CFUL)
522 #define REG_DMAC_CHCTRLA25 (*(RwReg *)0x4100A1D0UL)
523 #define REG_DMAC_CHCTRLB25 (*(RwReg8 *)0x4100A1D4UL)
524 #define REG_DMAC_CHPRILVL25 (*(RwReg8 *)0x4100A1D5UL)
525 #define REG_DMAC_CHEVCTRL25 (*(RwReg8 *)0x4100A1D6UL)
526 #define REG_DMAC_CHINTENCLR25 (*(RwReg8 *)0x4100A1DCUL)
527 #define REG_DMAC_CHINTENSET25 (*(RwReg8 *)0x4100A1DDUL)
528 #define REG_DMAC_CHINTFLAG25 (*(RwReg8 *)0x4100A1DEUL)
529 #define REG_DMAC_CHSTATUS25 (*(RwReg8 *)0x4100A1DFUL)
530 #define REG_DMAC_CHCTRLA26 (*(RwReg *)0x4100A1E0UL)
531 #define REG_DMAC_CHCTRLB26 (*(RwReg8 *)0x4100A1E4UL)
532 #define REG_DMAC_CHPRILVL26 (*(RwReg8 *)0x4100A1E5UL)
533 #define REG_DMAC_CHEVCTRL26 (*(RwReg8 *)0x4100A1E6UL)
534 #define REG_DMAC_CHINTENCLR26 (*(RwReg8 *)0x4100A1ECUL)
535 #define REG_DMAC_CHINTENSET26 (*(RwReg8 *)0x4100A1EDUL)
536 #define REG_DMAC_CHINTFLAG26 (*(RwReg8 *)0x4100A1EEUL)
537 #define REG_DMAC_CHSTATUS26 (*(RwReg8 *)0x4100A1EFUL)
538 #define REG_DMAC_CHCTRLA27 (*(RwReg *)0x4100A1F0UL)
539 #define REG_DMAC_CHCTRLB27 (*(RwReg8 *)0x4100A1F4UL)
540 #define REG_DMAC_CHPRILVL27 (*(RwReg8 *)0x4100A1F5UL)
541 #define REG_DMAC_CHEVCTRL27 (*(RwReg8 *)0x4100A1F6UL)
542 #define REG_DMAC_CHINTENCLR27 (*(RwReg8 *)0x4100A1FCUL)
543 #define REG_DMAC_CHINTENSET27 (*(RwReg8 *)0x4100A1FDUL)
544 #define REG_DMAC_CHINTFLAG27 (*(RwReg8 *)0x4100A1FEUL)
545 #define REG_DMAC_CHSTATUS27 (*(RwReg8 *)0x4100A1FFUL)
546 #define REG_DMAC_CHCTRLA28 (*(RwReg *)0x4100A200UL)
547 #define REG_DMAC_CHCTRLB28 (*(RwReg8 *)0x4100A204UL)
548 #define REG_DMAC_CHPRILVL28 (*(RwReg8 *)0x4100A205UL)
549 #define REG_DMAC_CHEVCTRL28 (*(RwReg8 *)0x4100A206UL)
550 #define REG_DMAC_CHINTENCLR28 (*(RwReg8 *)0x4100A20CUL)
551 #define REG_DMAC_CHINTENSET28 (*(RwReg8 *)0x4100A20DUL)
552 #define REG_DMAC_CHINTFLAG28 (*(RwReg8 *)0x4100A20EUL)
553 #define REG_DMAC_CHSTATUS28 (*(RwReg8 *)0x4100A20FUL)
554 #define REG_DMAC_CHCTRLA29 (*(RwReg *)0x4100A210UL)
555 #define REG_DMAC_CHCTRLB29 (*(RwReg8 *)0x4100A214UL)
556 #define REG_DMAC_CHPRILVL29 (*(RwReg8 *)0x4100A215UL)
557 #define REG_DMAC_CHEVCTRL29 (*(RwReg8 *)0x4100A216UL)
558 #define REG_DMAC_CHINTENCLR29 (*(RwReg8 *)0x4100A21CUL)
559 #define REG_DMAC_CHINTENSET29 (*(RwReg8 *)0x4100A21DUL)
560 #define REG_DMAC_CHINTFLAG29 (*(RwReg8 *)0x4100A21EUL)
561 #define REG_DMAC_CHSTATUS29 (*(RwReg8 *)0x4100A21FUL)
562 #define REG_DMAC_CHCTRLA30 (*(RwReg *)0x4100A220UL)
563 #define REG_DMAC_CHCTRLB30 (*(RwReg8 *)0x4100A224UL)
564 #define REG_DMAC_CHPRILVL30 (*(RwReg8 *)0x4100A225UL)
565 #define REG_DMAC_CHEVCTRL30 (*(RwReg8 *)0x4100A226UL)
566 #define REG_DMAC_CHINTENCLR30 (*(RwReg8 *)0x4100A22CUL)
567 #define REG_DMAC_CHINTENSET30 (*(RwReg8 *)0x4100A22DUL)
568 #define REG_DMAC_CHINTFLAG30 (*(RwReg8 *)0x4100A22EUL)
569 #define REG_DMAC_CHSTATUS30 (*(RwReg8 *)0x4100A22FUL)
570 #define REG_DMAC_CHCTRLA31 (*(RwReg *)0x4100A230UL)
571 #define REG_DMAC_CHCTRLB31 (*(RwReg8 *)0x4100A234UL)
572 #define REG_DMAC_CHPRILVL31 (*(RwReg8 *)0x4100A235UL)
573 #define REG_DMAC_CHEVCTRL31 (*(RwReg8 *)0x4100A236UL)
574 #define REG_DMAC_CHINTENCLR31 (*(RwReg8 *)0x4100A23CUL)
575 #define REG_DMAC_CHINTENSET31 (*(RwReg8 *)0x4100A23DUL)
576 #define REG_DMAC_CHINTFLAG31 (*(RwReg8 *)0x4100A23EUL)
577 #define REG_DMAC_CHSTATUS31 (*(RwReg8 *)0x4100A23FUL)
578 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
579 
580 /* ========== Instance parameters for DMAC peripheral ========== */
581 #define DMAC_BURST 1 // 0: no burst support; 1: burst support
582 #define DMAC_CH_BITS 5 // Number of bits to select channel
583 #define DMAC_CH_NUM 32 // Number of channels
584 #define DMAC_CLK_AHB_ID 9 // AHB clock index
585 #define DMAC_EVIN_NUM 8 // Number of input events
586 #define DMAC_EVOUT_NUM 4 // Number of output events
587 #define DMAC_FIFO_SIZE 16 // FIFO size for burst mode.
588 #define DMAC_LVL_BITS 2 // Number of bits to select level priority
589 #define DMAC_LVL_NUM 4 // Enable priority level number
590 #define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
591 #define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
592 #define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
593 #define DMAC_TRIG_BITS 7 // Number of bits to select trigger source
594 #define DMAC_TRIG_NUM 85 // Number of peripheral triggers
595 
596 #endif /* _SAME54_DMAC_INSTANCE_ */