SAME54P20A Test Project
port.h
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1 
30 #ifndef _SAME54_PORT_COMPONENT_
31 #define _SAME54_PORT_COMPONENT_
32 
33 /* ========================================================================== */
35 /* ========================================================================== */
38 
39 #define PORT_U2210
40 #define REV_PORT 0x220
41 
42 /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
44 typedef union {
45  struct {
46  uint32_t DIR:32;
47  } bit;
48  uint32_t reg;
50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
51 
52 #define PORT_DIR_OFFSET 0x00
53 #define PORT_DIR_RESETVALUE _U_(0x00000000)
55 #define PORT_DIR_DIR_Pos 0
56 #define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
57 #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
58 #define PORT_DIR_MASK _U_(0xFFFFFFFF)
60 /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
62 typedef union {
63  struct {
64  uint32_t DIRCLR:32;
65  } bit;
66  uint32_t reg;
68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
69 
70 #define PORT_DIRCLR_OFFSET 0x04
71 #define PORT_DIRCLR_RESETVALUE _U_(0x00000000)
73 #define PORT_DIRCLR_DIRCLR_Pos 0
74 #define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
75 #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
76 #define PORT_DIRCLR_MASK _U_(0xFFFFFFFF)
78 /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
80 typedef union {
81  struct {
82  uint32_t DIRSET:32;
83  } bit;
84  uint32_t reg;
86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
87 
88 #define PORT_DIRSET_OFFSET 0x08
89 #define PORT_DIRSET_RESETVALUE _U_(0x00000000)
91 #define PORT_DIRSET_DIRSET_Pos 0
92 #define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
93 #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
94 #define PORT_DIRSET_MASK _U_(0xFFFFFFFF)
96 /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
98 typedef union {
99  struct {
100  uint32_t DIRTGL:32;
101  } bit;
102  uint32_t reg;
104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
105 
106 #define PORT_DIRTGL_OFFSET 0x0C
107 #define PORT_DIRTGL_RESETVALUE _U_(0x00000000)
109 #define PORT_DIRTGL_DIRTGL_Pos 0
110 #define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
111 #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
112 #define PORT_DIRTGL_MASK _U_(0xFFFFFFFF)
114 /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
116 typedef union {
117  struct {
118  uint32_t OUT:32;
119  } bit;
120  uint32_t reg;
121 } PORT_OUT_Type;
122 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
123 
124 #define PORT_OUT_OFFSET 0x10
125 #define PORT_OUT_RESETVALUE _U_(0x00000000)
127 #define PORT_OUT_OUT_Pos 0
128 #define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
129 #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
130 #define PORT_OUT_MASK _U_(0xFFFFFFFF)
132 /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
134 typedef union {
135  struct {
136  uint32_t OUTCLR:32;
137  } bit;
138  uint32_t reg;
140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
141 
142 #define PORT_OUTCLR_OFFSET 0x14
143 #define PORT_OUTCLR_RESETVALUE _U_(0x00000000)
145 #define PORT_OUTCLR_OUTCLR_Pos 0
146 #define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
147 #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
148 #define PORT_OUTCLR_MASK _U_(0xFFFFFFFF)
150 /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
152 typedef union {
153  struct {
154  uint32_t OUTSET:32;
155  } bit;
156  uint32_t reg;
158 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
159 
160 #define PORT_OUTSET_OFFSET 0x18
161 #define PORT_OUTSET_RESETVALUE _U_(0x00000000)
163 #define PORT_OUTSET_OUTSET_Pos 0
164 #define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
165 #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
166 #define PORT_OUTSET_MASK _U_(0xFFFFFFFF)
168 /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
170 typedef union {
171  struct {
172  uint32_t OUTTGL:32;
173  } bit;
174  uint32_t reg;
176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
177 
178 #define PORT_OUTTGL_OFFSET 0x1C
179 #define PORT_OUTTGL_RESETVALUE _U_(0x00000000)
181 #define PORT_OUTTGL_OUTTGL_Pos 0
182 #define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
183 #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
184 #define PORT_OUTTGL_MASK _U_(0xFFFFFFFF)
186 /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
188 typedef union {
189  struct {
190  uint32_t IN:32;
191  } bit;
192  uint32_t reg;
193 } PORT_IN_Type;
194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
195 
196 #define PORT_IN_OFFSET 0x20
197 #define PORT_IN_RESETVALUE _U_(0x00000000)
199 #define PORT_IN_IN_Pos 0
200 #define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
201 #define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
202 #define PORT_IN_MASK _U_(0xFFFFFFFF)
204 /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
206 typedef union {
207  struct {
208  uint32_t SAMPLING:32;
209  } bit;
210  uint32_t reg;
212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
213 
214 #define PORT_CTRL_OFFSET 0x24
215 #define PORT_CTRL_RESETVALUE _U_(0x00000000)
217 #define PORT_CTRL_SAMPLING_Pos 0
218 #define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
219 #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
220 #define PORT_CTRL_MASK _U_(0xFFFFFFFF)
222 /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
223 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
224 typedef union {
225  struct {
226  uint32_t PINMASK:16;
227  uint32_t PMUXEN:1;
228  uint32_t INEN:1;
229  uint32_t PULLEN:1;
230  uint32_t :3;
231  uint32_t DRVSTR:1;
232  uint32_t :1;
233  uint32_t PMUX:4;
234  uint32_t WRPMUX:1;
235  uint32_t :1;
236  uint32_t WRPINCFG:1;
237  uint32_t HWSEL:1;
238  } bit;
239  uint32_t reg;
241 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
242 
243 #define PORT_WRCONFIG_OFFSET 0x28
244 #define PORT_WRCONFIG_RESETVALUE _U_(0x00000000)
246 #define PORT_WRCONFIG_PINMASK_Pos 0
247 #define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
248 #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
249 #define PORT_WRCONFIG_PMUXEN_Pos 16
250 #define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
251 #define PORT_WRCONFIG_INEN_Pos 17
252 #define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
253 #define PORT_WRCONFIG_PULLEN_Pos 18
254 #define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
255 #define PORT_WRCONFIG_DRVSTR_Pos 22
256 #define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
257 #define PORT_WRCONFIG_PMUX_Pos 24
258 #define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
259 #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
260 #define PORT_WRCONFIG_WRPMUX_Pos 28
261 #define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
262 #define PORT_WRCONFIG_WRPINCFG_Pos 30
263 #define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
264 #define PORT_WRCONFIG_HWSEL_Pos 31
265 #define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
266 #define PORT_WRCONFIG_MASK _U_(0xDF47FFFF)
268 /* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
269 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
270 typedef union {
271  struct {
272  uint32_t PID0:5;
273  uint32_t EVACT0:2;
274  uint32_t PORTEI0:1;
275  uint32_t PID1:5;
276  uint32_t EVACT1:2;
277  uint32_t PORTEI1:1;
278  uint32_t PID2:5;
279  uint32_t EVACT2:2;
280  uint32_t PORTEI2:1;
281  uint32_t PID3:5;
282  uint32_t EVACT3:2;
283  uint32_t PORTEI3:1;
284  } bit;
285  uint32_t reg;
287 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
288 
289 #define PORT_EVCTRL_OFFSET 0x2C
290 #define PORT_EVCTRL_RESETVALUE _U_(0x00000000)
292 #define PORT_EVCTRL_PID0_Pos 0
293 #define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
294 #define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
295 #define PORT_EVCTRL_EVACT0_Pos 5
296 #define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
297 #define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
298 #define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0)
299 #define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1)
300 #define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2)
301 #define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3)
302 #define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos)
303 #define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos)
304 #define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos)
305 #define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos)
306 #define PORT_EVCTRL_PORTEI0_Pos 7
307 #define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
308 #define PORT_EVCTRL_PID1_Pos 8
309 #define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
310 #define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
311 #define PORT_EVCTRL_EVACT1_Pos 13
312 #define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
313 #define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
314 #define PORT_EVCTRL_PORTEI1_Pos 15
315 #define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
316 #define PORT_EVCTRL_PID2_Pos 16
317 #define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
318 #define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
319 #define PORT_EVCTRL_EVACT2_Pos 21
320 #define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
321 #define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
322 #define PORT_EVCTRL_PORTEI2_Pos 23
323 #define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
324 #define PORT_EVCTRL_PID3_Pos 24
325 #define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
326 #define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
327 #define PORT_EVCTRL_EVACT3_Pos 29
328 #define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
329 #define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
330 #define PORT_EVCTRL_PORTEI3_Pos 31
331 #define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
332 #define PORT_EVCTRL_MASK _U_(0xFFFFFFFF)
334 /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing -------- */
335 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
336 typedef union {
337  struct {
338  uint8_t PMUXE:4;
339  uint8_t PMUXO:4;
340  } bit;
341  uint8_t reg;
343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
344 
345 #define PORT_PMUX_OFFSET 0x30
346 #define PORT_PMUX_RESETVALUE _U_(0x00)
348 #define PORT_PMUX_PMUXE_Pos 0
349 #define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
350 #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
351 #define PORT_PMUX_PMUXO_Pos 4
352 #define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
353 #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
354 #define PORT_PMUX_MASK _U_(0xFF)
356 /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration -------- */
357 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
358 typedef union {
359  struct {
360  uint8_t PMUXEN:1;
361  uint8_t INEN:1;
362  uint8_t PULLEN:1;
363  uint8_t :3;
364  uint8_t DRVSTR:1;
365  uint8_t :1;
366  } bit;
367  uint8_t reg;
369 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
370 
371 #define PORT_PINCFG_OFFSET 0x40
372 #define PORT_PINCFG_RESETVALUE _U_(0x00)
374 #define PORT_PINCFG_PMUXEN_Pos 0
375 #define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
376 #define PORT_PINCFG_INEN_Pos 1
377 #define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
378 #define PORT_PINCFG_PULLEN_Pos 2
379 #define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
380 #define PORT_PINCFG_DRVSTR_Pos 6
381 #define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
382 #define PORT_PINCFG_MASK _U_(0x47)
385 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
386 typedef struct {
399  __IO PORT_PMUX_Type PMUX[16];
400  __IO PORT_PINCFG_Type PINCFG[32];
401  RoReg8 Reserved1[0x20];
402 } PortGroup;
403 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
404 
406 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
407 typedef struct {
408  PortGroup Group[4];
409 } Port;
410 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
411 
414 #endif /* _SAME54_PORT_COMPONENT_ */
PORT_EVCTRL_Type::PID2
uint32_t PID2
Definition: port.h:278
PORT_WRCONFIG_Type::PINMASK
uint32_t PINMASK
Definition: port.h:226
PORT_WRCONFIG_Type::PMUX
uint32_t PMUX
Definition: port.h:233
PortGroup::OUT
__IO PORT_OUT_Type OUT
Offset: 0x10 (R/W 32) Data Output Value.
Definition: port.h:391
PORT_WRCONFIG_Type::WRPMUX
uint32_t WRPMUX
Definition: port.h:234
PORT_WRCONFIG_Type
Definition: port.h:224
PORT_DIR_Type
Definition: port.h:44
PORT_PMUX_Type::reg
uint8_t reg
Definition: port.h:341
PORT_EVCTRL_Type::reg
uint32_t reg
Definition: port.h:285
PORT_WRCONFIG_Type::reg
uint32_t reg
Definition: port.h:239
PORT_OUTSET_Type::OUTSET
uint32_t OUTSET
Definition: port.h:154
PORT_EVCTRL_Type::PID3
uint32_t PID3
Definition: port.h:281
PORT_PINCFG_Type::PULLEN
uint8_t PULLEN
Definition: port.h:362
PORT_OUT_Type::reg
uint32_t reg
Definition: port.h:120
PORT_CTRL_Type::reg
uint32_t reg
Definition: port.h:210
PORT_WRCONFIG_Type::WRPINCFG
uint32_t WRPINCFG
Definition: port.h:236
PORT_OUTTGL_Type
Definition: port.h:170
PORT_OUTTGL_Type::reg
uint32_t reg
Definition: port.h:174
Port
PORT hardware registers.
Definition: port.h:407
PORT_DIRCLR_Type::DIRCLR
uint32_t DIRCLR
Definition: port.h:64
PORT_PINCFG_Type::DRVSTR
uint8_t DRVSTR
Definition: port.h:364
PortGroup::DIRCLR
__IO PORT_DIRCLR_Type DIRCLR
Offset: 0x04 (R/W 32) Data Direction Clear.
Definition: port.h:388
PORT_DIRCLR_Type
Definition: port.h:62
PORT_DIRTGL_Type::reg
uint32_t reg
Definition: port.h:102
PortGroup::DIR
__IO PORT_DIR_Type DIR
Offset: 0x00 (R/W 32) Data Direction.
Definition: port.h:387
PORT_WRCONFIG_Type::PMUXEN
uint32_t PMUXEN
Definition: port.h:227
PortGroup::DIRSET
__IO PORT_DIRSET_Type DIRSET
Offset: 0x08 (R/W 32) Data Direction Set.
Definition: port.h:389
PORT_OUTCLR_Type::reg
uint32_t reg
Definition: port.h:138
PORT_PINCFG_Type::reg
uint8_t reg
Definition: port.h:367
PortGroup::CTRL
__IO PORT_CTRL_Type CTRL
Offset: 0x24 (R/W 32) Control.
Definition: port.h:396
PortGroup::OUTTGL
__IO PORT_OUTTGL_Type OUTTGL
Offset: 0x1C (R/W 32) Data Output Value Toggle.
Definition: port.h:394
PORT_DIR_Type::reg
uint32_t reg
Definition: port.h:48
PORT_OUT_Type::OUT
uint32_t OUT
Definition: port.h:118
PORT_PMUX_Type::PMUXO
uint8_t PMUXO
Definition: port.h:339
PORT_WRCONFIG_Type::INEN
uint32_t INEN
Definition: port.h:228
PORT_EVCTRL_Type::EVACT0
uint32_t EVACT0
Definition: port.h:273
PORT_PMUX_Type
Definition: port.h:336
PORT_IN_Type::reg
uint32_t reg
Definition: port.h:192
PORT_DIRSET_Type::DIRSET
uint32_t DIRSET
Definition: port.h:82
PORT_EVCTRL_Type::PID0
uint32_t PID0
Definition: port.h:272
PORT_OUTTGL_Type::OUTTGL
uint32_t OUTTGL
Definition: port.h:172
PORT_CTRL_Type::SAMPLING
uint32_t SAMPLING
Definition: port.h:208
PORT_DIRSET_Type
Definition: port.h:80
PortGroup::DIRTGL
__IO PORT_DIRTGL_Type DIRTGL
Offset: 0x0C (R/W 32) Data Direction Toggle.
Definition: port.h:390
PORT_OUTCLR_Type
Definition: port.h:134
PORT_WRCONFIG_Type::HWSEL
uint32_t HWSEL
Definition: port.h:237
PortGroup::WRCONFIG
__O PORT_WRCONFIG_Type WRCONFIG
Offset: 0x28 ( /W 32) Write Configuration.
Definition: port.h:397
PortGroup::EVCTRL
__IO PORT_EVCTRL_Type EVCTRL
Offset: 0x2C (R/W 32) Event Input Control.
Definition: port.h:398
PORT_IN_Type::IN
uint32_t IN
Definition: port.h:190
PORT_PINCFG_Type::INEN
uint8_t INEN
Definition: port.h:361
PORT_WRCONFIG_Type::DRVSTR
uint32_t DRVSTR
Definition: port.h:231
PORT_OUT_Type
Definition: port.h:116
PORT_WRCONFIG_Type::PULLEN
uint32_t PULLEN
Definition: port.h:229
PORT_PINCFG_Type
Definition: port.h:358
PORT_EVCTRL_Type::EVACT2
uint32_t EVACT2
Definition: port.h:279
PORT_PMUX_Type::PMUXE
uint8_t PMUXE
Definition: port.h:338
PORT_CTRL_Type
Definition: port.h:206
PORT_PINCFG_Type::PMUXEN
uint8_t PMUXEN
Definition: port.h:360
PORT_EVCTRL_Type::PORTEI2
uint32_t PORTEI2
Definition: port.h:280
PORT_OUTSET_Type::reg
uint32_t reg
Definition: port.h:156
PORT_DIR_Type::DIR
uint32_t DIR
Definition: port.h:46
PORT_EVCTRL_Type
Definition: port.h:270
PortGroup::OUTCLR
__IO PORT_OUTCLR_Type OUTCLR
Offset: 0x14 (R/W 32) Data Output Value Clear.
Definition: port.h:392
PORT_EVCTRL_Type::PORTEI1
uint32_t PORTEI1
Definition: port.h:277
PORT_OUTCLR_Type::OUTCLR
uint32_t OUTCLR
Definition: port.h:136
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
PORT_EVCTRL_Type::PORTEI0
uint32_t PORTEI0
Definition: port.h:274
PORT_DIRSET_Type::reg
uint32_t reg
Definition: port.h:84
PORT_EVCTRL_Type::EVACT3
uint32_t EVACT3
Definition: port.h:282
PORT_EVCTRL_Type::EVACT1
uint32_t EVACT1
Definition: port.h:276
PORT_DIRTGL_Type
Definition: port.h:98
PORT_EVCTRL_Type::PORTEI3
uint32_t PORTEI3
Definition: port.h:283
PortGroup
PortGroup hardware registers.
Definition: port.h:386
PORT_DIRTGL_Type::DIRTGL
uint32_t DIRTGL
Definition: port.h:100
PORT_DIRCLR_Type::reg
uint32_t reg
Definition: port.h:66
PortGroup::OUTSET
__IO PORT_OUTSET_Type OUTSET
Offset: 0x18 (R/W 32) Data Output Value Set.
Definition: port.h:393
PORT_IN_Type
Definition: port.h:188
PORT_EVCTRL_Type::PID1
uint32_t PID1
Definition: port.h:275
PortGroup::IN
__I PORT_IN_Type IN
Offset: 0x20 (R/ 32) Data Input Value.
Definition: port.h:395
PORT_OUTSET_Type
Definition: port.h:152