SAME54P20A Test Project
Data Fields
GCLK_PCHCTRL_Type Union Reference

Data Fields

struct {
   uint32_t   GEN:4
 
   uint32_t   __pad0__:2
 
   uint32_t   CHEN:1
 
   uint32_t   WRTLOCK:1
 
   uint32_t   __pad1__:24
 
bit
 
uint32_t reg
 

Detailed Description

Definition at line 209 of file gclk.h.

Field Documentation

◆ __pad0__

uint32_t GCLK_PCHCTRL_Type::__pad0__

bit: 4.. 5 Reserved

Definition at line 212 of file gclk.h.

◆ __pad1__

uint32_t GCLK_PCHCTRL_Type::__pad1__

bit: 8..31 Reserved

Definition at line 215 of file gclk.h.

◆ bit

struct { ... } GCLK_PCHCTRL_Type::bit

Structure used for bit access

◆ CHEN

uint32_t GCLK_PCHCTRL_Type::CHEN

bit: 6 Channel Enable

Definition at line 213 of file gclk.h.

◆ GEN

uint32_t GCLK_PCHCTRL_Type::GEN

bit: 0.. 3 Generic Clock Generator

Definition at line 211 of file gclk.h.

◆ reg

uint32_t GCLK_PCHCTRL_Type::reg

Type used for register access

Definition at line 217 of file gclk.h.

◆ WRTLOCK

uint32_t GCLK_PCHCTRL_Type::WRTLOCK

bit: 7 Write Lock

Definition at line 214 of file gclk.h.


The documentation for this union was generated from the following file: