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30 #ifndef _SAME54_EIC_COMPONENT_
31 #define _SAME54_EIC_COMPONENT_
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
56 #define EIC_CTRLA_OFFSET 0x00
57 #define EIC_CTRLA_RESETVALUE _U_(0x00)
59 #define EIC_CTRLA_SWRST_Pos 0
60 #define EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
61 #define EIC_CTRLA_ENABLE_Pos 1
62 #define EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
63 #define EIC_CTRLA_CKSEL_Pos 4
64 #define EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
65 #define EIC_CTRLA_MASK _U_(0x13)
68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
80 #define EIC_NMICTRL_OFFSET 0x01
81 #define EIC_NMICTRL_RESETVALUE _U_(0x00)
83 #define EIC_NMICTRL_NMISENSE_Pos 0
84 #define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
85 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
86 #define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0)
87 #define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1)
88 #define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2)
89 #define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3)
90 #define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4)
91 #define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5)
92 #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
93 #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
94 #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
95 #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
96 #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
97 #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
98 #define EIC_NMICTRL_NMIFILTEN_Pos 3
99 #define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
100 #define EIC_NMICTRL_NMIASYNCH_Pos 4
101 #define EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
102 #define EIC_NMICTRL_MASK _U_(0x1F)
105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
115 #define EIC_NMIFLAG_OFFSET 0x02
116 #define EIC_NMIFLAG_RESETVALUE _U_(0x0000)
118 #define EIC_NMIFLAG_NMI_Pos 0
119 #define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
120 #define EIC_NMIFLAG_MASK _U_(0x0001)
123 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
134 #define EIC_SYNCBUSY_OFFSET 0x04
135 #define EIC_SYNCBUSY_RESETVALUE _U_(0x00000000)
137 #define EIC_SYNCBUSY_SWRST_Pos 0
138 #define EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
139 #define EIC_SYNCBUSY_ENABLE_Pos 1
140 #define EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
141 #define EIC_SYNCBUSY_MASK _U_(0x00000003)
144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
154 #define EIC_EVCTRL_OFFSET 0x08
155 #define EIC_EVCTRL_RESETVALUE _U_(0x00000000)
157 #define EIC_EVCTRL_EXTINTEO_Pos 0
158 #define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
159 #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
160 #define EIC_EVCTRL_MASK _U_(0x0000FFFF)
163 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
173 #define EIC_INTENCLR_OFFSET 0x0C
174 #define EIC_INTENCLR_RESETVALUE _U_(0x00000000)
176 #define EIC_INTENCLR_EXTINT_Pos 0
177 #define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
178 #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
179 #define EIC_INTENCLR_MASK _U_(0x0000FFFF)
182 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
192 #define EIC_INTENSET_OFFSET 0x10
193 #define EIC_INTENSET_RESETVALUE _U_(0x00000000)
195 #define EIC_INTENSET_EXTINT_Pos 0
196 #define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
197 #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
198 #define EIC_INTENSET_MASK _U_(0x0000FFFF)
201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
211 #define EIC_INTFLAG_OFFSET 0x14
212 #define EIC_INTFLAG_RESETVALUE _U_(0x00000000)
214 #define EIC_INTFLAG_EXTINT_Pos 0
215 #define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
216 #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
217 #define EIC_INTFLAG_MASK _U_(0x0000FFFF)
220 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
230 #define EIC_ASYNCH_OFFSET 0x18
231 #define EIC_ASYNCH_RESETVALUE _U_(0x00000000)
233 #define EIC_ASYNCH_ASYNCH_Pos 0
234 #define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
235 #define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
236 #define EIC_ASYNCH_MASK _U_(0x0000FFFF)
239 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
263 #define EIC_CONFIG_OFFSET 0x1C
264 #define EIC_CONFIG_RESETVALUE _U_(0x00000000)
266 #define EIC_CONFIG_SENSE0_Pos 0
267 #define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
268 #define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
269 #define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0)
270 #define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1)
271 #define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2)
272 #define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3)
273 #define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4)
274 #define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5)
275 #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
276 #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
277 #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
278 #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
279 #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
280 #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
281 #define EIC_CONFIG_FILTEN0_Pos 3
282 #define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
283 #define EIC_CONFIG_SENSE1_Pos 4
284 #define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
285 #define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
286 #define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0)
287 #define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1)
288 #define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2)
289 #define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3)
290 #define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4)
291 #define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5)
292 #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
293 #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
294 #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
295 #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
296 #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
297 #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
298 #define EIC_CONFIG_FILTEN1_Pos 7
299 #define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
300 #define EIC_CONFIG_SENSE2_Pos 8
301 #define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
302 #define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
303 #define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0)
304 #define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1)
305 #define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2)
306 #define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3)
307 #define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4)
308 #define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5)
309 #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
310 #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
311 #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
312 #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
313 #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
314 #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
315 #define EIC_CONFIG_FILTEN2_Pos 11
316 #define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
317 #define EIC_CONFIG_SENSE3_Pos 12
318 #define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
319 #define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
320 #define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0)
321 #define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1)
322 #define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2)
323 #define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3)
324 #define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4)
325 #define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5)
326 #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
327 #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
328 #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
329 #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
330 #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
331 #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
332 #define EIC_CONFIG_FILTEN3_Pos 15
333 #define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
334 #define EIC_CONFIG_SENSE4_Pos 16
335 #define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
336 #define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
337 #define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0)
338 #define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1)
339 #define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2)
340 #define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3)
341 #define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4)
342 #define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5)
343 #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
344 #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
345 #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
346 #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
347 #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
348 #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
349 #define EIC_CONFIG_FILTEN4_Pos 19
350 #define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
351 #define EIC_CONFIG_SENSE5_Pos 20
352 #define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
353 #define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
354 #define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0)
355 #define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1)
356 #define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2)
357 #define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3)
358 #define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4)
359 #define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5)
360 #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
361 #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
362 #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
363 #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
364 #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
365 #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
366 #define EIC_CONFIG_FILTEN5_Pos 23
367 #define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
368 #define EIC_CONFIG_SENSE6_Pos 24
369 #define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
370 #define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
371 #define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0)
372 #define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1)
373 #define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2)
374 #define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3)
375 #define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4)
376 #define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5)
377 #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
378 #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
379 #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
380 #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
381 #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
382 #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
383 #define EIC_CONFIG_FILTEN6_Pos 27
384 #define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
385 #define EIC_CONFIG_SENSE7_Pos 28
386 #define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
387 #define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
388 #define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0)
389 #define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1)
390 #define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2)
391 #define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3)
392 #define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4)
393 #define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5)
394 #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
395 #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
396 #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
397 #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
398 #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
399 #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
400 #define EIC_CONFIG_FILTEN7_Pos 31
401 #define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
402 #define EIC_CONFIG_MASK _U_(0xFFFFFFFF)
405 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
415 #define EIC_DEBOUNCEN_OFFSET 0x30
416 #define EIC_DEBOUNCEN_RESETVALUE _U_(0x00000000)
418 #define EIC_DEBOUNCEN_DEBOUNCEN_Pos 0
419 #define EIC_DEBOUNCEN_DEBOUNCEN_Msk (_U_(0xFFFF) << EIC_DEBOUNCEN_DEBOUNCEN_Pos)
420 #define EIC_DEBOUNCEN_DEBOUNCEN(value) (EIC_DEBOUNCEN_DEBOUNCEN_Msk & ((value) << EIC_DEBOUNCEN_DEBOUNCEN_Pos))
421 #define EIC_DEBOUNCEN_MASK _U_(0x0000FFFF)
424 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
439 #define EIC_DPRESCALER_OFFSET 0x34
440 #define EIC_DPRESCALER_RESETVALUE _U_(0x00000000)
442 #define EIC_DPRESCALER_PRESCALER0_Pos 0
443 #define EIC_DPRESCALER_PRESCALER0_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER0_Pos)
444 #define EIC_DPRESCALER_PRESCALER0(value) (EIC_DPRESCALER_PRESCALER0_Msk & ((value) << EIC_DPRESCALER_PRESCALER0_Pos))
445 #define EIC_DPRESCALER_STATES0_Pos 3
446 #define EIC_DPRESCALER_STATES0 (_U_(0x1) << EIC_DPRESCALER_STATES0_Pos)
447 #define EIC_DPRESCALER_PRESCALER1_Pos 4
448 #define EIC_DPRESCALER_PRESCALER1_Msk (_U_(0x7) << EIC_DPRESCALER_PRESCALER1_Pos)
449 #define EIC_DPRESCALER_PRESCALER1(value) (EIC_DPRESCALER_PRESCALER1_Msk & ((value) << EIC_DPRESCALER_PRESCALER1_Pos))
450 #define EIC_DPRESCALER_STATES1_Pos 7
451 #define EIC_DPRESCALER_STATES1 (_U_(0x1) << EIC_DPRESCALER_STATES1_Pos)
452 #define EIC_DPRESCALER_TICKON_Pos 16
453 #define EIC_DPRESCALER_TICKON (_U_(0x1) << EIC_DPRESCALER_TICKON_Pos)
454 #define EIC_DPRESCALER_MASK _U_(0x000100FF)
457 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
467 #define EIC_PINSTATE_OFFSET 0x38
468 #define EIC_PINSTATE_RESETVALUE _U_(0x00000000)
470 #define EIC_PINSTATE_PINSTATE_Pos 0
471 #define EIC_PINSTATE_PINSTATE_Msk (_U_(0xFFFF) << EIC_PINSTATE_PINSTATE_Pos)
472 #define EIC_PINSTATE_PINSTATE(value) (EIC_PINSTATE_PINSTATE_Msk & ((value) << EIC_PINSTATE_PINSTATE_Pos))
473 #define EIC_PINSTATE_MASK _U_(0x0000FFFF)
476 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__I EIC_PINSTATE_Type PINSTATE
Offset: 0x38 (R/ 32) Pin State.
__IO EIC_NMICTRL_Type NMICTRL
Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control.
__IO EIC_NMIFLAG_Type NMIFLAG
Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear.
__IO EIC_DPRESCALER_Type DPRESCALER
Offset: 0x34 (R/W 32) Debouncer Prescaler.
__IO EIC_INTFLAG_Type INTFLAG
Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear.
__IO EIC_ASYNCH_Type ASYNCH
Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode.
__IO EIC_CTRLA_Type CTRLA
Offset: 0x00 (R/W 8) Control A.
__IO EIC_INTENCLR_Type INTENCLR
Offset: 0x0C (R/W 32) Interrupt Enable Clear.
__I EIC_SYNCBUSY_Type SYNCBUSY
Offset: 0x04 (R/ 32) Synchronization Busy.
__IO EIC_INTENSET_Type INTENSET
Offset: 0x10 (R/W 32) Interrupt Enable Set.
__IO EIC_DEBOUNCEN_Type DEBOUNCEN
Offset: 0x30 (R/W 32) Debouncer Enable.
__IO EIC_EVCTRL_Type EVCTRL
Offset: 0x08 (R/W 32) Event Control.
volatile const uint8_t RoReg8