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30 #ifndef _SAME54_PORT_COMPONENT_
31 #define _SAME54_PORT_COMPONENT_
40 #define REV_PORT 0x220
43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
52 #define PORT_DIR_OFFSET 0x00
53 #define PORT_DIR_RESETVALUE _U_(0x00000000)
55 #define PORT_DIR_DIR_Pos 0
56 #define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
57 #define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
58 #define PORT_DIR_MASK _U_(0xFFFFFFFF)
61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
70 #define PORT_DIRCLR_OFFSET 0x04
71 #define PORT_DIRCLR_RESETVALUE _U_(0x00000000)
73 #define PORT_DIRCLR_DIRCLR_Pos 0
74 #define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
75 #define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
76 #define PORT_DIRCLR_MASK _U_(0xFFFFFFFF)
79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
88 #define PORT_DIRSET_OFFSET 0x08
89 #define PORT_DIRSET_RESETVALUE _U_(0x00000000)
91 #define PORT_DIRSET_DIRSET_Pos 0
92 #define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
93 #define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
94 #define PORT_DIRSET_MASK _U_(0xFFFFFFFF)
97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
106 #define PORT_DIRTGL_OFFSET 0x0C
107 #define PORT_DIRTGL_RESETVALUE _U_(0x00000000)
109 #define PORT_DIRTGL_DIRTGL_Pos 0
110 #define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
111 #define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
112 #define PORT_DIRTGL_MASK _U_(0xFFFFFFFF)
115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
124 #define PORT_OUT_OFFSET 0x10
125 #define PORT_OUT_RESETVALUE _U_(0x00000000)
127 #define PORT_OUT_OUT_Pos 0
128 #define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
129 #define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
130 #define PORT_OUT_MASK _U_(0xFFFFFFFF)
133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
142 #define PORT_OUTCLR_OFFSET 0x14
143 #define PORT_OUTCLR_RESETVALUE _U_(0x00000000)
145 #define PORT_OUTCLR_OUTCLR_Pos 0
146 #define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
147 #define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
148 #define PORT_OUTCLR_MASK _U_(0xFFFFFFFF)
151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
160 #define PORT_OUTSET_OFFSET 0x18
161 #define PORT_OUTSET_RESETVALUE _U_(0x00000000)
163 #define PORT_OUTSET_OUTSET_Pos 0
164 #define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
165 #define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
166 #define PORT_OUTSET_MASK _U_(0xFFFFFFFF)
169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
178 #define PORT_OUTTGL_OFFSET 0x1C
179 #define PORT_OUTTGL_RESETVALUE _U_(0x00000000)
181 #define PORT_OUTTGL_OUTTGL_Pos 0
182 #define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
183 #define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
184 #define PORT_OUTTGL_MASK _U_(0xFFFFFFFF)
187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
196 #define PORT_IN_OFFSET 0x20
197 #define PORT_IN_RESETVALUE _U_(0x00000000)
199 #define PORT_IN_IN_Pos 0
200 #define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
201 #define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
202 #define PORT_IN_MASK _U_(0xFFFFFFFF)
205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
214 #define PORT_CTRL_OFFSET 0x24
215 #define PORT_CTRL_RESETVALUE _U_(0x00000000)
217 #define PORT_CTRL_SAMPLING_Pos 0
218 #define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
219 #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
220 #define PORT_CTRL_MASK _U_(0xFFFFFFFF)
223 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
243 #define PORT_WRCONFIG_OFFSET 0x28
244 #define PORT_WRCONFIG_RESETVALUE _U_(0x00000000)
246 #define PORT_WRCONFIG_PINMASK_Pos 0
247 #define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
248 #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
249 #define PORT_WRCONFIG_PMUXEN_Pos 16
250 #define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
251 #define PORT_WRCONFIG_INEN_Pos 17
252 #define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
253 #define PORT_WRCONFIG_PULLEN_Pos 18
254 #define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
255 #define PORT_WRCONFIG_DRVSTR_Pos 22
256 #define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
257 #define PORT_WRCONFIG_PMUX_Pos 24
258 #define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
259 #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
260 #define PORT_WRCONFIG_WRPMUX_Pos 28
261 #define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
262 #define PORT_WRCONFIG_WRPINCFG_Pos 30
263 #define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
264 #define PORT_WRCONFIG_HWSEL_Pos 31
265 #define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
266 #define PORT_WRCONFIG_MASK _U_(0xDF47FFFF)
269 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
289 #define PORT_EVCTRL_OFFSET 0x2C
290 #define PORT_EVCTRL_RESETVALUE _U_(0x00000000)
292 #define PORT_EVCTRL_PID0_Pos 0
293 #define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
294 #define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
295 #define PORT_EVCTRL_EVACT0_Pos 5
296 #define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
297 #define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
298 #define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0)
299 #define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1)
300 #define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2)
301 #define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3)
302 #define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos)
303 #define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos)
304 #define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos)
305 #define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos)
306 #define PORT_EVCTRL_PORTEI0_Pos 7
307 #define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
308 #define PORT_EVCTRL_PID1_Pos 8
309 #define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
310 #define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
311 #define PORT_EVCTRL_EVACT1_Pos 13
312 #define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
313 #define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
314 #define PORT_EVCTRL_PORTEI1_Pos 15
315 #define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
316 #define PORT_EVCTRL_PID2_Pos 16
317 #define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
318 #define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
319 #define PORT_EVCTRL_EVACT2_Pos 21
320 #define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
321 #define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
322 #define PORT_EVCTRL_PORTEI2_Pos 23
323 #define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
324 #define PORT_EVCTRL_PID3_Pos 24
325 #define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
326 #define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
327 #define PORT_EVCTRL_EVACT3_Pos 29
328 #define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
329 #define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
330 #define PORT_EVCTRL_PORTEI3_Pos 31
331 #define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
332 #define PORT_EVCTRL_MASK _U_(0xFFFFFFFF)
335 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
345 #define PORT_PMUX_OFFSET 0x30
346 #define PORT_PMUX_RESETVALUE _U_(0x00)
348 #define PORT_PMUX_PMUXE_Pos 0
349 #define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
350 #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
351 #define PORT_PMUX_PMUXO_Pos 4
352 #define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
353 #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
354 #define PORT_PMUX_MASK _U_(0xFF)
357 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
371 #define PORT_PINCFG_OFFSET 0x40
372 #define PORT_PINCFG_RESETVALUE _U_(0x00)
374 #define PORT_PINCFG_PMUXEN_Pos 0
375 #define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
376 #define PORT_PINCFG_INEN_Pos 1
377 #define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
378 #define PORT_PINCFG_PULLEN_Pos 2
379 #define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
380 #define PORT_PINCFG_DRVSTR_Pos 6
381 #define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
382 #define PORT_PINCFG_MASK _U_(0x47)
385 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
406 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
__IO PORT_OUT_Type OUT
Offset: 0x10 (R/W 32) Data Output Value.
__IO PORT_DIRCLR_Type DIRCLR
Offset: 0x04 (R/W 32) Data Direction Clear.
__IO PORT_DIR_Type DIR
Offset: 0x00 (R/W 32) Data Direction.
__IO PORT_DIRSET_Type DIRSET
Offset: 0x08 (R/W 32) Data Direction Set.
__IO PORT_CTRL_Type CTRL
Offset: 0x24 (R/W 32) Control.
__IO PORT_OUTTGL_Type OUTTGL
Offset: 0x1C (R/W 32) Data Output Value Toggle.
__IO PORT_DIRTGL_Type DIRTGL
Offset: 0x0C (R/W 32) Data Direction Toggle.
__O PORT_WRCONFIG_Type WRCONFIG
Offset: 0x28 ( /W 32) Write Configuration.
__IO PORT_EVCTRL_Type EVCTRL
Offset: 0x2C (R/W 32) Event Input Control.
__IO PORT_OUTCLR_Type OUTCLR
Offset: 0x14 (R/W 32) Data Output Value Clear.
volatile const uint8_t RoReg8
PortGroup hardware registers.
__IO PORT_OUTSET_Type OUTSET
Offset: 0x18 (R/W 32) Data Output Value Set.
__I PORT_IN_Type IN
Offset: 0x20 (R/ 32) Data Input Value.