e54testdir.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .text 000003d0 00000000 00000000 00010000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .relocate 00000000 20000000 20000000 000103d0 2**0 CONTENTS 2 .bkupram 00000000 47000000 47000000 000103d0 2**0 CONTENTS 3 .qspi 00000000 04000000 04000000 000103d0 2**0 CONTENTS 4 .bss 0000001c 20000000 20000000 00020000 2**2 ALLOC 5 .stack 00010004 2000001c 2000001c 00020000 2**0 ALLOC 6 .ARM.attributes 0000002e 00000000 00000000 000103d0 2**0 CONTENTS, READONLY 7 .comment 0000001e 00000000 00000000 000103fe 2**0 CONTENTS, READONLY 8 .debug_info 00000d0a 00000000 00000000 0001041c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 9 .debug_abbrev 00000200 00000000 00000000 00011126 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_aranges 00000048 00000000 00000000 00011326 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_ranges 00000028 00000000 00000000 0001136e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_macro 00026037 00000000 00000000 00011396 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_line 00000cd8 00000000 00000000 000373cd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_str 000f108b 00000000 00000000 000380a5 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_frame 000000cc 00000000 00000000 00129130 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 00000000 : 0: 20 00 01 20 a9 02 00 00 a5 02 00 00 a5 02 00 00 .. ............ 10: a5 02 00 00 a5 02 00 00 a5 02 00 00 00 00 00 00 ................ ... 2c: a5 02 00 00 a5 02 00 00 00 00 00 00 a5 02 00 00 ................ 3c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 4c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 5c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 6c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 7c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 8c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 9c: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ ac: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ bc: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ cc: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ dc: a5 02 00 00 a5 02 00 00 a5 02 00 00 00 00 00 00 ................ ... f4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 104: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 114: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 124: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 134: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 144: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 154: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 164: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 174: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 184: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 194: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 1a4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 1b4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 1c4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 1d4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 1e4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 1f4: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 204: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 214: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 224: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 234: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 244: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 254: a5 02 00 00 a5 02 00 00 a5 02 00 00 a5 02 00 00 ................ 00000264 <__do_global_dtors_aux>: 264: b510 push {r4, lr} 266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>) 268: 7823 ldrb r3, [r4, #0] 26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16> 26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>) 26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12> 270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>) 272: f3af 8000 nop.w 276: 2301 movs r3, #1 278: 7023 strb r3, [r4, #0] 27a: bd10 pop {r4, pc} 27c: 20000000 .word 0x20000000 280: 00000000 .word 0x00000000 284: 000003d0 .word 0x000003d0 00000288 : 288: b508 push {r3, lr} 28a: 4b03 ldr r3, [pc, #12] ; (298 ) 28c: b11b cbz r3, 296 28e: 4903 ldr r1, [pc, #12] ; (29c ) 290: 4803 ldr r0, [pc, #12] ; (2a0 ) 292: f3af 8000 nop.w 296: bd08 pop {r3, pc} 298: 00000000 .word 0x00000000 29c: 20000004 .word 0x20000004 2a0: 000003d0 .word 0x000003d0 000002a4 : /** * \brief Default interrupt handler for unused IRQs. */ void Dummy_Handler(void) { while (1) { 2a4: e7fe b.n 2a4 ... 000002a8 : if (pSrc != pDest) { 2a8: 4918 ldr r1, [pc, #96] ; (30c ) 2aa: 4819 ldr r0, [pc, #100] ; (310 ) 2ac: 4281 cmp r1, r0 { 2ae: b510 push {r4, lr} if (pSrc != pDest) { 2b0: d00a beq.n 2c8 *pDest++ = *pSrc++; 2b2: 4b18 ldr r3, [pc, #96] ; (314 ) 2b4: 1cda adds r2, r3, #3 2b6: 1a12 subs r2, r2, r0 2b8: f022 0203 bic.w r2, r2, #3 2bc: 1ec4 subs r4, r0, #3 2be: 42a3 cmp r3, r4 2c0: bf38 it cc 2c2: 2200 movcc r2, #0 2c4: 4b14 ldr r3, [pc, #80] ; (318 ) 2c6: 4798 blx r3 *pDest++ = 0; 2c8: 4b14 ldr r3, [pc, #80] ; (31c ) 2ca: 4815 ldr r0, [pc, #84] ; (320 ) 2cc: 1cda adds r2, r3, #3 2ce: 1a12 subs r2, r2, r0 2d0: 1ec1 subs r1, r0, #3 2d2: f022 0203 bic.w r2, r2, #3 2d6: 4299 cmp r1, r3 2d8: bf88 it hi 2da: 2200 movhi r2, #0 2dc: 4b11 ldr r3, [pc, #68] ; (324 ) 2de: 2100 movs r1, #0 2e0: 4798 blx r3 SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); 2e2: 4a11 ldr r2, [pc, #68] ; (328 ) 2e4: 4b11 ldr r3, [pc, #68] ; (32c ) 2e6: f022 027f bic.w r2, r2, #127 ; 0x7f 2ea: 609a str r2, [r3, #8] SCB->CPACR |= (0xFu << 20); 2ec: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 2f0: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 2f4: f8c3 2088 str.w r2, [r3, #136] ; 0x88 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 2f8: f3bf 8f4f dsb sy __ASM volatile ("isb 0xF":::"memory"); 2fc: f3bf 8f6f isb sy __libc_init_array(); 300: 4b0b ldr r3, [pc, #44] ; (330 ) 302: 4798 blx r3 main(); 304: 4b0b ldr r3, [pc, #44] ; (334 ) 306: 4798 blx r3 while (1) 308: e7fe b.n 308 30a: bf00 nop 30c: 000003d0 .word 0x000003d0 310: 20000000 .word 0x20000000 314: 20000000 .word 0x20000000 318: 00000385 .word 0x00000385 31c: 2000001c .word 0x2000001c 320: 20000000 .word 0x20000000 324: 000003a1 .word 0x000003a1 328: 00000000 .word 0x00000000 32c: e000ed00 .word 0xe000ed00 330: 0000033d .word 0x0000033d 334: 00000339 .word 0x00000339 00000338
: int main() { for(;;) { asm volatile("nop"); 338: bf00 nop for(;;) 33a: e7fd b.n 338
0000033c <__libc_init_array>: 33c: b570 push {r4, r5, r6, lr} 33e: 4d0d ldr r5, [pc, #52] ; (374 <__libc_init_array+0x38>) 340: 4c0d ldr r4, [pc, #52] ; (378 <__libc_init_array+0x3c>) 342: 1b64 subs r4, r4, r5 344: 10a4 asrs r4, r4, #2 346: 2600 movs r6, #0 348: 42a6 cmp r6, r4 34a: d109 bne.n 360 <__libc_init_array+0x24> 34c: 4d0b ldr r5, [pc, #44] ; (37c <__libc_init_array+0x40>) 34e: 4c0c ldr r4, [pc, #48] ; (380 <__libc_init_array+0x44>) 350: f000 f82e bl 3b0 <_init> 354: 1b64 subs r4, r4, r5 356: 10a4 asrs r4, r4, #2 358: 2600 movs r6, #0 35a: 42a6 cmp r6, r4 35c: d105 bne.n 36a <__libc_init_array+0x2e> 35e: bd70 pop {r4, r5, r6, pc} 360: f855 3b04 ldr.w r3, [r5], #4 364: 4798 blx r3 366: 3601 adds r6, #1 368: e7ee b.n 348 <__libc_init_array+0xc> 36a: f855 3b04 ldr.w r3, [r5], #4 36e: 4798 blx r3 370: 3601 adds r6, #1 372: e7f2 b.n 35a <__libc_init_array+0x1e> 374: 000003bc .word 0x000003bc 378: 000003bc .word 0x000003bc 37c: 000003bc .word 0x000003bc 380: 000003c0 .word 0x000003c0 00000384 : 384: 440a add r2, r1 386: 4291 cmp r1, r2 388: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff 38c: d100 bne.n 390 38e: 4770 bx lr 390: b510 push {r4, lr} 392: f811 4b01 ldrb.w r4, [r1], #1 396: f803 4f01 strb.w r4, [r3, #1]! 39a: 4291 cmp r1, r2 39c: d1f9 bne.n 392 39e: bd10 pop {r4, pc} 000003a0 : 3a0: 4402 add r2, r0 3a2: 4603 mov r3, r0 3a4: 4293 cmp r3, r2 3a6: d100 bne.n 3aa 3a8: 4770 bx lr 3aa: f803 1b01 strb.w r1, [r3], #1 3ae: e7f9 b.n 3a4 000003b0 <_init>: 3b0: b5f8 push {r3, r4, r5, r6, r7, lr} 3b2: bf00 nop 3b4: bcf8 pop {r3, r4, r5, r6, r7} 3b6: bc08 pop {r3} 3b8: 469e mov lr, r3 3ba: 4770 bx lr 000003bc <__frame_dummy_init_array_entry>: 3bc: 0289 0000 .... 000003c0 <_fini>: 3c0: b5f8 push {r3, r4, r5, r6, r7, lr} 3c2: bf00 nop 3c4: bcf8 pop {r3, r4, r5, r6, r7} 3c6: bc08 pop {r3} 3c8: 469e mov lr, r3 3ca: 4770 bx lr 000003cc <__do_global_dtors_aux_fini_array_entry>: 3cc: 0265 0000 e...