testdir.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .text 000002c0 00000000 00000000 00010000 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .relocate 00000000 20000000 20000000 000102c0 2**0 CONTENTS 2 .bss 0000001c 20000000 20000000 00020000 2**2 ALLOC 3 .stack 00002004 2000001c 2000001c 00020000 2**0 ALLOC 4 .ARM.attributes 00000028 00000000 00000000 000102c0 2**0 CONTENTS, READONLY 5 .comment 0000001e 00000000 00000000 000102e8 2**0 CONTENTS, READONLY 6 .debug_info 00003d0a 00000000 00000000 00010306 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 7 .debug_abbrev 000003d9 00000000 00000000 00014010 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 8 .debug_aranges 00000048 00000000 00000000 000143e9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 9 .debug_ranges 000000f0 00000000 00000000 00014431 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 10 .debug_macro 00011a5c 00000000 00000000 00014521 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 11 .debug_line 00000b0b 00000000 00000000 00025f7d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 12 .debug_str 0006ed4e 00000000 00000000 00026a88 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_frame 000000dc 00000000 00000000 000957d8 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_loc 0000027c 00000000 00000000 000958b4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 00000000 : 0: 20 20 00 20 01 01 00 00 fd 00 00 00 fd 00 00 00 . ............ ... 2c: fd 00 00 00 00 00 00 00 00 00 00 00 fd 00 00 00 ................ 3c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................ 4c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................ 5c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................ 6c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................ 7c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................ 8c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................ 9c: fd 00 00 00 fd 00 00 00 fd 00 00 00 fd 00 00 00 ................ ac: fd 00 00 00 00 00 00 00 ........ 000000b4 <__do_global_dtors_aux>: b4: b510 push {r4, lr} b6: 4c06 ldr r4, [pc, #24] ; (d0 <__do_global_dtors_aux+0x1c>) b8: 7823 ldrb r3, [r4, #0] ba: 2b00 cmp r3, #0 bc: d107 bne.n ce <__do_global_dtors_aux+0x1a> be: 4b05 ldr r3, [pc, #20] ; (d4 <__do_global_dtors_aux+0x20>) c0: 2b00 cmp r3, #0 c2: d002 beq.n ca <__do_global_dtors_aux+0x16> c4: 4804 ldr r0, [pc, #16] ; (d8 <__do_global_dtors_aux+0x24>) c6: e000 b.n ca <__do_global_dtors_aux+0x16> c8: bf00 nop ca: 2301 movs r3, #1 cc: 7023 strb r3, [r4, #0] ce: bd10 pop {r4, pc} d0: 20000000 .word 0x20000000 d4: 00000000 .word 0x00000000 d8: 000002c0 .word 0x000002c0 000000dc : dc: 4b04 ldr r3, [pc, #16] ; (f0 ) de: b510 push {r4, lr} e0: 2b00 cmp r3, #0 e2: d003 beq.n ec e4: 4903 ldr r1, [pc, #12] ; (f4 ) e6: 4804 ldr r0, [pc, #16] ; (f8 ) e8: e000 b.n ec ea: bf00 nop ec: bd10 pop {r4, pc} ee: 46c0 nop ; (mov r8, r8) f0: 00000000 .word 0x00000000 f4: 20000004 .word 0x20000004 f8: 000002c0 .word 0x000002c0 000000fc : /** * \brief Default interrupt handler for unused IRQs. */ void Dummy_Handler(void) { while (1) { fc: e7fe b.n fc ... 00000100 : if (pSrc != pDest) { 100: 4925 ldr r1, [pc, #148] ; (198 ) 102: 4826 ldr r0, [pc, #152] ; (19c ) { 104: b570 push {r4, r5, r6, lr} if (pSrc != pDest) { 106: 4281 cmp r1, r0 108: d00a beq.n 120 *pDest++ = *pSrc++; 10a: 4b25 ldr r3, [pc, #148] ; (1a0 ) 10c: 1ec4 subs r4, r0, #3 10e: 2200 movs r2, #0 110: 42a3 cmp r3, r4 112: d303 bcc.n 11c 114: 3303 adds r3, #3 116: 1a1a subs r2, r3, r0 118: 0892 lsrs r2, r2, #2 11a: 0092 lsls r2, r2, #2 11c: 4b21 ldr r3, [pc, #132] ; (1a4 ) 11e: 4798 blx r3 *pDest++ = 0; 120: 4821 ldr r0, [pc, #132] ; (1a8 ) 122: 4b22 ldr r3, [pc, #136] ; (1ac ) 124: 1ec1 subs r1, r0, #3 126: 2200 movs r2, #0 128: 4299 cmp r1, r3 12a: d803 bhi.n 134 12c: 3303 adds r3, #3 12e: 1a1a subs r2, r3, r0 130: 0892 lsrs r2, r2, #2 132: 0092 lsls r2, r2, #2 134: 2100 movs r1, #0 136: 4b1e ldr r3, [pc, #120] ; (1b0 ) 138: 4798 blx r3 SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); 13a: 22ff movs r2, #255 ; 0xff 13c: 4b1d ldr r3, [pc, #116] ; (1b4 ) USB->DEVICE.QOSCTRL.bit.CQOS = 2; 13e: 2103 movs r1, #3 SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); 140: 4393 bics r3, r2 142: 4a1d ldr r2, [pc, #116] ; (1b8 ) USB->DEVICE.QOSCTRL.bit.DQOS = 2; 144: 250c movs r5, #12 SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); 146: 6093 str r3, [r2, #8] SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; 148: 2202 movs r2, #2 USB->DEVICE.QOSCTRL.bit.DQOS = 2; 14a: 2408 movs r4, #8 DMAC->QOSCTRL.bit.DQOS = 2; 14c: 2630 movs r6, #48 ; 0x30 SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; 14e: 4b1b ldr r3, [pc, #108] ; (1bc ) USB->DEVICE.QOSCTRL.bit.CQOS = 2; 150: 481b ldr r0, [pc, #108] ; (1c0 ) SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; 152: 625a str r2, [r3, #36] ; 0x24 USB->DEVICE.QOSCTRL.bit.CQOS = 2; 154: 78c3 ldrb r3, [r0, #3] 156: 438b bics r3, r1 158: 4313 orrs r3, r2 15a: 70c3 strb r3, [r0, #3] USB->DEVICE.QOSCTRL.bit.DQOS = 2; 15c: 78c3 ldrb r3, [r0, #3] 15e: 43ab bics r3, r5 160: 4323 orrs r3, r4 162: 70c3 strb r3, [r0, #3] DMAC->QOSCTRL.bit.DQOS = 2; 164: 4b17 ldr r3, [pc, #92] ; (1c4 ) 166: 7b98 ldrb r0, [r3, #14] 168: 43b0 bics r0, r6 16a: 0006 movs r6, r0 16c: 2020 movs r0, #32 16e: 4330 orrs r0, r6 170: 7398 strb r0, [r3, #14] DMAC->QOSCTRL.bit.FQOS = 2; 172: 7b98 ldrb r0, [r3, #14] 174: 43a8 bics r0, r5 176: 4304 orrs r4, r0 178: 739c strb r4, [r3, #14] DMAC->QOSCTRL.bit.WRBQOS = 2; 17a: 7b98 ldrb r0, [r3, #14] 17c: 4388 bics r0, r1 17e: 4302 orrs r2, r0 180: 739a strb r2, [r3, #14] NVMCTRL->CTRLB.bit.MANW = 1; 182: 2380 movs r3, #128 ; 0x80 184: 4a10 ldr r2, [pc, #64] ; (1c8 ) 186: 6851 ldr r1, [r2, #4] 188: 430b orrs r3, r1 18a: 6053 str r3, [r2, #4] __libc_init_array(); 18c: 4b0f ldr r3, [pc, #60] ; (1cc ) 18e: 4798 blx r3 main(); 190: 4b0f ldr r3, [pc, #60] ; (1d0 ) 192: 4798 blx r3 while (1); 194: e7fe b.n 194 196: 46c0 nop ; (mov r8, r8) 198: 000002c0 .word 0x000002c0 19c: 20000000 .word 0x20000000 1a0: 20000000 .word 0x20000000 1a4: 0000027d .word 0x0000027d 1a8: 20000000 .word 0x20000000 1ac: 2000001c .word 0x2000001c 1b0: 0000028f .word 0x0000028f 1b4: 00000000 .word 0x00000000 1b8: e000ed00 .word 0xe000ed00 1bc: 410070fc .word 0x410070fc 1c0: 41005000 .word 0x41005000 1c4: 41004800 .word 0x41004800 1c8: 41004000 .word 0x41004000 1cc: 00000235 .word 0x00000235 1d0: 000001d5 .word 0x000001d5 000001d4
: void init_pin(int port, int pin) { uint32_t* dir_reg = (uint32_t*)((PORT_ADDR | (port * PORT_GROUP_SIZE) | PORT_DIR_OFF)); *dir_reg |= (1 << pin); 1d4: 4a13 ldr r2, [pc, #76] ; (224 ) 1d6: 4b14 ldr r3, [pc, #80] ; (228 ) 1d8: 6811 ldr r1, [r2, #0] } void clr_pin(int port, int pin) { uint32_t* out_reg = (uint32_t*)((PORT_ADDR | (port * PORT_GROUP_SIZE) | PORT_OUT_OFF)); *out_reg &= ~(1 << pin); 1da: 2080 movs r0, #128 ; 0x80 *dir_reg |= (1 << pin); 1dc: 430b orrs r3, r1 *out_reg &= ~(1 << pin); 1de: 2102 movs r1, #2 { 1e0: b530 push {r4, r5, lr} *dir_reg |= (1 << pin); 1e2: 6013 str r3, [r2, #0] *out_reg &= ~(1 << pin); 1e4: 4c11 ldr r4, [pc, #68] ; (22c ) 1e6: 4a12 ldr r2, [pc, #72] ; (230 ) 1e8: 05c0 lsls r0, r0, #23 1ea: 25fa movs r5, #250 ; 0xfa 1ec: 6813 ldr r3, [r2, #0] 1ee: 006d lsls r5, r5, #1 1f0: 438b bics r3, r1 1f2: 4303 orrs r3, r0 1f4: 6013 str r3, [r2, #0] { 1f6: 2364 movs r3, #100 ; 0x64 asm volatile("nop"); 1f8: 46c0 nop ; (mov r8, r8) for(i=0;i<100;i++) 1fa: 3b01 subs r3, #1 1fc: 2b00 cmp r3, #0 1fe: d1fb bne.n 1f8 for(;n>0;n--) 200: 3d01 subs r5, #1 202: 2d00 cmp r5, #0 204: d1f7 bne.n 1f6 *out_reg |= (1 << pin); 206: 25fa movs r5, #250 ; 0xfa *out_reg &= ~(1 << pin); 208: 6813 ldr r3, [r2, #0] *out_reg |= (1 << pin); 20a: 006d lsls r5, r5, #1 *out_reg &= ~(1 << pin); 20c: 4023 ands r3, r4 *out_reg |= (1 << pin); 20e: 430b orrs r3, r1 210: 6013 str r3, [r2, #0] *out_reg &= ~(1 << pin); 212: 2364 movs r3, #100 ; 0x64 asm volatile("nop"); 214: 46c0 nop ; (mov r8, r8) for(i=0;i<100;i++) 216: 3b01 subs r3, #1 218: 2b00 cmp r3, #0 21a: d1fb bne.n 214 for(;n>0;n--) 21c: 3d01 subs r5, #1 21e: 2d00 cmp r5, #0 220: d1f7 bne.n 212 222: e7e2 b.n 1ea 224: 41004480 .word 0x41004480 228: 40000002 .word 0x40000002 22c: bfffffff .word 0xbfffffff 230: 41004490 .word 0x41004490 00000234 <__libc_init_array>: 234: b570 push {r4, r5, r6, lr} 236: 2600 movs r6, #0 238: 4d0c ldr r5, [pc, #48] ; (26c <__libc_init_array+0x38>) 23a: 4c0d ldr r4, [pc, #52] ; (270 <__libc_init_array+0x3c>) 23c: 1b64 subs r4, r4, r5 23e: 10a4 asrs r4, r4, #2 240: 42a6 cmp r6, r4 242: d109 bne.n 258 <__libc_init_array+0x24> 244: 2600 movs r6, #0 246: f000 f82b bl 2a0 <_init> 24a: 4d0a ldr r5, [pc, #40] ; (274 <__libc_init_array+0x40>) 24c: 4c0a ldr r4, [pc, #40] ; (278 <__libc_init_array+0x44>) 24e: 1b64 subs r4, r4, r5 250: 10a4 asrs r4, r4, #2 252: 42a6 cmp r6, r4 254: d105 bne.n 262 <__libc_init_array+0x2e> 256: bd70 pop {r4, r5, r6, pc} 258: 00b3 lsls r3, r6, #2 25a: 58eb ldr r3, [r5, r3] 25c: 4798 blx r3 25e: 3601 adds r6, #1 260: e7ee b.n 240 <__libc_init_array+0xc> 262: 00b3 lsls r3, r6, #2 264: 58eb ldr r3, [r5, r3] 266: 4798 blx r3 268: 3601 adds r6, #1 26a: e7f2 b.n 252 <__libc_init_array+0x1e> 26c: 000002ac .word 0x000002ac 270: 000002ac .word 0x000002ac 274: 000002ac .word 0x000002ac 278: 000002b0 .word 0x000002b0 0000027c : 27c: 2300 movs r3, #0 27e: b510 push {r4, lr} 280: 429a cmp r2, r3 282: d100 bne.n 286 284: bd10 pop {r4, pc} 286: 5ccc ldrb r4, [r1, r3] 288: 54c4 strb r4, [r0, r3] 28a: 3301 adds r3, #1 28c: e7f8 b.n 280 0000028e : 28e: 0003 movs r3, r0 290: 1882 adds r2, r0, r2 292: 4293 cmp r3, r2 294: d100 bne.n 298 296: 4770 bx lr 298: 7019 strb r1, [r3, #0] 29a: 3301 adds r3, #1 29c: e7f9 b.n 292 ... 000002a0 <_init>: 2a0: b5f8 push {r3, r4, r5, r6, r7, lr} 2a2: 46c0 nop ; (mov r8, r8) 2a4: bcf8 pop {r3, r4, r5, r6, r7} 2a6: bc08 pop {r3} 2a8: 469e mov lr, r3 2aa: 4770 bx lr 000002ac <__frame_dummy_init_array_entry>: 2ac: 00dd 0000 .... 000002b0 <_fini>: 2b0: b5f8 push {r3, r4, r5, r6, r7, lr} 2b2: 46c0 nop ; (mov r8, r8) 2b4: bcf8 pop {r3, r4, r5, r6, r7} 2b6: bc08 pop {r3} 2b8: 469e mov lr, r3 2ba: 4770 bx lr 000002bc <__do_global_dtors_aux_fini_array_entry>: 2bc: 00b5 0000 ....